Silicon wafer carrier and pecvd reaction chamber

Abstract

The present application provides a silicon wafer carrier and a PECVD reaction chamber. The silicon wafer carrier comprises an insulating frame and an electrode frame nested outside the insulating frame, the insulating frame comprises opposite first and second insulating walls, and the first and second insulating walls are further provided with corresponding first and second electrodes for carrying silicon wafers, the first electrode extends outward from the first insulating wall and is connected with a first bus bar on one side of the electrode frame, and the second electrode extends outward from the second insulating wall and is connected with a second bus bar, the second bus bar is insulated from the electrode frame and is arranged between the electrode frame and the insulating frame. The silicon wafer carrier of the present application can carry silicon wafers outside the PECVD reaction chamber to reduce the use of silicon wafer baskets, can carry out plasma discharge in the chamber, and can accommodate more silicon wafers in the reaction chamber at the same time, thereby improving the production capacity of the PECVD process.

Description

Technical Field

[0001] This invention relates to the field of solar cell manufacturing, and particularly to silicon wafer carriers and PECVD reaction chambers. Background Technology

[0002] Thin-film / crystalline silicon heterojunction solar cells (hereinafter referred to as heterojunction solar cells, also known as HIT or SHJ solar cells) belong to the third generation of high-efficiency solar cell technology. They combine the advantages of first-generation crystalline silicon and second-generation thin-film silicon, featuring high conversion efficiency and low temperature coefficient. In particular, bifacial heterojunction solar cells can achieve conversion efficiencies exceeding 26%, demonstrating broad market prospects. Tunneling oxide passivated contact (TOPCon) technology involves fabricating an ultrathin tunneling oxide layer and a highly doped polycrystalline silicon thin layer on the back of the cell. TOPCon cells are also one of the future development directions for high-efficiency solar cells.

[0003] Both TOPCON and HJT battery manufacturing processes utilize equipment such as plasma-enhanced chemical vapor deposition (PECVD) to deposit amorphous / microcrystalline silicon layers. Before depositing the amorphous / microcrystalline silicon layer via PECVD, silicon wafers that have completed the previous process are stacked in a wafer basket. An automated unloading device places the stacked wafers from the wafer basket into a wafer carrier or tray, and then the wafer carrier is transferred to the PECVD reaction chamber. The PECVD reaction chamber is then evacuated, reactive gases are injected, and an RF power supply is turned on to generate plasma, thereby depositing amorphous / microcrystalline silicon onto the silicon wafer.

[0004] Existing silicon wafer carriers are typically flat graphite plates, with each carrier usually comprising multiple wafer-bearing areas on the same plane, each holding one silicon wafer. However, existing silicon wafer carriers cannot replace wafer baskets for directly loading wafers from the previous process, and they also limit the number of wafers that can simultaneously enter the reaction chamber, thus restricting further increases in production capacity.

[0005] Therefore, how to provide a silicon wafer carrier and PECVD reaction chamber that can both transport silicon wafers outside the chamber to reduce the use of silicon wafer baskets, and perform plasma discharge inside the chamber, while also accommodating more silicon wafers simultaneously in the reaction chamber, thereby increasing the production capacity of the PECVD process, has become a technical problem that urgently needs to be solved in the industry. Summary of the Invention

[0006] To address the aforementioned problems of the prior art, the present invention proposes a silicon wafer carrier, comprising an insulating frame and an electrode frame nested outside the insulating frame. The insulating frame includes a first insulating wall and a second insulating wall opposite to each other. A first electrode and a second electrode for carrying the silicon wafer are correspondingly and crosswise disposed on the first insulating wall and the second insulating wall. The first electrode extends outward from the first insulating wall and is connected to a first busbar on one side of the electrode frame. The second electrode extends outward from the second insulating wall and is connected to a second busbar. The second busbar is insulated from the electrode frame and disposed between the electrode frame and the insulating frame.

[0007] In one embodiment, the first electrode includes a first electrode sheet and a second electrode sheet that are separated and respectively connected to the first insulating wall and the second insulating wall. The first electrode sheet is connected to the first busbar. The second electrode includes a third electrode sheet and a fourth electrode sheet that are separated and respectively connected to the first insulating wall and the second insulating wall. The fourth electrode sheet is connected to the second busbar. The first electrode sheet and the third electrode sheet are arranged intersectingly on the first insulating wall, and the second electrode sheet and the fourth electrode sheet are arranged intersectingly on the second insulating wall.

[0008] In one embodiment, the first electrode is a first electrode plate that passes through the second insulating wall and is connected to the first busbar, and the second electrode is a second electrode plate that passes through the first insulating wall and is connected to the second busbar.

[0009] In one embodiment, the insulating frame is a polypropylene frame or a polytetrafluoroethylene frame, the first insulating wall and the second insulating wall are a first polypropylene wall and a second polypropylene wall, or the first insulating wall and the second insulating wall are a first polytetrafluoroethylene wall and a second polytetrafluoroethylene wall, the electrode frame is a graphite frame or an aluminum frame, and the first busbar and the second busbar are both graphite busbars or aluminum busbars.

[0010] In one embodiment, the first bus and the second bus are respectively located on both sides of the insulating frame. The electrode frame has an opening covered with an insulating plug on the opposite side of the first bus. The second bus is connected to a first connector that extends through the insulating plug and out of the opening. The electrode frame has a second connector that is insulated from the first connector around the insulating plug. The first connector and the second connector form a power plug.

[0011] In one embodiment, the first electrode is disposed at the bottom of the insulating frame and is connected to the bottom of the electrode frame, and the second electrode is disposed at the top of the insulating frame and is spaced apart from the top of the electrode frame.

[0012] The present invention also provides a PECVD reaction chamber, including a substrate for placing a plurality of silicon wafer carriers, wherein the plurality of silicon wafer carriers are a plurality of silicon wafer carriers as described in any of the preceding claims, the PECVD reaction chamber including an RF power supply having an output terminal and a ground terminal, wherein either a first bus or a second bus of each silicon wafer carrier is electrically connected to the output terminal, and the other is electrically connected to the ground terminal.

[0013] In one embodiment, the PECVD reaction chamber further includes a plurality of power sockets disposed on its sidewalls, each power socket having a third connector and a fourth connector, the positions of the power sockets being matched with a power plug formed by a first connector and a second connector.

[0014] In one embodiment, the first bus and the second bus are electrically connected to the first connector and the second connector of the power plug, respectively, and the third connector and the fourth connector of the power socket are electrically connected to the output terminal and the ground terminal, respectively. The first bus and the second bus are powered through the electrical connection between the power plug and the power socket.

[0015] In one embodiment, three to five silicon wafer carriers loaded with silicon wafers are placed on the substrate of the PECVD reaction chamber to perform PECVD processes simultaneously. Adjacent silicon wafers are electrically connected to the output terminal of the RF power supply and the ground terminal, respectively, so as to generate plasma between adjacent silicon wafers.

[0016] Compared to existing technologies that use flat graphite carriers to carry silicon wafers and feed them into the plasma reaction chamber, resulting in lower throughput, the silicon wafer carrier of this invention includes an insulating frame and an electrode frame nested outside the insulating frame. The insulating frame includes opposing first and second insulating walls, on which first and second electrodes for carrying silicon wafers are correspondingly and crosswise arranged. The first electrode extends outward from the first insulating wall and connects to a first busbar on one side of the electrode frame, and the second electrode extends outward from the second insulating wall and connects to a second busbar. The second busbar is insulated from the electrode frame and is disposed between the electrode frame and the insulating frame. This invention enables the silicon wafer carrier to both carry silicon wafers outside the PECVD reaction chamber, reducing the use of silicon wafer baskets, and perform plasma discharge inside the chamber, while also allowing the reaction chamber to accommodate more silicon wafers simultaneously, thereby increasing the throughput of the PECVD process. Attached Figure Description

[0017] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0018] Figure 1 This is a schematic diagram of the composition structure of the silicon wafer carrier of the present invention in the first embodiment;

[0019] Figure 2 For the present invention, wherein the following is placed Figure 1 A schematic diagram of the composition and structure of the PECVD reaction chamber of a silicon wafer carrier;

[0020] Figure 3 for Figure 1 A schematic diagram of the composition of the power module 3 used to supply power to the silicon wafer carrier; and

[0021] Figure 4 This is a schematic diagram of the composition structure of the second embodiment of the silicon wafer carrier of the present invention. Detailed Implementation Plan

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments to provide a clearer understanding of its objectives, features, and advantages. It should be understood that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way. Unless the context clearly indicates otherwise, the singular forms “a” and “described” include plural references. The terms “first,” “second,” and similar terms as used in this specification and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0023] Figure 1 This is a schematic diagram of the structural composition of a first embodiment of the silicon wafer carrier of the present invention. The silicon wafer carrier 1 includes an electrode frame 10 and an insulating frame 11, with the electrode frame 10 nested outside the insulating frame 11. The components of the silicon wafer carrier 1 will be described in detail below.

[0024] The insulating frame 11 includes a first insulating wall 110 and a second insulating wall 112 facing each other, which are connected at their ends to form a space for accommodating a silicon wafer. A first electrode 13 and a second electrode 14 for supporting the silicon wafer are also correspondingly and intersectingly arranged on the first insulating wall 110 and the second insulating wall 112. The first electrode 13 extends outward from the first insulating wall 110 and connects to a first busbar 100 on one side of the electrode frame 10. The second electrode 14 extends outward from the second insulating wall 112 and connects to a second busbar 12. The second busbar 12 is insulated from the electrode frame 10 and is disposed between the electrode frame 10 and the insulating frame 11.

[0025] In this embodiment, the first electrode 13 includes a separate first electrode piece 130 and a second electrode piece 132, which are respectively connected to the first insulating wall 110 and the second insulating wall 112. The first electrode piece 130 is connected to the first busbar 100. In this embodiment, the second electrode 14 includes a separate third electrode piece 140 and a fourth electrode piece 142, which are respectively connected to the first insulating wall 110 and the second insulating wall 112. The fourth electrode piece 142 is connected to the second busbar 12. The first electrode piece 130 and the third electrode piece 140 are arranged crosswise on the first insulating wall 110, and the second electrode piece 132 and the fourth electrode piece 142 are arranged crosswise on the second insulating wall 112.

[0026] The insulating frame 11 is a polypropylene frame or a polytetrafluoroethylene frame. The first insulating wall 110 and the second insulating wall 112 are a first polypropylene wall and a second polypropylene wall, respectively. Alternatively, the first insulating wall 110 and the second insulating wall 112 can be a first polytetrafluoroethylene wall and a second polytetrafluoroethylene wall. The electrode frame 10 is a graphite frame or an aluminum frame. The first busbar 100 and the second busbar 12 are respectively a graphite busbar or an aluminum busbar.

[0027] like Figure 1 As shown, the first busbar 100 and the second busbar 12 are located on both sides of the insulating frame 11. The electrode frame 10 has an opening on the side opposite to the first busbar 100, which is covered by an insulating plug 15. The second busbar 12 is connected to a first connector 160 that extends through the insulating plug 15 and out of the opening. The electrode frame 10 has a second connector 162 that is insulated from the first connector 160 around the insulating plug 15. The first connector 160 and the second connector 162 form a power plug 16.

[0028] like Figure 1 As shown, the first electrode 13 is disposed at the bottom of the insulating frame 11 and is connected to the bottom of the electrode frame 10. The second electrode 14 is disposed at the top of the insulating frame 11 and is spaced apart from the top of the electrode frame 10.

[0029] Figure 2 This describes the structural composition of the PECVD reaction chamber 2 of the present invention. For example... Figure 2 As shown, the PECVD reaction chamber 2 includes a substrate 22, which is used to place multiple... Figure 1 or Figure 4The silicon wafer carrier 1 or 1”, the PECVD reaction chamber 2 includes an RF power supply 3 having an output terminal 30 and a ground terminal G. Either the first bus 100 or the second bus 12 of each silicon wafer carrier 1 is electrically connected to the output terminal 30, and the other is electrically connected to the ground terminal G.

[0030] Three to five silicon wafer carriers 2, each carrying a silicon wafer 4, are simultaneously placed on the substrate 22 of the PECVD reaction chamber 2 for simultaneous PECVD processing. Adjacent silicon wafers 4 are electrically connected to the output terminal 30 of the RF power supply 3 and the ground terminal G, respectively, to generate plasma between adjacent silicon wafers 4. Figure 2 In the embodiment of the PECVD reaction chamber 2 shown, three silicon wafer carriers 2, each loaded with a silicon wafer 4, are placed on the substrate 22 simultaneously.

[0031] like Figure 3 As shown, it displays as Figure 1 The diagram illustrates the structural composition of the power module 3 used to power the silicon wafer carrier 1. The PECVD reaction chamber 2 also includes multiple power sockets 30 that can be disposed on the side wall of the PECVD reaction chamber 2. Each power socket 30 has a third connector 300 and a fourth connector 304, which are insulated by an insulating pad 302 and electrically connected to the output terminal 30 and ground terminal G of the RF power supply 3, respectively. The positions of the multiple power sockets 30 correspond to the power plug 16 formed by the first connector 160 and the second connector 162.

[0032] Figure 1 The first busbar 100 and the second busbar 12 are electrically connected to the first connector 160 and the second connector 162 of the power plug 16, respectively. The third connector 300 and the fourth connector 304 of the power socket 30 are electrically connected to the output terminal 30 and the ground terminal G, respectively. The first busbar 100 and the second busbar 12 are powered through the electrical connection between the power plug 16 and the power socket 30.

[0033] Figure 4 This is a schematic diagram of the structural composition of a second embodiment of the silicon wafer carrier of the present invention. The second embodiment of the silicon wafer carrier is compared with... Figure 1 The difference in the first embodiment of the silicon wafer carrier lies in whether the first electrode 13 or 13” and the second electrode 14 or 14” are separate structures. Figure 1 In the first embodiment of the silicon wafer carrier, the first electrode 13 and the second electrode 14 are separate structures. Figure 4 In the second embodiment of the silicon wafer carrier, the first electrode 13” and the second electrode 14” are each an integral structure with a non-separable structure.

[0034] like Figure 4As shown, the first electrode 13” of the silicon wafer carrier 1” is a first electrode plate that passes through the second insulating wall 112 and the first insulating wall 110 and is connected to the first busbar 100. The second electrode 14” is a second electrode plate that passes through the first insulating wall 110 and the second insulating wall 112 and is connected to the second busbar 12. The first electrode plate and the second electrode plate are arranged crosswise and are respectively connected to the first busbar 100 and the second busbar 12.

[0035] This invention is in Figure 2 Before the PECVD process, the PECVD reaction chamber 2 can directly place the silicon wafer 4, which has completed the previous process before PECVD, onto the first electrode 13 and the second electrode 14 between the first insulating wall 110 and the second insulating wall 112. If producing HJT cells, the previous process is a texturing and cleaning process; if producing TOPCon cells, the previous process is an etching process. In the prior art, a first automated wafer unloading device inserts the silicon wafer that has completed the previous process into a silicon wafer basket, and then a second automated wafer unloading device places the silicon wafer basket into a silicon wafer carrier. This invention can use only one automated wafer unloading device to insert the silicon wafer 4, which has completed the previous process, into the silicon wafer carrier 1 or 1”, thereby saving a batch of silicon wafer baskets and one automated device. Then, the silicon wafer carrier 1 or 1” carrying the silicon wafer 4 is placed into the PECVD reaction chamber 2. After that, the PECVD reaction chamber 2 is evacuated, the reaction gas is injected, and the radio frequency power supply 3 is turned on. The adjacent first electrode 13 and second electrode 14 are electrically connected to the output terminal 300 and the ground terminal G of the radio frequency power supply 3, respectively, thereby generating plasma between them, and then depositing amorphous silicon / microcrystalline silicon on the silicon wafer 4.

[0036] The silicon wafer carrier of the present invention includes an insulating frame and an electrode frame nested outside the insulating frame. The insulating frame includes a first insulating wall and a second insulating wall opposite to each other. A first electrode and a second electrode for carrying the silicon wafer are correspondingly and crosswise disposed on the first insulating wall and the second insulating wall. The first electrode extends outward from the first insulating wall and connects to a first busbar on one side of the electrode frame. The second electrode extends outward from the second insulating wall and connects to a second busbar. The second busbar is insulated from the electrode frame and disposed between the electrode frame and the insulating frame. This invention enables the silicon wafer carrier to both transport silicon wafers outside the PECVD reaction chamber, reducing the use of silicon wafer baskets, and perform plasma discharge inside the chamber, while also allowing more silicon wafers to be accommodated simultaneously in the reaction chamber, thereby increasing the throughput of the PECVD process.

[0037] The above embodiments are provided for those skilled in the art to implement or use the present invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope that conforms to the innovative features mentioned in the claims.

Claims

1. A silicon wafer carrier, characterized by, The electrode frame is nested outside the insulating frame, the insulating frame comprises opposite first and second insulating walls, and the first and second insulating walls are further provided with first and second electrodes corresponding to each other for carrying silicon wafers, the first electrode extends outward from the first insulating wall and is connected with a first busbar on one side of the electrode frame, and the second electrode extends outward from the second insulating wall and is connected with a second busbar, which is insulated from the electrode frame and is arranged between the electrode frame and the insulating frame.

2. The silicon wafer carrier of claim 1, wherein, The first electrode comprises first and second electrode pieces separately connected to the first and second insulating walls, the first electrode piece is connected with the first busbar, and the second electrode comprises third and fourth electrode pieces separately connected to the first and second insulating walls, the fourth electrode piece is connected with the second busbar, the first and third electrode pieces are arranged on the first insulating wall in a cross manner, and the second and fourth electrode pieces are arranged on the second insulating wall in a cross manner.

3. The silicon wafer carrier of claim 1, wherein, The first electrode is a first electrode plate connected to the first busbar through the first insulating wall from the second insulating wall, and the second electrode is a second electrode plate connected to the second busbar through the second insulating wall from the first insulating wall.

4. The silicon wafer carrier of claim 1, wherein, The insulating frame is a polypropylene frame or a polytetrafluoroethylene frame, the first and second insulating walls are first and second polypropylene walls, or the first and second insulating walls are first and second polytetrafluoroethylene walls, the electrode frame is a graphite frame or an aluminum frame, and the first and second busbars are graphite busbars or aluminum busbars.

5. The silicon wafer carrier of claim 1, wherein, The first and second busbars are respectively located on two sides of the insulating frame, the electrode frame is provided with an opening on the other side opposite to the first busbar, an insulating plug covers the opening, a first connector is connected to the second busbar and extends out of the opening through the insulating plug, a second connector is arranged around the insulating plug and is insulated from the first connector, and the first and second connectors form a power plug.

6. The silicon wafer carrier of claim 1, wherein, The first electrode is arranged at the bottom of the insulating frame and connected with the bottom of the electrode frame, and the second electrode is arranged at the top of the insulating frame and spaced apart from the top of the electrode frame.

7. A PECVD reaction chamber comprising a substrate for placing a plurality of silicon wafer carriers, characterized in that, The plurality of silicon wafer carriers are a plurality of silicon wafer carriers as claimed in any one of claims 1 to 6, the PECVD reaction chamber comprises a radio frequency power supply having an output end and a ground end, and any one of the first busbar or the second busbar of each silicon wafer carrier is electrically connected with the output end, and the other is electrically connected with the ground end.

8. The PECVD reaction chamber of claim 7, wherein, The PECVD reaction chamber further comprises a plurality of power sockets arranged on the sidewall thereof, each power socket has a third connector and a fourth connector, and the position of the power socket matches the power plug formed by the first and second connectors.

9. The PECVD reaction chamber of claim 8, wherein, The first bus bar and the second bus bar are electrically connected with the first terminal and the second terminal of the power plug respectively, and the third terminal and the fourth terminal of the power socket are electrically connected with the output terminal and the ground terminal respectively, so that the first bus bar and the second bus bar are powered through the electrical connection between the power plug and the power socket.

10. The PECVD reaction chamber of claim 7, wherein, The PECVD reaction cavity is used for simultaneously placing 3-5 silicon wafer carriers loaded with silicon wafers on a substrate to simultaneously perform a PECVD process, and adjacent silicon wafers are electrically connected with output terminals and ground terminals of a radio frequency power source respectively to generate plasma between the adjacent silicon wafers.

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