Fpga global reset synchronization circuit, chip, verification simulation system and method

Abstract

The application discloses a FPGA global reset synchronization circuit, a chip, a verification simulation system and a method. The FPGA global reset synchronization circuit comprises a clock signal channel and a reset signal channel. The clock signal channel comprises a filter and a frequency multiplier. The filter is used for filtering an input first clock signal, the frequency multiplier is used for frequency multiplication after the filtering, a second clock signal is generated, the frequency of the second clock signal is an integer multiple of the first clock signal, and the second clock signal is output to provide a clock signal for user logic in the FPGA chip. The reset signal channel comprises a cross-clock-domain transmission circuit. The cross-clock-domain transmission circuit is used for outputting an input reset signal after the cross-clock-domain transmission to provide a global reset signal for the user logic in the FPGA chip. The application does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when the FPGAs are used for chip verification and simulation.

Description

Technical Field

[0001] This invention relates to a multi-FPGA chip verification and simulation system, specifically to an FPGA global reset synchronization circuit, chip, verification and simulation system, and method. Background Technology

[0002] When using FPGAs for chip verification and simulation, because the logic resources of a single FPGA chip are limited, the chip is usually divided into multiple parts, and each part is deployed on multiple FPGAs (for example, there are usually close to one hundred FPGAs). This requires that the FPGAs maintain synchronization during operation, as if they were on a single chip, with reset signal synchronization being the most important aspect. Reset synchronization requires that the reset signal be transmitted to all FPGAs within one clock cycle. However, FPGAs typically operate at relatively high clock frequencies (e.g., 50MHz), meaning that the reset signal must reach all FPGAs in a very short time (no more than 20ns). Due to the large number of FPGAs and the considerable distances between them, as well as the distance from the reset signal source to the FPGA (tens of centimeters to several meters), it is difficult to achieve reset synchronization by adjusting the length of the signal lines. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an FPGA global reset synchronization circuit, chip, verification simulation system and method to address the above-mentioned problems of the prior art. The present invention is not dependent on the distance of the FPGA and the length of the signal line, and is particularly suitable for clock reset synchronization of a large number of FPGAs when using FPGA for chip verification and simulation.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] An FPGA global reset synchronization circuit based on fast and slow clocks is characterized by comprising a clock signal channel and a reset signal channel. The clock signal channel includes a filter and a frequency multiplier, used to filter the input first clock signal and multiply its frequency by the frequency multiplier to generate a second clock signal whose frequency is an integer multiple of the first clock signal, and output the second clock signal to provide a clock signal for user logic in the FPGA chip. The reset signal channel includes a cross-clock domain transmission circuit, used to output the input reset signal after passing through the cross-clock domain transmission circuit to provide a global reset signal for user logic in the FPGA chip.

[0006] Optionally, the cross-clock domain transmission circuit includes four registers: a first register, a second register, a third register, and a fourth register, cascaded in sequence. The first and second registers use a first clock signal, while the third and fourth registers use a second clock signal. The first register serves as the reset register of the FPGA chip, used to sample the reset signal from the reset signal transmission network at the rising edge of the first clock signal and transmit it to the second register. The second register is used to sample the reset signal transmitted by the first register at the rising edge of the first clock signal and transmit it to the third register, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the sampling of the first register. The third register is used to sample the reset signal transmitted by the second register at the rising edge of the second clock signal and transmit it to the fourth register. The fourth register is used to sample the reset signal transmitted by the third register at the rising edge of the second clock signal and transmit it to the user logic as a global reset signal, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the sampling of the third register.

[0007] Optionally, the rising edge of the second clock signal is delayed by a time Δt compared to the rising edge of the first clock signal, and the time Δt satisfies the following constraint:

[0008] Δt≥t cqd +t setup

[0009] Among them, t cqd t is the time difference in a cross-clock domain transmission circuit from the rising edge of the clock in the second register to the propagation of the reset signal to the input of the third register. setup This refers to the setup time of the third register in the cross-clock domain transmission circuit.

[0010] Furthermore, the present invention also provides an FPGA chip, including an FPGA chip body with user logic, wherein the FPGA chip body is provided with a first clock signal pin and a reset signal pin, and the FPGA chip body is provided with the aforementioned FPGA global reset synchronization circuit based on fast and slow clocks, wherein the first clock signal pin is connected to the input terminal of the clock signal channel, and the reset signal pin is connected to the input terminal of the reset signal channel.

[0011] Furthermore, the present invention also provides a multi-FPGA chip verification and simulation system, comprising:

[0012] Multiple FPGA chips,

[0013] The reset control unit is used to generate the first clock signal and the reset signal.

[0014] A synchronous clock transmission network is used to synchronously transmit the first clock signal to each FPGA chip.

[0015] And a reset signal transmission network, used to transmit the reset signal to each FPGA chip in one cycle;

[0016] The clock signal output terminal of the reset control unit is connected to the first clock signal pin of each FPGA chip through a synchronous clock transmission network, and the reset signal output terminal of the reset control unit is connected to the reset signal pin of each FPGA chip through a reset signal transmission network.

[0017] Optionally, the transmission cable lengths between the clock signal output terminal of the reset control unit and the first clock signal pins of each FPGA chip in the synchronous clock transmission network are the same or the deviation is within a set value.

[0018] Optionally, the transmission cable lengths between the reset signal output terminal of the reset control unit and the reset signal pins of each FPGA chip in the reset signal transmission network are the same or the deviation is within a set value.

[0019] Furthermore, the present invention also provides an application method for the aforementioned multi-FPGA chip verification simulation system, comprising:

[0020] S101 generates a first clock signal and a reset signal through the reset control unit;

[0021] S102, the first clock signal is synchronously transmitted to each FPGA chip through the synchronous clock transmission network, and the reset signal is transmitted to each FPGA chip within one cycle through the reset signal transmission network.

[0022] S103, in each FPGA chip, the input first clock signal is filtered by a filter and multiplied by a frequency multiplier through the clock signal channel to generate a second clock signal, and the second clock signal is output to provide a clock signal for the user logic in the FPGA chip; at the same time, the input reset signal is transmitted through the reset signal channel, including the cross-clock domain transmission circuit, and output to provide a global reset signal for the user logic in the FPGA chip, thereby realizing global reset synchronization of each FPGA chip.

[0023] Optionally, when generating the first clock signal and the reset signal through the reset control unit in step S101, it means that the reset signal is generated based on the rising edge of the first clock signal.

[0024] Optionally, in step S101, when the first clock signal and the reset signal are generated by the reset control unit, the period T of the generated first clock signal is... c The following constraints must be met:

[0025] T c≥t cq +t rd +t setup -t cd +t skew

[0026] In the above formula, t cq To reset the control unit, the time difference from the rising edge of the first clock signal to the output reset signal, t rd To reset the signal propagation delay of the signal transmission network, t setup t represents the setup time of the reset register in the FPGA chip. cd For the signal propagation delay of the synchronous clock transmission network, t skew The skew caused by transmitting clock signals to a synchronous clock transmission network.

[0027] Compared with the prior art, the present invention has the following advantages: The reset source signal of the FPGA global reset synchronization circuit based on fast and slow clocks is generated according to the slow clock (first clock signal). The clock period of the slow clock is set to be large enough to ensure that the reset signal can reach all FPGAs within one clock cycle. On the FPGA, the slow clock is multiplied into a fast clock (second clock signal) to drive the logic. The reset signal is transmitted to the running logic through a cross-clock domain circuit, thereby realizing reset synchronization. The present invention does not depend on the distance of the FPGA and the length of the signal line, and is especially suitable for clock reset synchronization of a large number of FPGAs when using FPGAs for chip verification and simulation. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the FPGA global reset synchronization circuit and its interface with the FPGA chip in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram illustrating the parameter definition principle for time Δt satisfying constraints in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the multi-FPGA chip verification simulation system in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram illustrating the parameter definition principle of the timing constraint of the first clock signal in an embodiment of the present invention. Detailed Implementation

[0032] like Figure 1As shown, this embodiment provides an FPGA global reset synchronization circuit based on fast and slow clocks, including a clock signal channel and a reset signal channel. The clock signal channel includes a filter and a frequency multiplier, used to filter the input first clock signal and multiply it by the frequency multiplier to generate a second clock signal whose frequency is an integer multiple of the first clock signal. The second clock signal is then output to provide a clock signal for the user logic in the FPGA chip. The reset signal channel includes a cross-clock domain transmission circuit, used to output the input reset signal after passing through the cross-clock domain transmission circuit to provide a global reset signal for the user logic in the FPGA chip. In this embodiment, the reset source signal of the FPGA global reset synchronization circuit is generated based on a slow clock (first clock signal). The clock period of the slow clock is set to be sufficiently large to ensure that the reset signal can reach all FPGAs within one clock cycle. On the FPGA, the slow clock is multiplied to a fast clock (second clock signal) to drive the logic. The reset signal is transmitted to the running logic through the cross-clock domain circuit, thereby achieving reset synchronization.

[0033] As an optional implementation, the filters and frequency multipliers in this embodiment are implemented using a Digital Clock Manager (DCM). Other filters and frequency multipliers can also be used as needed. The slow clock is filtered by the first DCM and multiplied by the second DCM to generate a fast clock. Because the slow clock signals received by each FPGA are synchronized, the fast clocks generated by each FPGA are also synchronized. After the reset signal arrives at the node, it is traversed from the slow clock signal domain to the fast clock signal domain of the actual driving logic within the FPGA via a cross-clock domain circuit. By appropriately setting the period ratio and phase deviation of the fast and slow clocks, the reset signal is ensured to be synchronously acquired by the fast clock at a predetermined time, thereby achieving global synchronization of the reset signal.

[0034] like Figure 1As shown, the cross-clock domain transmission circuit includes four registers (represented by FF in the figure): a first register, a second register, a third register, and a fourth register, which are cascaded in sequence. The first and second registers use the first clock signal, while the third and fourth registers use the second clock signal. The first register serves as the reset register of the FPGA chip, used to sample the reset signal from the reset signal transmission network on the rising edge of the first clock signal and transmit it to the second register. The second register is used to sample the reset signal transmitted by the first register on the rising edge of the first clock signal and transmit it to the third register, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the sampling of the first register. The third register is used to sample the reset signal transmitted by the second register on the rising edge of the second clock signal and transmit it to the fourth register. The fourth register is used to sample the reset signal transmitted by the third register on the rising edge of the second clock signal and transmit it to the user logic as a global reset signal, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the sampling of the third register.

[0035] In this embodiment, the rising edge of the second clock signal is delayed by a time Δt compared to the rising edge of the first clock signal, and the time Δt satisfies the following constraint:

[0036] Δt≥t cqd +t setup

[0037] Among them, t cqd t is the time difference in a cross-clock domain transmission circuit from the rising edge of the clock in the second register to the propagation of the reset signal to the input of the third register. setup The setup time of the third register in the cross-clock domain transmission circuit is defined as follows: Figure 2 As shown.

[0038] like Figure 1 As shown, this embodiment also provides an FPGA chip, including an FPGA chip body with user logic (the user logic is a user-defined processing module of the FPGA; in this embodiment, the specific processing content and implementation of the processing module are not relevant). The FPGA chip body is provided with a first clock signal pin and a reset signal pin. Figure 1 The two interfaces in the text are the interfaces corresponding to the two pins here. The FPGA chip body is equipped with the aforementioned FPGA global reset synchronization circuit based on fast and slow clocks. The first clock signal pin is connected to the input terminal of the clock signal channel, and the reset signal pin is connected to the input terminal of the reset signal channel.

[0039] like Figure 3 As shown, this embodiment also provides a multi-FPGA chip verification and simulation system, including:

[0040] n of the aforementioned FPGA chips, Figure 3 FPGA1 to FPGA n ,

[0041] The reset control unit is used to generate the first clock signal and the reset signal.

[0042] A synchronous clock transmission network is used to synchronously transmit the first clock signal to each FPGA chip.

[0043] And a reset signal transmission network, used to transmit the reset signal to each FPGA chip in one cycle;

[0044] The clock signal output of the reset control unit is connected to the first clock signal pin of each FPGA chip via a synchronous clock transmission network. Similarly, the reset signal output of the reset control unit is connected to the reset signal pin of each FPGA chip via a reset signal transmission network. It should be noted that the number of FPGA chips, n, can be selected as needed, with a minimum of one (a special case of a single FPGA chip) and a maximum determined based on the FPGA chip verification and simulation requirements.

[0045] In this embodiment, the transmission cable lengths between the clock signal output terminal of the reset control unit and the first clock signal pin of each FPGA chip in the synchronous clock transmission network are the same (or the deviation is within a set value). Through the above optimization, the multi-FPGA chip verification simulation system in this embodiment can be compatible with the distance difference between each FPGA chip.

[0046] In this embodiment, the transmission cable lengths between the reset signal output terminal of the reset control unit and the reset signal pins of each FPGA chip in the reset signal transmission network are the same (or the deviation is within a set value). Through the above optimization, the multi-FPGA chip verification simulation system in this embodiment can be compatible with the distance difference between each FPGA chip.

[0047] This embodiment also provides an application method for the aforementioned multi-FPGA chip verification simulation system, including:

[0048] S101 generates a first clock signal and a reset signal through the reset control unit;

[0049] S102, the first clock signal is synchronously transmitted to each FPGA chip through the synchronous clock transmission network, and the reset signal is transmitted to each FPGA chip within one cycle through the reset signal transmission network.

[0050] S103, in each FPGA chip, the input first clock signal is filtered by a filter and multiplied by a frequency multiplier through the clock signal channel to generate a second clock signal, and the second clock signal is output to provide a clock signal for the user logic in the FPGA chip; at the same time, the input reset signal is transmitted through the reset signal channel, including the cross-clock domain transmission circuit, and output to provide a global reset signal for the user logic in the FPGA chip, thereby realizing global reset synchronization of each FPGA chip.

[0051] In this embodiment, when the first clock signal and the reset signal are generated by the reset control unit in step S101, it means that the reset signal is generated based on the rising edge of the first clock signal.

[0052] The slow clock signal is transmitted through a synchronous clock transmission network to ensure that each FPGA receives a synchronized slow clock signal. The period of the slow clock signal should be set large enough to ensure that the reset signal reaches the reset synchronization registers of all FPGAs in the system within one clock cycle, satisfying the corresponding timing constraints, thereby ensuring that all FPGA nodes are sampled synchronously by the slow clock. Its timing constraints are as follows: Figure 4 As shown. Where CLK_a is the clock source signal, CLK_b is the clock signal received by the FPGA's clock interface, RST_a is the reset source signal, and RST_b is the reset signal received by the FPGA's reset interface; T c It is the period of a slow clock, t cd For the signal propagation delay of the synchronous clock transmission network, t cq t is the time difference between the rising edge of the clock and the output reset signal of the CPLD. rd To reset the signal propagation delay of the signal transmission network, t setup This is the setup time for the FPGA reset register. Considering the skewness t caused by the clock signal transmitted through the synchronous clock transmission network... skew In this embodiment, when the first clock signal and the reset signal are generated by the reset control unit in step S101, the period T of the generated first clock signal is... c The following constraints must be met:

[0053] T c ≥t cq +t rd +t setup -t cd +t skew

[0054] In the above formula, t cq To reset the control unit, the time difference from the rising edge of the first clock signal to the output reset signal, t rd To reset the signal propagation delay of the signal transmission network, t setupt represents the setup time of the reset register in the FPGA chip. cd For the signal propagation delay of the synchronous clock transmission network, t skew The skew caused by transmitting clock signals to a synchronous clock transmission network.

[0055] In summary, this embodiment employs a combination of fast and slow clocks. The reset source signal first passes through the CPLD on the reset board, and is filtered and synchronized at the first stage by a globally synchronized slow clock signal. Then, it reaches the reset pin of each FPGA chip via the reset transmission network. The slow clock signal is transmitted through the synchronous clock transmission network to ensure that each FPGA receives the synchronized slow clock signal. The period of the slow clock signal should be set sufficiently large to ensure that the reset signal reaches the reset synchronization registers of all FPGAs in the system within one clock cycle, satisfying the corresponding timing constraints, thereby ensuring that all FPGA nodes are sampled synchronously by the slow clock. The reset signal transmission network needs to ensure that the reset signal reaches all FPGAs in the system within one slow clock cycle. Due to the sufficiently long slow clock period, the design difficulty of the reset signal transmission network is extremely low.

[0056] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0057] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. An FPGA global reset synchronization circuit based on fast and slow clocks, characterized in that, The FPGA includes a clock signal channel and a reset signal channel. The clock signal channel includes a filter and a frequency multiplier. The filter filters the input first clock signal, and the frequency multiplier multiplies the frequency to generate a second clock signal whose frequency is an integer multiple of the first clock signal. The second clock signal is then output to provide a clock signal for the user logic in the FPGA chip. The reset signal channel includes a cross-clock domain transmission circuit. The input reset signal passes through this circuit and is output to provide a global reset signal for the user logic in the FPGA chip. The cross-clock domain transmission circuit includes four registers cascaded in sequence: a first register, a second register, a third register, and a fourth register. The first and second registers use the first clock signal, while the third and fourth registers use the second clock signal. The first register serves as the reset signal for the FPGA chip. A bit register is used to sample the reset signal from the reset signal transmission network at the rising edge of the first clock signal and transmit it to a second register; the second register is used to sample the reset signal transmitted by the first register at the rising edge of the first clock signal and transmit it to a third register, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the first register sample; the third register is used to sample the reset signal transmitted by the second register at the rising edge of the second clock signal and transmit it to a fourth register; the fourth register is used to sample the reset signal transmitted by the third register at the rising edge of the second clock signal and transmit it to the user logic as a global reset signal, so as to prevent the metastable signal from continuing to be transmitted and to enhance signal stability when metastability occurs in the third register sample; the rising edge of the second clock signal is delayed by a time Δt compared with the rising edge of the first clock signal, and the time Δt satisfies the following constraint: Δt ≥ t cqd + t setup Among them, t cqd t is the time difference in a cross-clock domain transmission circuit from the rising edge of the clock in the second register to the propagation of the reset signal to the input of the third register. setup This refers to the setup time of the third register in the cross-clock domain transmission circuit.

2. An FPGA chip, comprising an FPGA chip body with user logic, characterized in that, The FPGA chip body is provided with a first clock signal pin and a reset signal pin. The FPGA chip body is provided with the FPGA global reset synchronization circuit based on fast and slow clocks as described in claim 1. The first clock signal pin is connected to the input terminal of the clock signal channel, and the reset signal pin is connected to the input terminal of the reset signal channel.

3. A multi-FPGA chip verification and simulation system, characterized in that, include: The FPGA chip according to multiple claims 2, The reset control unit is used to generate the first clock signal and the reset signal. A synchronous clock transmission network is used to synchronously transmit the first clock signal to each FPGA chip. And a reset signal transmission network, used to transmit the reset signal to each FPGA chip in one cycle; The clock signal output terminal of the reset control unit is connected to the first clock signal pin of each FPGA chip through a synchronous clock transmission network, and the reset signal output terminal of the reset control unit is connected to the reset signal pin of each FPGA chip through a reset signal transmission network.

4. The multi-FPGA chip verification and simulation system according to claim 3, characterized in that, In the synchronous clock transmission network, the transmission cable lengths between the clock signal output terminal of the reset control unit and the first clock signal pins of each FPGA chip are the same or the deviation is within a set value.

5. The multi-FPGA chip verification and simulation system according to claim 4, characterized in that, In the reset signal transmission network, the transmission cable lengths between the reset signal output terminal of the reset control unit and the reset signal pins of each FPGA chip are the same or the deviation is within a set value.

6. An application method of the multi-FPGA chip verification simulation system as described in claim 5, characterized in that, include: S101 generates a first clock signal and a reset signal through the reset control unit; S102, the first clock signal is synchronously transmitted to each FPGA chip through the synchronous clock transmission network, and the reset signal is transmitted to each FPGA chip within one cycle through the reset signal transmission network. S103, in each FPGA chip, the input first clock signal is filtered by a filter and multiplied by a frequency multiplier through the clock signal channel to generate a second clock signal, and the second clock signal is output to provide a clock signal for the user logic in the FPGA chip; at the same time, the input reset signal is transmitted through the reset signal channel, including the cross-clock domain transmission circuit, and output to provide a global reset signal for the user logic in the FPGA chip, thereby realizing global reset synchronization of each FPGA chip.

7. The application method of the multi-FPGA chip verification simulation system according to claim 6, characterized in that, In step S101, when the first clock signal and the reset signal are generated by the reset control unit, it means that the reset signal is generated based on the rising edge of the first clock signal.

8. The application method of the multi-FPGA chip verification simulation system according to claim 7, characterized in that, In step S101, when the first clock signal and the reset signal are generated by the reset control unit, the period T of the generated first clock signal is... c The following constraints must be met: T c ≥ t cq + t rd + t setup – t cd + t skew In the above formula, t cq To reset the control unit, the time difference from the rising edge of the first clock signal to the output reset signal, t rd To reset the signal propagation delay of the signal transmission network, t setup t represents the setup time of the reset register in the FPGA chip. cd For the signal propagation delay of the synchronous clock transmission network, t skew The skew caused by transmitting clock signals to a synchronous clock transmission network.

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