A memory information processing method, device, apparatus and storage medium

Abstract

Embodiments of the present application disclose a memory information processing method. The method comprises: obtaining a memory exception address of a to-be-processed memory; analyzing the memory exception address based on attribute information of the memory exception address, and predicting a memory risk region on a memory page of the to-be-processed memory; wherein the memory risk region is a region where a memory error occurs on the memory page; determining a target memory page where the memory risk region is located from the memory page, and marking the target memory page. Embodiments of the present application also disclose a memory information processing device, equipment and storage medium.

Description

Technical Field

[0001] This application relates to memory processing technology in the field of computers, and more particularly to a memory information processing method, apparatus, device and storage medium. Background Technology

[0002] Currently, operating systems in electronic devices manage memory in units of memory pages. When the operating system detects an anomaly in the physical memory address within a memory page, it marks the memory page containing that address so that it will not be used again. However, this marking method can only isolate (mark) the memory page containing the currently abnormal physical memory address, resulting in low isolation effectiveness and reduced stability of the operating system. Summary of the Invention

[0003] To address the aforementioned technical problems, this application aims to provide a memory information processing method, apparatus, device, and storage medium that solves the problem of low isolation effectiveness, as it can only isolate the memory page containing the currently abnormal physical memory address.

[0004] A memory information processing method, the method comprising:

[0005] Obtain the memory exception address of the memory to be processed;

[0006] Based on the attribute information of the abnormal memory address, the abnormal memory address is analyzed to predict the memory risk area on the memory page of the memory to be processed; wherein, the memory risk area is the area on the memory page where a memory error occurs;

[0007] The target memory page containing the memory risk region is determined from the memory pages, and the target memory page is marked.

[0008] In the above scheme, obtaining the memory exception address of the memory to be processed includes:

[0009] Obtain historical running data of the memory to be processed; wherein, the historical running data represents the historical usage status information of the memory to be processed;

[0010] The historical running data is examined to determine the abnormal memory address.

[0011] In the above scheme, the step of analyzing the abnormal memory address based on its attribute information and predicting the memory risk region on the memory page of the memory to be processed includes:

[0012] Analyze the abnormal memory address to determine its type;

[0013] Analyze the abnormal memory addresses for each type to predict the memory risk areas.

[0014] In the above scheme, the analysis of each type of abnormal memory address and the prediction of the memory risk area includes:

[0015] For each type of abnormal memory address, statistical analysis is performed on the abnormal memory addresses to obtain the first distribution pattern among the abnormal memory addresses;

[0016] Based on the first distribution pattern, the abnormal memory addresses are analyzed to predict the memory risk areas.

[0017] In the above scheme, the step of analyzing the abnormal memory addresses and predicting the memory risk areas based on the first distribution pattern includes:

[0018] Based on the first distribution pattern, the abnormal memory addresses are statistically classified to determine the second distribution pattern among different types of abnormal memory addresses.

[0019] Based on the second distribution pattern, the target memory anomaly address in the memory page is predicted, and the memory risk area is determined based on the target memory anomaly address.

[0020] The method in the above scheme further includes:

[0021] Based on the mapping relationship between the abnormal memory address and the memory address on the memory page and the memory address on the memory module, the abnormal address on the memory module is determined;

[0022] Based on the abnormal address and memory structure, determine whether to generate an alarm message.

[0023] In the above scheme, determining whether to generate alarm information based on the abnormal address and memory structure includes:

[0024] Determine the character information of the abnormal address, and analyze the character information to determine the degree of abnormality of the abnormal address;

[0025] Determine the location of the exception address within the memory structure;

[0026] The degree of memory anomaly of the memory module is determined based on the degree of anomaly of the abnormal address and the location.

[0027] If the memory anomaly level exceeds the anomaly threshold, the alarm information is generated and output.

[0028] A memory information processing device, the device comprising:

[0029] The acquisition unit is used to acquire the memory exception address of the memory to be processed;

[0030] The prediction unit is used to analyze the abnormal memory address based on the attribute information of the abnormal memory address and predict the memory risk area on the memory page of the memory to be processed; wherein, the memory risk area is the area on the memory page where a memory error occurs;

[0031] The processing unit is configured to determine the target memory page containing the memory risk region from the memory pages, and mark the target memory page.

[0032] A memory information processing device, the device comprising: a processor, a memory, and a communication bus;

[0033] The communication bus is used to realize the communication connection between the processor and the memory;

[0034] The processor is used to execute a memory information processing program in the memory to perform the following steps:

[0035] Obtain the memory exception address of the memory to be processed;

[0036] Based on the attribute information of the abnormal memory address, the abnormal memory address is analyzed to predict the memory risk area on the memory page of the memory to be processed; wherein, the memory risk area is the area on the memory page where a memory error occurs;

[0037] The target memory page containing the memory risk region is determined from the memory pages, and the target memory page is marked.

[0038] A computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps of the memory information processing method described above.

[0039] The memory information processing method, apparatus, device, and storage medium provided in this application embodiment obtain the memory error address of the memory to be processed; based on the attribute information of the memory error address, analyze the memory error address to predict the memory risk area on the memory page of the memory to be processed; wherein, the memory risk area is the area on the memory page where a memory error occurs; determine the target memory page where the memory risk area is located from the memory page, and mark the target memory page; in this way, the memory error address of the memory to be processed can be analyzed to predict the memory risk area on the memory page corresponding to the memory to be processed, and the target memory page where the memory risk area is located can be marked so that the target memory page will not be used again in the future, thus avoiding a large number of memory errors on the memory page in advance, improving the isolation effect, and increasing the stability of the operating system of the electronic device. Attached Figure Description

[0040] Figure 1 A flowchart illustrating a memory information processing method provided in an embodiment of this application;

[0041] Figure 2 A flowchart illustrating a memory information processing method according to another embodiment of this application;

[0042] Figure 3 This application provides a schematic diagram of the structure of a memory reliability platform for a memory information processing method according to an embodiment of the present application.

[0043] Figure 4 This is a schematic diagram of the structure of a memory information processing device provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of the structure of a memory information processing device provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0046] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0047] This application provides a memory information processing method, which is applied to a memory information processing device, such as... Figure 1 As shown, the method includes the following steps:

[0048] Step 101: Obtain the memory exception address of the memory to be processed.

[0049] Among them, the memory to be processed can be the memory on the electronic device monitored by the memory information processing device; memory is used to temporarily store the computing data in the central processing unit (CPU). All programs in the electronic device run in memory. The normal operation of memory determines the overall speed of the electronic device and also affects the stability of the operating system on the electronic device. Therefore, monitoring the memory of the electronic device is particularly important.

[0050] In this embodiment of the application, obtaining the abnormal memory address may be achieved by the memory information processing device sending an acquisition instruction to the electronic device, so that the electronic device receives the acquisition instruction and sends it to the memory information processing device according to the acquisition instruction; or it may be achieved by the memory information processing device obtaining the memory operation data of the electronic device from the electronic device and determining the address after analyzing the memory operation data.

[0051] In one feasible implementation, the abnormal memory address can be an abnormal physical memory address on a memory page of an electronic device; specifically, the abnormal physical memory address refers to the physical memory address on the memory page where an error occurred.

[0052] It should be noted that the memory exception address can be a historical memory exception address of the memory to be processed; or it can be a memory exception address of the memory to be processed collected periodically.

[0053] Step 102: Based on the attribute information of the abnormal memory address, analyze the abnormal memory address and predict the memory risk area on the memory page of the memory to be processed.

[0054] The memory risk region is the area consisting of physical memory addresses on memory pages where errors occur; the memory risk region includes multiple target physical memory addresses that may cause errors.

[0055] In the embodiments of this application, the attribute information of the memory abnormal address refers to the information of the memory abnormal address itself; the attribute information of the memory abnormal address includes, but is not limited to, the size, length, type, character information, and byte information of the memory abnormal address.

[0056] In this embodiment of the application, the location of the abnormal memory address in the memory page can be analyzed based on the attribute information of the abnormal memory address, the distribution of the abnormal memory address can be determined, and the memory risk area can be predicted based on the distribution of the abnormal memory address.

[0057] In one feasible implementation, the memory error address is a set of multiple abnormal physical memory addresses on a memory page. The memory information processing device can analyze each pair of adjacent abnormal physical memory addresses based on the attribute information of the abnormal physical memory addresses to determine the distribution of abnormal physical memory addresses. Based on the distribution of abnormal physical memory addresses, the device can predict the region where the physical memory address that may be erroneous on the memory page is located and designate this region as the memory risk region.

[0058] It should be noted that in this embodiment, memory risk areas can be predicted by the abnormal memory addresses appearing on memory pages. Then, corresponding measures can be taken based on the predicted memory risk areas to prevent a large number of memory errors on memory pages from occurring in advance. This further avoids the operating system on electronic devices from crashing due to a large number of memory errors on memory pages, thus improving the stability of the operating system.

[0059] Step 103: Determine the target memory page containing the memory risk region from the memory pages, and mark the target memory page.

[0060] In this embodiment of the application, the target memory page containing the target physical memory address can be determined from multiple memory pages based on the target physical memory address in the memory risk region, and the target memory page can be marked so that the operating system of the electronic device does not use the marked target memory page, thereby improving the stability of the operating system of the electronic device.

[0061] The memory information processing method provided in this application embodiment obtains the memory error address of the memory to be processed; analyzes the memory error address based on the attribute information of the memory error address to predict the memory risk area on the memory page corresponding to the memory to be processed; wherein, the memory risk area is the area on the memory page where memory errors occur; determines the target memory page where the memory risk area is located from the memory pages, and marks the target memory page; in this way, the memory error address of the memory to be processed can be analyzed to predict the memory risk area on the memory page corresponding to the memory to be processed, and the target memory page where the memory risk area is located can be marked so that the target memory page will not be used again in the future, thus avoiding a large number of memory errors on the memory page in advance, improving the isolation effect, and increasing the stability of the operating system.

[0062] Based on the foregoing embodiments, this application provides a memory information processing method, such as... Figure 2 As shown, the method includes:

[0063] Step 201: The memory information processing device acquires the historical running data of the memory to be processed.

[0064] Among them, historical operation data represents the historical usage status information of the memory to be processed.

[0065] In this embodiment, the memory information processing device can send an acquisition instruction to the electronic device to obtain real-time running data of the memory. This allows the electronic device to send its own real-time running data of the memory to the memory information processing device according to the acquisition instruction, and store the real-time running data in a memory reliability database. This enables the memory information processing device to retrieve the historical running data of the memory to be processed from the memory reliability database. The memory information processing device can also send an acquisition instruction to the electronic device to obtain historical running data of the memory according to the historical running time of the memory. This allows the electronic device to send the historical running data corresponding to the historical running time of the memory to the memory determination device according to the acquisition instruction.

[0066] Step 202: The memory information processing device detects historical operating data and determines abnormal memory addresses.

[0067] In this embodiment, the memory information processing device can use Error Checking and Correction Code (ECC) technology to detect historical running data of the memory to be processed and determine abnormal memory addresses in the historical running data.

[0068] In one feasible implementation, such as Figure 3 As shown, the memory information processing method can be applied to a memory reliability analysis platform on a memory information processing device. The platform can store acquired historical runtime data in its own memory reliability database. Then, it can retrieve historical runtime data from the reliability database based on memory runtime, and analyze the historical runtime data using ECC technology or memory-related algorithms through a memory error analysis engine to determine abnormal memory addresses. This allows for the generation of memory analysis reports and memory error visualization analysis reports based on these abnormal addresses. The memory analysis report indicates whether abnormal memory addresses exist in the historical runtime data and the number of such addresses. The memory error visualization analysis report can include the type and distribution of abnormal memory addresses, as well as the identifier of the target memory page containing the memory risk area determined based on the distribution of abnormal memory addresses. The identifier of the target memory page can be its identity document (ID).

[0069] Step 203: The memory information processing device analyzes the abnormal memory address and determines the type of the abnormal memory address.

[0070] The types of abnormal memory addresses include at least correctable error types and uncorrectable error types; correctable errors can be represented by Corrected error, abbreviated as CE; uncorrectable errors can be represented by Uncorrected error, abbreviated as UE.

[0071] In this embodiment, the memory information processing device can analyze abnormal memory addresses, determine the degree of abnormality (i.e., error level) of each abnormal memory address, and determine the type of abnormal memory address based on the error level of each abnormal memory address. The error level of a correctable error is less than that of an uncorrectable error; the error level of each abnormal memory address can be determined based on the number of characters in each abnormal memory address.

[0072] In one feasible implementation, the character information of the physical memory address of each exception can be analyzed to determine the number of exception characters in the physical memory address of each exception. When the number of exception characters is greater than a preset number of exceptions, the type of the physical memory address of the exception can be determined as an uncorrectable error; when the number of exception characters is less than or equal to the preset number of exceptions, the type of the physical memory address of the exception can be determined as a correctable error.

[0073] Step 204: The memory information processing device analyzes the memory abnormal addresses of each type and predicts the memory risk areas.

[0074] In this embodiment of the application, the memory information processing device analyzes each type of memory abnormal address to determine the distribution pattern of each type of memory abnormal address in the memory page. Then, based on the distribution patterns of multiple types of memory abnormal addresses in the memory page, it analyzes the memory abnormal addresses to determine the distribution patterns of different types of memory abnormal addresses in the memory page. Based on the distribution patterns of different types of memory abnormal addresses in the memory page, it predicts the target memory abnormal address in the memory page that may be abnormal (error), and designates the area where the target memory abnormal address is located as the memory risk area.

[0075] Step 204 can be implemented by a1 and a2:

[0076] a1. The memory information processing device performs statistical analysis on each type of memory abnormal address to obtain the first distribution pattern among memory abnormal addresses.

[0077] In this embodiment of the application, a statistical algorithm can be used to perform statistical analysis on the byte information of each type of memory abnormal address, determine the row and column in the memory page where each type of memory abnormal address is located, and then determine the first distribution pattern corresponding to each type of memory abnormal address.

[0078] In one feasible implementation, a statistical algorithm can be used to determine the row and column of the memory page containing the memory exception address of type CE, based on byte alignment. Then, based on the row and column of the memory page containing the memory exception address of type CE, the first distribution pattern of the memory exception address of type CE within the memory page can be determined. Byte alignment includes kilobyte alignment and megabyte alignment.

[0079] It should be noted that different analysis algorithms or the same analysis algorithm can be used when analyzing different types of abnormal memory addresses.

[0080] In one feasible implementation, the memory analysis error engine stores the analysis algorithm corresponding to each type of memory exception address. Once the type of memory exception address is determined, the algorithm corresponding to that type can be used to analyze the memory exception address to improve the accuracy of the determined first distribution pattern.

[0081] a2. The memory information processing device analyzes abnormal memory addresses based on the first distribution law and predicts memory risk areas.

[0082] In this embodiment of the application, the distribution of different types of abnormal memory addresses in memory pages can be determined based on the first distribution pattern of each type of abnormal memory address in memory pages, and a prediction algorithm can be used to predict memory risk areas based on the distribution of different types of abnormal memory addresses in memory pages.

[0083] Step a2 can be achieved by steps b1 and b2:

[0084] b1. The memory information processing device statistically classifies abnormal memory addresses based on the first distribution law and determines the second distribution law between different types of abnormal memory addresses.

[0085] In the embodiments of this application, a classification and statistical algorithm can be used to analyze the distribution of memory exception addresses of each type in memory pages among multiple types, and to determine the second distribution pattern between different types of memory exception addresses.

[0086] In one feasible implementation, the memory error addresses in memory pages can be analyzed according to the first distribution law to determine the common characteristics of the locations of different types of memory error addresses, and the second distribution law can be determined based on these common characteristics.

[0087] b2. The memory information processing device predicts the target memory abnormal address in the memory page based on the second distribution law, and determines the memory risk area based on the target memory abnormal address.

[0088] In this embodiment of the application, the memory information processing device can use a prediction algorithm to predict the target memory error address in the memory page based on the distribution of different types of memory error addresses, and regard the area where the target memory error address is located as the memory risk area.

[0089] In one feasible implementation, if the memory abnormal addresses of type CE and UE are distributed within a specific megabyte, column, and row, the target memory abnormal address can be determined based on the memory address of that megabyte, column, and row, and the region where the target memory abnormal address is located can be designated as the memory risk region.

[0090] Step 205: The memory information processing device determines the target memory page where the memory risk area is located from the memory pages and marks the target memory page.

[0091] Compared to the method of isolating only the memory page where the memory error address is located, the memory information processing method provided in this application can predict memory risk areas and isolate the memory pages where the memory risk areas are located, thereby reducing the frequency of memory errors on memory pages and making the operating system more stable.

[0092] Based on the foregoing embodiments, in other embodiments of this application, the memory information processing method may further include the following steps:

[0093] Step 206: The memory information processing device determines the abnormal address on the memory module based on the mapping relationship between the abnormal memory address and the memory address on the memory page and the memory address on the memory module.

[0094] Here, "abnormal address on memory module" refers to the address on the memory module where a memory error has occurred.

[0095] In one feasible implementation, the mapping relationship between memory addresses on memory pages and memory addresses on memory modules can refer to the mapping relationship between the location of memory addresses on memory pages and the location of memory addresses on memory modules.

[0096] In this embodiment of the application, the abnormal address on the memory module corresponding to the abnormal address on the memory page can be determined according to the mapping relationship between the memory address of the memory page and the memory address of the memory module; wherein, the abnormal address on the memory module refers to the physical memory address on the memory module.

[0097] Step 207: The memory information processing device determines whether to generate alarm information based on the abnormal data and memory structure.

[0098] Among them, memory structure refers to the structure of memory modules.

[0099] In this embodiment of the application, the degree of damage to the memory module can be determined based on the abnormal address and the structure of the memory module, and whether to generate alarm information can be determined based on the degree of damage to the memory module.

[0100] Step 207 can be implemented using c1-c4:

[0101] c1. The memory information processing device determines the character information of the abnormal address and analyzes the character information to determine the degree of abnormality of the abnormal address.

[0102] In this embodiment of the application, the memory information processing device can analyze the character information of the abnormal address, determine the number of abnormal characters in each abnormal address, compare the number of abnormal characters with a preset number of characters, and determine the degree of abnormality of the abnormal address based on the comparison result; if the number of abnormal characters is greater than the preset number of characters, it indicates that the degree of abnormality of the abnormal address is high, and if the number of abnormal characters is less than or equal to the preset number of characters, it indicates that the degree of abnormality of the abnormal address is low.

[0103] c2. The memory information processing device determines the location of the abnormal address in the memory structure.

[0104] In this embodiment, the memory information processing device can determine the location of the abnormal address in each level of the memory structure based on the abnormal address and the memory structure. The memory structure levels include at least rank and bank, where bank is the smallest memory unit in the memory module, and rank is the memory unit at the next higher level than bank.

[0105] It should be noted that by determining the location of the abnormal address in the memory structure, we can determine the distribution of the abnormal address in each level of the memory structure. This distribution can then be used as a basis for determining the degree of memory abnormality of the memory module.

[0106] c3. The memory information processing device can determine the degree of memory abnormality of the memory module based on the degree and location of the abnormal address.

[0107] In this embodiment of the application, the degree of abnormality of each level of the memory module can be determined based on the distribution of abnormal addresses in each level of the memory structure and the degree of abnormality of the abnormal addresses, and the degree of memory abnormality of the memory module can be determined based on the degree of abnormality of each level of the memory module.

[0108] In one feasible implementation, the memory information processing device can assign a certain score to the degree of abnormality of each level of the memory module, and then calculate the average of the scores corresponding to each level to obtain the target score, whereby the target score represents the degree of memory abnormality of the memory module.

[0109] c4. When the memory anomaly level exceeds the anomaly threshold, the memory information processing device generates and outputs alarm information.

[0110] The degree of memory anomaly can be represented by a target score.

[0111] In this embodiment, the target score of the memory module can be compared with an abnormal threshold. When the target score of the memory module is greater than the abnormal threshold, it indicates a serious memory module failure that requires replacement. An alarm message is generated and output to prompt the user to replace the memory module in a timely manner, preventing the electronic device from malfunctioning and affecting the user's work. The alarm message includes the degree of the memory module failure and the location of the failure.

[0112] It should be noted that alarm information output methods include at least audible alarms and / or visual alarms.

[0113] The memory information processing method provided in this application can analyze the abnormal memory addresses of the memory to be processed, predict the memory risk areas on the memory pages of the memory to be processed, and mark the target memory pages where the memory risk areas are located so that the target memory pages will not be used in the future. This avoids a large number of memory errors on memory pages in advance, improves the isolation effect, and increases the stability of the operating system of electronic devices.

[0114] Based on the foregoing embodiments, this application also provides a memory information processing device, which can be applied to... Figure 1-2 In the memory information processing method provided in the corresponding embodiment, refer to Figure 4 The memory information processing device 3 includes:

[0115] Acquisition unit 31 is used to acquire the memory exception address of the memory to be processed;

[0116] The prediction unit 32 is used to analyze the abnormal memory address based on the attribute information of the abnormal memory address and predict the memory risk area on the memory page of the memory to be processed; wherein, the memory risk area is the area on the memory page where the memory error occurs;

[0117] The processing unit 33 is used to determine the target memory page where the memory risk region is located from the memory pages, and to mark the target memory page.

[0118] In this embodiment of the application, the acquisition unit 31 is further configured to perform the following steps:

[0119] Obtain historical runtime data of the memory to be processed; whereby historical runtime data represents the historical usage status information of the memory to be processed;

[0120] Historical operational data is examined to identify abnormal memory addresses.

[0121] In this embodiment of the application, the prediction unit 32 is further configured to perform the following steps:

[0122] Analyze the abnormal memory addresses to determine their type;

[0123] Analyze the memory addresses for each type of abnormal memory and predict the memory risk areas.

[0124] In this embodiment of the application, the prediction unit 32 is further configured to perform the following steps:

[0125] For each type of memory error address, statistical analysis is performed on the memory error addresses to obtain the first distribution pattern among the memory error addresses;

[0126] Based on the first distribution law, abnormal memory addresses are analyzed to predict memory risk areas.

[0127] In this embodiment of the application, the prediction unit 32 is further configured to perform the following steps:

[0128] Based on the first distribution law, abnormal memory addresses are statistically classified to determine the second distribution law between different types of abnormal memory addresses;

[0129] The target memory anomaly address in the memory page is predicted based on the second distribution law, and the memory risk area is determined based on the target memory anomaly address.

[0130] In this embodiment of the application, the processing unit 33 is further configured to perform the following steps:

[0131] The abnormal address on the memory module is determined based on the mapping relationship between the abnormal memory address and the memory address on the memory page and the memory address on the memory module;

[0132] Based on the abnormal address and memory structure, determine whether to generate an alarm message.

[0133] In this embodiment of the application, the processing unit 33 is further configured to perform the following steps:

[0134] Determine the character information of the abnormal address and analyze the character information to determine the degree of abnormality of the abnormal address;

[0135] Determine the location of the exception address within the memory structure;

[0136] The degree of memory anomaly of the memory module is determined based on the degree and location of the anomaly at the abnormal address;

[0137] If the memory anomaly level exceeds the anomaly threshold, generate and output an alarm message.

[0138] It should be noted that the interaction process between the units in the embodiments of this application can be referred to Figure 1-2 The implementation process of the memory information processing method provided in the corresponding embodiment will not be described in detail here.

[0139] The memory information processing device provided in this application embodiment can analyze the abnormal memory addresses of the memory to be processed, predict the memory risk area on the memory page corresponding to the memory to be processed, and mark the target memory page where the memory risk area is located so that the target memory page will not be used again in the future. This avoids a large number of memory errors on the memory page in advance, improves the isolation effect, and increases the stability of the operating system of the electronic device.

[0140] Based on the foregoing embodiments, embodiments of this application provide a memory information processing device, which can be applied to... Figure 1-2 In the memory information processing method provided in the corresponding embodiment, refer to Figure 5 As shown, the memory information processing device 4 may include: a processor 41, a memory 42, and a communication bus 43, wherein:

[0141] Communication bus 43 is used to realize the communication connection between processor 41 and memory 42;

[0142] The processor 41 is used to execute the memory information processing program in the memory 42 to perform the following steps:

[0143] Obtain the memory exception address of the memory to be processed;

[0144] Based on the attribute information of abnormal memory addresses, the abnormal memory addresses are analyzed to predict the memory risk areas on the memory pages to be processed; where the memory risk areas are the areas on the memory pages where memory errors occur.

[0145] Identify the target memory page containing the memory risk region from the memory pages, and mark the target memory page.

[0146] In other embodiments of this application, the processor 41 is used to execute a memory information processing program in the memory 42 to obtain the memory exception address of the memory to be processed, in order to implement the following steps:

[0147] Obtain historical runtime data of the memory to be processed; whereby historical runtime data represents the historical usage status information of the memory to be processed;

[0148] Historical operational data is examined to identify abnormal memory addresses.

[0149] In other embodiments of this application, the processor 41 is used to execute the memory information processing program in the memory 42 based on the attribute information of the abnormal memory address, analyze the abnormal memory address, and predict the memory risk area on the memory page of the memory to be processed, so as to achieve the following steps:

[0150] Analyze the abnormal memory addresses to determine their type;

[0151] Analyze the memory addresses for each type of abnormal memory and predict the memory risk areas.

[0152] In other embodiments of this application, the processor 41 is used to execute a memory information processing program in the memory 42 to analyze memory exception addresses of each type and predict memory risk areas in order to achieve the following steps:

[0153] For each type of memory error address, statistical analysis is performed on the memory error addresses to obtain the first distribution pattern among the memory error addresses;

[0154] Based on the first distribution law, abnormal memory addresses are analyzed to predict memory risk areas.

[0155] In other embodiments of this application, the processor 41 is used to execute a memory information processing program in the memory 42 to analyze abnormal memory addresses based on a first distribution law and predict memory risk areas, in order to achieve the following steps:

[0156] Based on the first distribution law, abnormal memory addresses are statistically classified to determine the second distribution law between different types of abnormal memory addresses;

[0157] The target memory anomaly address in the memory page is predicted based on the second distribution law, and the memory risk area is determined based on the target memory anomaly address.

[0158] In other embodiments of this application, the processor 41 is used to execute a memory information processing program in the memory 42 to perform the following steps:

[0159] The abnormal address on the memory module is determined based on the mapping relationship between the abnormal memory address and the memory address on the memory page and the memory address on the memory module;

[0160] Based on the abnormal address and memory structure, determine whether to generate an alarm message.

[0161] In other embodiments of this application, the processor 41 is used to execute a memory information processing program in the memory 42 to determine whether to generate alarm information based on the exception address and memory structure, in order to implement the following steps:

[0162] Determine the character information of the abnormal address and analyze the character information to determine the degree of abnormality of the abnormal address;

[0163] Determine the location of the exception address within the memory structure;

[0164] The degree of memory anomaly of the memory module is determined based on the degree and location of the anomaly at the abnormal address;

[0165] If the memory anomaly level exceeds the anomaly threshold, generate and output an alarm message.

[0166] It should be noted that the specific implementation process of the steps executed by the processor in this embodiment can be referred to Figure 1-2 The implementation process of the memory information processing method provided in the corresponding embodiment will not be described in detail here.

[0167] The memory information processing device provided in the embodiments of this application can analyze the abnormal memory addresses of the memory to be processed, predict the memory risk areas on the memory pages of the memory to be processed, and mark the target memory pages where the memory risk areas are located so that the target memory pages will not be used in the future. This avoids a large number of memory errors on memory pages in advance, improves the isolation effect, and increases the stability of the operating system of electronic devices.

[0168] Based on the foregoing embodiments, embodiments of this application provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement... Figure 1-2 The steps in the memory information processing method provided in the corresponding embodiment.

[0169] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0170] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0171] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0172] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0173] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0174] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0175] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory information processing method characterized by comprising: The method comprises: acquiring a memory exception address of a to-be-processed memory; based on attribute information of the memory exception address, analyzing the memory exception address, and predicting a memory risk region on a memory page of the to-be-processed memory; wherein the memory risk region is a region on the memory page where a memory error occurs; determining a target memory page where the memory risk region is located from the memory page, and marking the target memory page; wherein, based on the attribute information of the memory exception address, analyzing the memory exception address, and predicting the memory risk region on the memory page of the to-be-processed memory, comprises: based on the type of the memory exception address, statistically analyzing the memory exception address of each type to obtain a first distribution rule between the memory exception addresses; based on the first distribution rule, statistically classifying the memory exception addresses to determine a second distribution rule between memory exception addresses of different types; based on the second distribution rule, predicting a target memory exception address in the memory page, and determining the memory risk region based on the target memory exception address.

2. The method of claim 1, wherein, The acquisition of the memory exception address of the to-be-processed memory comprises: acquiring historical running data of the to-be-processed memory; wherein the historical running data represents historical usage state information of the to-be-processed memory; detecting the historical running data to determine the memory exception address.

3. The method of claim 1, wherein, The analysis of the memory exception address based on the attribute information of the memory exception address, and the prediction of the memory risk region on the memory page of the to-be-processed memory, comprises: analyzing the memory exception address to determine the type of the memory exception address; analyzing each type of memory exception address to predict the memory risk region.

4. The method of claim 1, wherein, The method further comprises: based on the mapping relationship between the memory exception address and the memory address on the memory page and the memory address on the memory bank, determining an exception address on the memory bank; based on the exception address and the memory structure, determining whether to generate an alarm information.

5. The method of claim 4, wherein, The determination of whether to generate an alarm information based on the exception address and the memory structure comprises: determining character information of the exception address, and analyzing the character information to determine the abnormality degree of the exception address; determining the position of the exception address in the memory structure; based on the abnormality degree of the exception address and the position, determining the memory exception degree of the memory bank; in the case where the memory exception degree is greater than an exception threshold, generating the alarm information and outputting.

6. A memory information processing apparatus characterized by comprising: The device comprises: an acquisition unit configured to acquire a memory exception address of a to-be-processed memory; a prediction unit configured to analyze the memory exception address based on attribute information of the memory exception address, and predict a memory risk region on a memory page of the to-be-processed memory; wherein the memory risk region is a region on the memory page where a memory error occurs; a processing unit configured to determine a target memory page where the memory risk region is located from the memory page, and mark the target memory page. The prediction unit is further configured to: based on the type of the memory exception address, obtain a first distribution rule between memory exception addresses by statistical analysis of each type of memory exception address; based on the first distribution rule, statistically classify the memory exception addresses to determine a second distribution rule between memory exception addresses of different types; based on the second distribution rule, predict a target memory exception address in the memory page, and determine the memory risk region based on the target memory exception address.

7. A memory information processing apparatus, characterized by comprising: The device comprises a processor, a memory and a communication bus; The communication bus is configured to realize communication connection between the processor and the memory; The processor is configured to execute a memory page determination program in the memory to realize the following steps: obtain a memory exception address of a to-be-processed memory; based on attribute information of the memory exception address, analyze the memory exception address, and predict a memory risk region on a memory page of the to-be-processed memory; wherein the memory risk region is a region where memory errors occur on the memory page; determine a target memory page where the memory risk region is located from the memory page, and mark the target memory page; wherein the step of analyzing the memory exception address based on the attribute information of the memory exception address and predicting the memory risk region on the memory page of the to-be-processed memory comprises: based on the type of the memory exception address, obtain a first distribution rule between memory exception addresses by statistical analysis of each type of memory exception address; based on the first distribution rule, statistically classify the memory exception addresses to determine a second distribution rule between memory exception addresses of different types; based on the second distribution rule, predict a target memory exception address in the memory page, and determine the memory risk region based on the target memory exception address.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, which can be executed by one or more processors to realize the steps of the memory information processing method according to any one of claims 1 to 5.

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