Manufacturing method of gallium nitride power device, device and integrated circuit

Abstract

The present invention provides a method for manufacturing a gallium nitride integrated circuit, the method comprising: providing a substrate; sequentially forming a channel layer and a barrier layer on the substrate in a direction away from the substrate; depositing a hard mask on the surface of the barrier layer; etching the hard mask to form an opening in the hard mask; epitaxially forming a p-GaN layer in the opening; depositing metal materials on the surface of the barrier layer and annealing to form a source electrode and a drain electrode; forming a p-GaN gate; depositing a passivation layer on top of the p-GaN gate; forming a source metal interconnect layer and a metal field plate; the source metal interconnect layer is formed on the top of the source electrode, and the metal field plate is formed on the surface of the passivation layer on the top of the p-GaN gate; connecting the metal field plate to the source metal interconnect layer; and forming a drain metal interconnect layer and a gate metal interconnect layer. The technical solution provided by the present invention, by selecting a method for epitaxially growing p-GaN, effectively avoids the problem of device damage caused by the etching process of the p-GaN layer, thereby achieving the effects of increasing device output current, reducing dynamic on-resistance, and improving the reliability of power tubes and gate drive units.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for manufacturing a gallium nitride power device, the device, and an integrated circuit. Background Art

[0002] As a third-generation semiconductor material, gallium nitride (GaN) holds great promise for commercial applications in high-frequency power amplifiers and power switching devices due to its wide bandgap, high electron mobility, and high breakdown field. However, during the fabrication of GaN HEMTs, the etching of the p-GaN layer can damage the lateral heterojunction surface and the conductive channel, leading to surface state degradation and low electron mobility. This, in turn, affects the device's static and dynamic performance, severely impacting the reliability of the power transistor. Therefore, process improvements are needed to mitigate the reliability issues caused by etching damage. Furthermore, in practical circuit applications, high-frequency switching of GaN power devices can cause a series of reliability issues due to voltage spikes and oscillations introduced by parasitic inductance introduced by the interconnects between the gate drive circuit and the power switch, as well as by printed circuit board (PCB) wiring.

[0003] Therefore, developing a new p-GaN enhancement mode device preparation process and researching a technical solution to reduce the parasitic inductance between the gate drive and the power device have become technical priorities that need to be urgently addressed by those skilled in the art. Summary of the Invention

[0004] The present invention provides a method for manufacturing a gallium nitride power device, a device, and an integrated circuit to solve the problem that the etching process of the p-GaN layer may cause device damage, and the problem that parasitic inductance is generated by the interconnection line between the gate driver and the gallium nitride power device.

[0005] According to a first aspect of the present invention, a method for manufacturing a gallium nitride power device is provided, the method comprising:

[0006] Providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence in a direction away from the substrate;

[0007] depositing a hard mask on the surface of the barrier layer;

[0008] etching the hard mask to form an opening in the hard mask;

[0009] forming a p-GaN layer in the opening;

[0010] Depositing metal materials on surfaces of the barrier layer at both sides of the p-GaN layer along the first direction and annealing the materials to form a source electrode and a drain electrode;

[0011] forming a p-GaN gate, wherein the p-GaN gate comprises the p-GaN layer and a gate metal layer formed on top of the p-GaN layer;

[0012] depositing a passivation layer on top of the p-GaN gate;

[0013] forming a source metal interconnect layer and a metal field plate; the source metal interconnect layer is formed on the top of the source electrode, and the metal field plate is formed on the surface of the passivation layer on the top of the p-GaN gate; the metal field plate is connected to the source metal interconnect layer;

[0014] A drain metal interconnection layer and a gate metal interconnection layer are formed.

[0015] Optionally, the specific step of etching the hard mask to form an opening on the hard mask includes:

[0016] coating a photoresist on the surface of the hard mask;

[0017] After the photoresist is exposed and developed, the hard mask is etched using the developed photoresist as a mask to form an opening on the hard mask.

[0018] Optionally, forming a p-GaN layer in the opening specifically includes:

[0019] Epitaxially growing a p-GaN layer in the opening and on the surface of the remaining hard mask;

[0020] The remaining hard mask and the p-GaN layer on the surface thereof are removed.

[0021] Optionally, after removing the remaining hard mask and the p-GaN layer on the surface thereof, the method further includes:

[0022] The p-GaN layer is activated with Mg+.

[0023] Optionally, before depositing a hard mask on the surface of the barrier layer, the method further includes:

[0024] Performing mesa isolation; forming an isolation layer in the barrier layer and the channel layer, wherein the isolation layer penetrates the barrier layer and does not contact the substrate.

[0025] Optionally, the specific steps for forming a p-GaN gate are:

[0026] Depositing a passivation layer on the surface of the barrier layer; the passivation layer covers the source electrode, the drain electrode, and the p-GaN layer, and fills the gap between the source electrode, the p-GaN layer, and the drain electrode;

[0027] Etching the passivation layer on top of the p-GaN layer to form a gate hole;

[0028] A gate metal layer is deposited and filled in the gate hole to form the p-GaN gate.

[0029] Optionally, the specific steps of forming the source metal interconnect layer and the metal field plate are:

[0030] Etching the passivation layer at the top of the source electrode to form a source opening;

[0031] A metal material is deposited in the source opening to form a source metal interconnection layer, and a metal material is deposited on the surface of the passivation layer at the top of the p-GaN gate to form a metal field plate.

[0032] Optionally, the specific steps of forming the drain metal interconnection layer and the gate metal interconnection layer are:

[0033] Depositing the passivation layer on the surface of the metal field plate;

[0034] Etching the passivation layer at the top of the drain and the top of the p-GaN gate to form a drain opening and a gate opening;

[0035] Metal materials are deposited in the gate opening and the drain opening respectively to form the drain metal interconnection layer and the gate metal interconnection layer.

[0036] According to a second aspect of the present invention, there is provided a gallium nitride power device, comprising: a gallium nitride power device manufactured using the method for manufacturing a gallium nitride power device according to any one of the first aspects of the present invention.

[0037] According to a third aspect of the present invention, a gallium nitride power device monolithic integrated circuit with a gate driver is provided, comprising: the gallium nitride power device according to the second aspect of the present invention, wherein the gallium nitride power device monolithic integrated circuit with a gate driver further comprises a gate driver; and the gate driver and the gallium nitride power device share a same substrate to form the gallium nitride power device monolithic integrated circuit with a gate driver.

[0038] According to a fourth aspect of the present invention, a method for manufacturing a monolithic integrated circuit of a gallium nitride power device with a gate driver is provided, comprising:

[0039] Providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence in a direction away from the substrate;

[0040] Performing mesa isolation; forming an isolation layer in the barrier layer and the channel layer, wherein the isolation layer penetrates the barrier layer and does not contact the substrate;

[0041] depositing a hard mask on the surface of the barrier layer;

[0042] Etching the hard mask in the first region and the second region to form an opening in the hard mask; forming a p-GaN layer in the opening;

[0043] Depositing a metal material on the surface of the barrier layer and annealing the metal material to form a source electrode and a drain electrode in the first region, the second region, and the third region;

[0044] forming a gate and a p-GaN gate; the p-GaN gate is formed in the first region and the second region; the gate is formed in the third region; wherein the p-GaN gate includes the p-GaN layer and a gate metal layer on top of the p-GaN layer;

[0045] Depositing a passivation layer on top of the gate and the p-GaN gate;

[0046] forming a source metal interconnect layer and a metal field plate in the second region; the source metal interconnect layer is formed at the top of the source electrode, and the metal field plate is formed on the surface of the passivation layer at the top of the p-GaN gate; and the metal field plate and the source metal interconnect layer are electrically connected;

[0047] forming a drain metal interconnection layer, a gate metal interconnection layer, and the source metal interconnection layer in the first region and the third region; the drain metal interconnection layer is formed on top of the drain; the gate metal interconnection layer is formed on top of the p-GaN gate and the gate; thereby forming a gate driver in the third region and the first region, and forming a gallium nitride power device in the second region;

[0048] The third region, the first region and the second region are arranged in sequence along a first direction.

[0049] The present invention provides a method for manufacturing a gallium nitride power device. The method adopts a selective epitaxial growth method to form an opening in a hard mask to form a p-GaN layer in the opening. This solves the problem that the etching process of the p-GaN layer may cause device damage. While achieving the effect of increasing the device output current and reducing the dynamic on-resistance, it also improves the reliability of the power tube and the gate drive unit.

[0050] Furthermore, the present invention provides a gallium nitride power device monolithic integrated circuit with a gate driver. By fabricating the gallium nitride power device and the gate driver on the same substrate to form a gallium nitride power device monolithic integrated circuit with a gate driver, the problem of parasitic inductance generated by the interconnection line between the gate driver and the gallium nitride power device is solved, thereby obtaining a purer gate drive signal and more stable switching characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 This is a schematic flow chart of a method for manufacturing a gallium nitride power device provided by a specific embodiment of the present invention;

[0053] Figure 2 This is a flow chart of a method for manufacturing a gallium nitride power device monolithic integrated circuit with a gate driver provided by a specific embodiment of the present invention;

[0054] Figure 3-9 1 is a schematic diagram of a device structure at different process stages according to a method for manufacturing a gallium nitride power device provided by an embodiment of the present invention;

[0055] Figure 10-14 Schematic diagram of a device structure at different process stages manufactured according to a method for manufacturing a gallium nitride power device monolithic integrated circuit with a gate driver provided by one embodiment of the present invention;

[0056] Description of reference numerals:

[0057] 101-substrate;

[0058] 102-channel layer;

[0059] 103-barrier layer;

[0060] 104-p-GaN layer;

[0061] 105-gate metal layer;

[0062] 106- isolation layer;

[0063] 107-passivation layer;

[0064] 108- source;

[0065] 109-drain;

[0066] 110-source metal interconnection layer;

[0067] 111-drain metal interconnection layer;

[0068] 112-Metal field plate;

[0069] 113-Hard mask. DETAILED DESCRIPTION

[0070] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0071] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatus.

[0072] The third-generation semiconductor material gallium nitride has extremely broad application prospects in commercial applications such as high-frequency power amplifiers and power switching devices due to its advantages such as wide band gap, high electron mobility and large electrical breakdown field.

[0073] For pGaN gate enhancement mode power transistors, the pGaN etching process can cause a certain degree of damage to the heterojunction surface and conductive channel, leading to surface state degradation and reduced electron mobility, which in turn affects the static and dynamic performance of the device and seriously affects the reliability of the power transistor. Therefore, process improvements are needed to avoid reliability issues caused by etching damage.

[0074] In addition, the planar structure of GaN HEMT (high electron mobility transistor) has the inherent advantage of high-density integration, which can be used to expand functions, optimize device performance and improve circuit reliability. However, because the gate drive voltage window of commercial p-GaN gate power HEMT is much narrower than that of Si / SiC (silicon carbide)-based MOSFET (metal oxide semiconductor field effect transistor), large gate voltage spikes may cause gate junction degradation. At the same time, the threshold voltage Vth of gallium nitride power transistors is also relatively low, and misleading turn-on is likely to occur. Moreover, in actual circuit applications, the high-frequency switching of GaN power devices will cause voltage spikes / oscillations caused by parasitic inductance introduced by the interconnection lines between the gate drive circuit and the power switch and the pCB (printed circuit board) wires, which will cause a series of reliability issues.

[0075] In view of this, the inventors discovered through repeated experiments that the use of an epitaxial pGaN process to prepare an enhanced power transistor and a drive logic unit with an enhanced HEMT can avoid damage from the pGaN etching process. While increasing the device output current and reducing the dynamic on-resistance, it can also improve the reliability of the power transistor and gate drive unit.

[0076] Furthermore, the inventors have discovered that by monolithically integrating the gate drive circuit with the power switch, the parasitic inductance between the gate drive and the power device can be greatly reduced, thereby obtaining a purer gate drive signal and more stable switching characteristics.

[0077] Therefore, the present application provides a gallium nitride power device monolithic integrated circuit with a gate driver, which adopts the selected epitaxial pGaN process to prepare the enhanced power tube and enhanced logic unit, avoiding damage from the pGaN etching process. While increasing the device output current and reducing the dynamic on-resistance, it also improves the reliability of the power tube and the gate driver unit. At the same time, by monolithically integrating the gate drive circuit with the power switch, the parasitic inductance generated by the interconnection line between the gate drive and the power device is greatly reduced, thereby obtaining a purer gate drive signal and more stable switching characteristics.

[0078] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0079] Please refer to Figure 1 , Figure 3-Figure 9 According to an embodiment of the present invention, a method for manufacturing a gallium nitride power device is provided, the method comprising:

[0080] S11: providing a substrate 101; forming a channel layer 102 and a barrier layer 103 on the substrate 101 in sequence in a direction away from the substrate 101, such as Figure 3 As shown;

[0081] S12: depositing a hard mask 113 on the surface of the barrier layer 103;

[0082] S13: Etching the hard mask 113 to form an opening on the hard mask 113. After the opening is formed, the device is as follows: Figure 5 As shown;

[0083] S14: forming a p-GaN layer 104 in the opening, and forming the device after the p-GaN layer 104 is as follows Figure 6 As shown;

[0084] S15: Depositing metal materials on the surface of the barrier layer 103 on both sides of the p-GaN layer 104 along the first direction and annealing to form a source 108 and a drain 109. After the source 108 and the drain 109 are formed, the device is as follows: Figure 7 As shown;

[0085] S16: forming a p-GaN gate; the p-GaN gate includes the p-GaN layer 104 and a gate metal layer 105 formed on top of the p-GaN layer 104;

[0086] S17: depositing a passivation layer 107 on top of the p-GaN gate;

[0087] S18: forming a source metal interconnect layer 110 and a metal field plate 112; the source metal interconnect layer is formed on the top of the source electrode 108, and the metal field plate 112 is formed on the surface of the passivation layer 107 on the top of the p-GaN gate; the metal field plate 112 is electrically connected to the source metal interconnect layer;

[0088] S19: forming a drain metal interconnection layer 111 and a gate metal interconnection layer. After forming the drain metal interconnection layer 111 and the gate metal interconnection layer, the device is as follows: Figure 9 shown.

[0089] The technical solution provided by the present invention avoids damage to the p-GaN layer 104 during the etching process by depositing a hard mask 113 on the surface of the barrier layer 103 and forming an opening in the hard mask 113 to form the p-GaN layer 104 in the opening. This improves the reliability of the power tube and the gate driver unit while increasing the output current of the device and reducing the dynamic on-resistance.

[0090] In one embodiment, when a gallium nitride power device is to be manufactured, step S12: before depositing a hard mask 113 on the surface of the barrier layer 103, further comprising: performing mesa isolation to isolate the gallium nitride power device; forming an isolation layer 106 in the barrier layer 103 and the channel layer 102, the isolation layer 106 penetrating the barrier layer 103 and not contacting the substrate 101, and the device after forming the isolation layer 106 is as follows Figure 4 shown.

[0091] In one embodiment, the specific steps of step S13: etching the hard mask 113 to form an opening on the hard mask 113 include:

[0092] S131, coating a photoresist on the surface of the hard mask 113;

[0093] S132 , exposing and developing the photoresist, and etching the hard mask 113 using the developed photoresist as a mask to form openings on the hard mask 113 .

[0094] In one embodiment, step S14: forming the p-GaN layer 104 in the opening specifically includes:

[0095] S141: epitaxially growing a p-GaN layer 104 in the opening and on the surface of the remaining hard mask 113;

[0096] S142 : removing the remaining hard mask 113 and the p-GaN layer 104 on the surface thereof.

[0097] In one embodiment, after removing the remaining hard mask 113 and the p-GaN layer 104 on the surface thereof in step S142, the following steps are further included:

[0098] Mg+ activation is performed in the p-GaN layer 104 .

[0099] In one embodiment, step S16: forming the p-GaN gate comprises the following steps:

[0100] S161: Depositing a passivation layer 107 on the surface of the barrier layer 103; the passivation layer 107 covers the source 108, the drain 109 and the p-GaN layer 104, and fills the gaps between the source 108, the p-GaN layer 104 and the drain 109. After the barrier layer 103 is deposited, the device is as follows: Figure 8 As shown;

[0101] S162: Etching the passivation layer 107 on the top of the p-GaN layer 104 to form a gate hole;

[0102] S163: depositing and filling a gate metal layer 105 in the gate hole to form the p-GaN gate.

[0103] In one embodiment, the specific steps of step S18: forming the source metal interconnect layer 110 and the metal field plate 112 are as follows:

[0104] S181: etching the passivation layer 107 on the top of the source electrode 108 to form a source opening;

[0105] S182 : depositing a metal material in the source opening to form a source metal interconnection layer, and depositing a metal material on the surface of the passivation layer 107 at the top of the p-GaN gate to form a metal field plate 112 .

[0106] In one embodiment, the specific steps of step S19: forming the drain metal interconnection layer 111 and the gate metal interconnection layer are:

[0107] S191: Depositing the passivation layer 107 on the surface of the metal field plate 112;

[0108] S192: etching the passivation layer 107 at the top of the drain electrode 109 and the top of the p-GaN gate to form a drain opening and a gate opening;

[0109] S193: depositing metal materials in the gate opening and the drain opening respectively to form the drain metal interconnection layer 111 and the gate metal interconnection layer.

[0110] According to an embodiment of the present invention, there is further provided a gallium nitride power device, comprising: a gallium nitride power device manufactured using the method for manufacturing a gallium nitride power device according to any one of the aforementioned embodiments of the present invention.

[0111] Secondly, please refer to Figure 14 According to other embodiments of the present invention, a gallium nitride power device monolithic integrated circuit with a gate driver is provided, comprising: the gallium nitride power device according to the aforementioned embodiment of the present invention, wherein the gallium nitride power device monolithic integrated circuit with a gate driver further comprises a gate driver; and the gate driver and the gallium nitride power device share the same substrate 101 to form the gallium nitride power device monolithic integrated circuit with a gate driver.

[0112] The present invention provides a gallium nitride power device monolithic integrated circuit with a gate driver. By fabricating a gallium nitride power device and a gate driver on the same substrate 101, a gallium nitride power device monolithic integrated circuit with a gate driver is formed. This significantly reduces the parasitic inductance generated by the interconnection lines between the gate driver and the gallium nitride power device, thereby obtaining a purer gate drive signal and more stable switching characteristics.

[0113] Again, please refer to Figure 2 , Figure 10-14 According to an embodiment of the present invention, there is also provided a method for manufacturing a monolithic integrated circuit of a gallium nitride power device with a gate driver, comprising:

[0114] S21: providing a substrate 101; forming a channel layer 102 and a barrier layer 103 on the substrate 101 in sequence in a direction away from the substrate 101, such as Figure 10 As shown;

[0115] S22: Performing mesa isolation; forming an isolation layer 106 in the barrier layer 103 and the channel layer 102, wherein the isolation layer 106 penetrates the barrier layer 103 and does not contact the substrate 101. After the isolation layer 106 is formed, the device is as follows. Figure 11 As shown;

[0116] S23: depositing a hard mask 113 on the surface of the barrier layer 103;

[0117] S24: etching the hard mask 113 in the first region and the second region to form openings on the hard mask 113. After the openings are formed, the device is as follows: Figure 12 As shown;

[0118] S25: forming a p-GaN layer 104 in the opening, and forming the device after the p-GaN layer 104 is as follows Figure 13 As shown;

[0119] Step S25: forming a p-GaN layer 104 in the opening, specifically comprising:

[0120] S251: epitaxially growing a p-GaN layer 104 in the opening and on the surface of the remaining hard mask 113;

[0121] S252 : removing the remaining hard mask 113 and the p-GaN layer 104 on the surface thereof.

[0122] S26: depositing a metal material on the surface of the barrier layer 103 and annealing to form a source 108 and a drain 109 in the first region, the second region, and the third region;

[0123] S27: forming a gate and a p-GaN gate; the p-GaN gate is formed in the first region and the second region; the gate is formed in the third region; wherein the p-GaN gate includes the p-GaN layer 104 and a gate metal layer 105 on top of the p-GaN layer 104; the gate includes a gate metal layer;

[0124] S28: depositing a passivation layer 107 on top of the gate and the p-GaN gate;

[0125] S29: forming a source metal interconnect layer 110 and a metal field plate 112 in the second region; the source metal interconnect layer is formed on the top of the source electrode 108, and the metal field plate 112 is formed on the surface of the passivation layer 107 on the top of the p-GaN gate; and the metal field plate 112 is electrically connected to the source metal interconnect layer;

[0126] S30: forming a drain metal interconnection layer 111, a gate metal interconnection layer, and forming the source metal interconnection layer 110 in the first region and the third region; the drain metal interconnection layer 111 is formed on the top of the drain 109; the gate metal interconnection layer is formed on the top of the p-GaN gate and the gate; thereby forming a gate driver in the third region and the first region, forming a gallium nitride power device in the second region, forming the drain metal interconnection layer 111, the gate metal interconnection layer, and forming the source metal interconnection layer 110 in the first region and the third region; Figure 14 As shown;

[0127] The third region, the first region and the second region are arranged in sequence along a first direction.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a gallium nitride power device, characterized in that: The method includes: Providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence in a direction away from the substrate; depositing a hard mask on the surface of the barrier layer; etching the hard mask to form an opening in the hard mask; forming a p-GaN layer in the opening; Depositing metal materials on surfaces of the barrier layer at both sides of the p-GaN layer along the first direction and annealing the materials to form a source electrode and a drain electrode; forming a p-GaN gate, wherein the p-GaN gate comprises the p-GaN layer and a gate metal layer formed on top of the p-GaN layer; depositing a passivation layer on top of the p-GaN gate; forming a source metal interconnect layer and a metal field plate; the source metal interconnect layer is formed on the top of the source electrode, and the metal field plate is formed on the surface of the passivation layer on the top of the p-GaN gate; the metal field plate is connected to the source metal interconnect layer; A drain metal interconnection layer and a gate metal interconnection layer are formed.

2. The method for manufacturing a gallium nitride power device according to claim 1, wherein: The specific steps of etching the hard mask to form an opening on the hard mask include: coating a photoresist on the surface of the hard mask; After the photoresist is exposed and developed, the hard mask is etched using the developed photoresist as a mask to form an opening on the hard mask.

3. The method for manufacturing a gallium nitride power device according to claim 1, wherein: Forming a p-GaN layer in the opening specifically includes: Epitaxially growing a p-GaN layer in the opening and on the surface of the remaining hard mask; The remaining hard mask and the p-GaN layer on the surface thereof are removed.

4. The method for manufacturing a gallium nitride power device according to claim 3, wherein: After removing the remaining hard mask and the p-GaN layer on the surface thereof, the method further includes: The p-GaN layer is activated with Mg+.

5. The method for manufacturing a gallium nitride power device according to claim 4, wherein: Before depositing a hard mask on the surface of the barrier layer, the method further comprises: Performing mesa isolation; forming an isolation layer in the barrier layer and the channel layer, wherein the isolation layer penetrates the barrier layer and does not contact the substrate.

6. The method for manufacturing a gallium nitride power device according to claim 5, wherein: The specific steps for forming a p-GaN gate are: Depositing a passivation layer on the surface of the barrier layer; the passivation layer covers the source electrode, the drain electrode, and the p-GaN layer, and fills the gap between the source electrode, the p-GaN layer, and the drain electrode; Etching the passivation layer on top of the p-GaN layer to form a gate hole; A gate metal layer is deposited and filled in the gate hole to form the p-GaN gate.

7. The method for manufacturing a gallium nitride power device according to claim 6, wherein: The specific steps of forming the source metal interconnect layer and the metal field plate are: Etching the passivation layer at the top of the source electrode to form a source opening; A metal material is deposited in the source opening to form a source metal interconnection layer, and a metal material is deposited on the surface of the passivation layer at the top of the p-GaN gate to form a metal field plate.

8. The method for manufacturing a gallium nitride power device according to claim 7, wherein: The specific steps of forming the drain metal interconnection layer and the gate metal interconnection layer are: Depositing the passivation layer on the surface of the metal field plate; Etching the passivation layer at the top of the drain and the top of the p-GaN gate to form a drain opening and a gate opening; Metal materials are deposited in the gate opening and the drain opening respectively to form the drain metal interconnection layer and the gate metal interconnection layer.

9. A gallium nitride power device, characterized in that: include: The gallium nitride power device is manufactured using the method for manufacturing the gallium nitride power device according to any one of claims 1 to 8.

10. A gallium nitride power device monolithic integrated circuit with a gate driver, characterized in that: include: The gallium nitride power device of claim 9, wherein the gallium nitride power device monolithic integrated circuit with a gate driver further comprises a gate driver; and the gate driver and the gallium nitride power device share a same substrate to form the gallium nitride power device monolithic integrated circuit with a gate driver.

11. A method for manufacturing a gallium nitride power device monolithic integrated circuit with a gate driver, characterized in that: include: Providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence in a direction away from the substrate; Conduct countertop isolation; forming an isolation layer in the barrier layer and the channel layer, wherein the isolation layer penetrates the barrier layer and does not contact the substrate; depositing a hard mask on the surface of the barrier layer; etching the hard mask in the first region and the second region to form an opening in the hard mask; forming a p-GaN layer in the opening; Depositing a metal material on the surface of the barrier layer and annealing the metal material to form a source electrode and a drain electrode in the first region, the second region, and the third region; forming a gate and a p-GaN gate; The p-GaN gate is formed in the first region and the second region; the gate is formed in the third region; wherein the p-GaN gate includes the p-GaN layer and a gate metal layer on top of the p-GaN layer; Depositing a passivation layer on top of the gate and the p-GaN gate; forming a source metal interconnect layer and a metal field plate in the second region; the source metal interconnect layer is formed at the top of the source electrode, and the metal field plate is formed on the surface of the passivation layer at the top of the p-GaN gate; and the metal field plate and the source metal interconnect layer are electrically connected; forming a drain metal interconnection layer, a gate metal interconnection layer, and the source metal interconnection layer in the first region and the third region; the drain metal interconnection layer is formed on top of the drain; the gate metal interconnection layer is formed on top of the p-GaN gate and the gate; thereby forming a gate driver in the third region and the first region, and forming a gallium nitride power device in the second region; The third region, the first region and the second region are arranged in sequence along a first direction.

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