Semiconductor element with contact point structure and method for producing the same

Abstract

The present disclosure provides a semiconductor element having a contact structure and a method of manufacturing the semiconductor element. The semiconductor element has a source / drain structure disposed on a semiconductor substrate, and a dielectric layer disposed on the source / drain structure. The semiconductor element also has a polysilicon stack disposed on the source / drain structure and surrounded by the dielectric layer. The polysilicon stack has a first polysilicon layer and a second polysilicon layer disposed on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor element further has a contact structure disposed directly on the polysilicon stack and surrounded by the dielectric layer.

Description

[0001] CROSS-REFERENCE

[0002] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 347,136, filed June 14, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor element and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor element having a contact structure and a method of manufacturing the same. BACKGROUND

[0004] Semiconductor elements are indispensable for many modern applications. As electronic technology advances, semiconductor elements become smaller and smaller while providing better functionality and including larger numbers of integrated circuits. Due to the miniaturization of semiconductor elements, different forms and sizes of semiconductor elements that implement different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed on the integration of semiconductor devices of various forms.

[0005] However, the manufacturing and integration of these semiconductor elements include many complex steps and operations. The integration in these semiconductor elements becomes more and more complex. The increase in complexity of the manufacturing and integration of these semiconductor elements can cause many defects. Accordingly, there is a need to continuously improve the manufacturing process of these semiconductor elements in order to deal with these defects and can enhance their performance.

[0006] The above description of background art is provided merely for the purposes of background information and does not constitute an admission that the background art techniques are prior art to the present disclosure, that any of the above described art is the closest prior art, or that the present disclosure is not entitled to an exception under 37 C.F.R. § 1.131 (a) or (b). SUMMARY

[0007] An embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a source / drain structure disposed on a semiconductor substrate; and a dielectric layer disposed on the source / drain structure. The semiconductor element also includes a polysilicon stack disposed on the source / drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor element further includes a contact structure disposed directly on the polysilicon stack and surrounded by the dielectric layer.

[0008] In some embodiments, the second polysilicon layer is doped with arsenic, boron, or phosphorous. In some embodiments, the polysilicon stack further includes a third polysilicon layer disposed on the second polysilicon layer, and a fourth polysilicon layer disposed on the third polysilicon layer. The third polysilicon layer is undoped, and the fourth polysilicon layer is doped. In some embodiments, a doping concentration of the second polysilicon layer is greater than a doping concentration of the fourth polysilicon layer. In some embodiments, the second polysilicon layer is separated from the dielectric layer by the first polysilicon layer. In some embodiments, the second polysilicon layer directly contacts the dielectric layer. In some embodiments, the contact structure includes a barrier layer and a conductive layer disposed on and surrounded by the barrier layer, wherein the barrier layer includes titanium, titanium nitride, or a combination thereof, and the conductive layer includes tungsten.

[0009] In some embodiments, the barrier layer has a lower portion surrounded by the polysilicon stack. In some embodiments, the source / drain structure includes an epitaxial layer and a silicide layer disposed on the epitaxial layer. In some embodiments, the silicide layer includes tungsten silicide. In some embodiments, the semiconductor element further includes a gate structure extending through the dielectric layer, the silicide layer, and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is adjacent to the polysilicon stack and the contact structure. In some embodiments, the semiconductor element further includes a gate structure extending through the dielectric layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is separated from the silicide layer by the dielectric layer.

[0010] Another embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a source / drain structure disposed on a semiconductor substrate, and a dielectric layer disposed on the source / drain structure. The semiconductor element also includes a conductive contact extending through the dielectric layer and the source / drain structure. The conductive contact includes a conductive layer and a barrier layer covering a sidewall and an undersurface of the conductive layer. A first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the undersurface of the conductive layer.

[0011] In some embodiments, the first thickness is along a first direction, and the second thickness is along a second direction perpendicular to the first direction. In some embodiments, the conductive contact extends into the semiconductor substrate. In some embodiments, the barrier layer includes titanium, titanium nitride, or a combination thereof, and the conductive layer includes tungsten. In some embodiments, the source / drain structure includes an epitaxial layer and a silicide layer disposed on the epitaxial layer. In some embodiments, the silicide layer includes cobalt silicide.

[0012] Yet another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming an epitaxial layer on a semiconductor substrate; and forming a dielectric layer on the epitaxial layer. The method also includes etching the dielectric layer to form an opening; and forming a polysilicon stack in the opening, wherein forming the polysilicon stack includes forming a first polysilicon layer; and forming a second polysilicon layer on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The method further includes forming a contact structure in the opening and on the polysilicon stack.

[0013] In some embodiments, the method further includes forming a gate structure through the dielectric layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is formed prior to forming the opening. In some embodiments, forming the polysilicon stack further includes forming a third polysilicon layer on the second polysilicon layer; and forming a fourth polysilicon layer on the third polysilicon layer. The third polysilicon layer is undoped, and the fourth polysilicon layer is doped. In some embodiments, a doping concentration of the second polysilicon layer is greater than a doping concentration of the fourth polysilicon layer.

[0014] In some embodiments, forming the contact structure includes forming a barrier layer to line the opening and on the polysilicon stack; and after forming the barrier layer, filling a remaining portion of the opening with a conductive layer, wherein the conductive layer is separated from the polysilicon stack by the barrier layer. In some embodiments, the method further includes, prior to forming the opening, forming a silicide layer between the epitaxial layer and the dielectric layer, wherein an upper surface of the silicide layer is exposed by the opening prior to forming the polysilicon stack. In some embodiments, an upper surface of the epitaxial layer is exposed by the opening prior to forming the polysilicon stack, and a silicide layer is formed between the epitaxial layer and the polysilicon stack during formation of the first polysilicon layer.

[0015] Yet another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a source / drain structure on a semiconductor substrate; and forming a dielectric layer on the source / drain structure. The method also includes etching the dielectric layer and the source / drain structure to form an opening; and forming a conductive contact in the opening. Forming the conductive contact includes performing a non-isotropic deposition process to form a barrier layer covering a sidewall and a lower surface of the opening; and after forming the barrier layer, filling a remaining portion of the opening with a conductive layer.

[0016] In some embodiments, the non-isotropic deposition process is a physical vapor deposition (PVD) process. In some embodiments, a first thickness of the barrier layer on the sidewall of the opening is less than a second thickness of the barrier layer on the bottom surface of the opening. The first thickness is along a first direction, the second thickness is along a second direction, and the second direction is perpendicular to the first direction. In some embodiments, the source / drain structure includes an epitaxial layer and a silicide layer on the epitaxial layer, and the opening extends through the silicide layer and the epitaxial layer. In some embodiments, the opening extends into the semiconductor substrate.

[0017] Some embodiments of a semiconductor device structure and a method of fabricating the same are provided in the present disclosure. In some embodiments, the semiconductor device structure includes a polysilicon stack disposed on a source / drain structure; and a contact structure disposed directly on the polysilicon stack. The polysilicon stack has an undoped polysilicon layer and a doped polysilicon layer disposed on the undoped polysilicon layer. By forming the polysilicon stack between the contact structure and the source / drain structure, the contact resistance can be reduced, and the device performance is improved. In addition, in some embodiments, the semiconductor device includes a contact structure having a barrier layer and a conductive layer disposed on and surrounded by the barrier layer. The barrier layer has a first thickness on the sidewall of the conductive layer and a second thickness under the bottom surface of the conductive layer. Since the first thickness is less than the second thickness, the conductive layer can be formed void-free, and the device performance is improved.

[0018] The foregoing has outlined rather broadly the technical features and advantages of the technology of the present disclosure so that the detailed description of the present disclosure that follows can be understood. Additional technical features and advantages of the present disclosure will be described below. Those skilled in the art will appreciate that the conception, upon which, the disclosure is based, can readily be utilized as a basis for the designing of other structures or processes, and that the same can be achieved by using different conceptual steps and equivalents thereof. Such equivalent constructions cannot depart from the scope of the present disclosure defined by the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0019] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference symbols refer to like elements throughout the several views.

[0020] FIG. 1 is a cross-sectional schematic view illustrating a semiconductor device of some embodiments of the present disclosure.

[0021] FIG. 2is a cross-sectional schematic diagram illustrating a semiconductor element of some embodiments of the present disclosure.

[0022] FIG. 3 is a cross-sectional schematic diagram illustrating a semiconductor element of some embodiments of the present disclosure.

[0023] FIG. 4 is a flowchart illustrating a method of manufacturing a semiconductor element of some embodiments of the present disclosure.

[0024] FIG. 5 is a flowchart illustrating a method of manufacturing a semiconductor element of some embodiments of the present disclosure.

[0025] FIG. 6 is a flowchart illustrating a method of manufacturing a semiconductor element of some embodiments of the present disclosure.

[0026] FIG. 7 is a cross-sectional schematic diagram illustrating an intermediate stage of sequentially forming an epitaxial layer, a silicide layer, and a dielectric layer on a semiconductor substrate during formation of a semiconductor element of some embodiments of the present disclosure.

[0027] FIG. 8 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of openings through the dielectric layer, the silicide layer, and the epitaxial layer during formation of a semiconductor element of some embodiments of the present disclosure.

[0028] FIG. 9 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of gate structures in the plurality of openings through the epitaxial layer, the silicide layer, and the dielectric layer during formation of a semiconductor element of some embodiments of the present disclosure.

[0029] FIG. 10 is a cross-sectional schematic diagram illustrating an intermediate stage of etching the dielectric layer to form an opening between the plurality of gate structures during formation of a semiconductor element of some embodiments of the present disclosure.

[0030] FIG. 11 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a first polysilicon layer and a second polysilicon layer in the opening and on the dielectric layer during formation of a semiconductor element of some embodiments of the present disclosure.

[0031] FIG. 12 is a cross-sectional schematic diagram illustrating an intermediate stage of etching back the first polysilicon layer and the second polysilicon layer to form a polysilicon stack in the opening during formation of a semiconductor element of some embodiments of the present disclosure.

[0032] FIG. 13 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a barrier layer in the opening and on the dielectric layer during formation of a semiconductor element of some embodiments of the present disclosure.

[0033] FIG. 14 is a cross-sectional schematic diagram illustrating an intermediate stage of etching the barrier layer during formation of a semiconductor element according to some embodiments of the present disclosure.

[0034] FIG. 15 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a conductive layer in the opening and on the dielectric layer during formation of a semiconductor element according to some embodiments of the present disclosure.

[0035] FIG. 16 is a cross-sectional schematic diagram illustrating an intermediate stage of sequentially forming an opening between the plurality of gate structures during formation of a semiconductor element according to some embodiments of the present disclosure.

[0036] FIG. 17 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a silicide layer and a first polysilicon layer in the opening during formation of a semiconductor element according to some embodiments of the present disclosure.

[0037] FIG. 18 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a second polysilicon layer in the opening during formation of a semiconductor element according to some embodiments of the present disclosure.

[0038] FIG. 19 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a third polysilicon layer in the opening during formation of a semiconductor element according to some embodiments of the present disclosure.

[0039] FIG. 20 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a fourth polysilicon layer in the opening during formation of a semiconductor element according to some embodiments of the present disclosure.

[0040] FIG. 21 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a barrier layer in the opening and on the dielectric layer during formation of a semiconductor element according to some embodiments of the present disclosure.

[0041] FIG. 22 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a conductive layer in the opening and on the dielectric layer during formation of a semiconductor element according to some embodiments of the present disclosure.

[0042] FIG. 23 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of openings to pass through the dielectric layer, the silicide layer, and the epitaxial layer during formation of a semiconductor element according to some embodiments of the present disclosure.

[0043] FIG. 24 is a cross-sectional schematic diagram illustrating an intermediate stage of forming a plurality of barrier layers to line the plurality of openings during formation of a semiconductor element according to some embodiments of the present disclosure.

[0044] BRIEF DESCRIPTION OF REFERENCE NUMERALS:

[0045] 10A: method of making

[0046] 10B: method of making

[0047] 10C: method of making

[0048] 100A: semiconductor element

[0049] 100B: semiconductor element

[0050] 100C: semiconductor element

[0051] 101: semiconductor substrate

[0052] 103: epitaxial layer

[0053] 103T: top surface

[0054] 105: silicide layer

[0055] 105T: top surface

[0056] 107: silicide layer

[0057] 109: source / drain structure

[0058] 111: source / drain structure

[0059] 113: dielectric layer

[0060] 113T: top surface

[0061] 120: opening

[0062] 125: gate structure

[0063] 130: opening

[0064] 133: first polysilicon layer

[0065] 135: second polysilicon layer

[0066] 139: polysilicon stack

[0067] 141: first polysilicon layer

[0068] 143: second polysilicon layer

[0069] 145: third polysilicon layer

[0070] 147: fourth polysilicon layer

[0071] 149: polysilicon stack

[0072] 153: barrier layer

[0073] 153L: lower portion

[0074] 155: conductive layer

[0075] 159: contact point structure

[0076] 163: barrier layer

[0077] 163T: upper surface

[0078] 165: conductive layer

[0079] 165T: upper surface

[0080] 169: contact point structure

[0081] 170: opening

[0082] 170B: lower surface

[0083] 170S: sidewall

[0084] 173: barrier layer

[0085] 175: conductive layer

[0086] 175B: lower surface

[0087] 175S: sidewall

[0088] 179: contact point structure

[0089] S11: step

[0090] S13: step

[0091] S15: step

[0092] S17: step

[0093] S19: step

[0094] S21: step

[0095] S31: step

[0096] S33: step

[0097] S35: step

[0098] S37: step

[0099] S39: step

[0100] S41: step

[0101] S51: step

[0102] S53: step

[0103] S55: step

[0104] S57: step

[0105] S59: step

[0106] T1: first thickness

[0107] T2: second thickness DETAILED DESCRIPTION

[0108] The following description describes specific examples of components and configurations to simplify the present disclosure. These examples are merely intended to provide examples for the sake of illustration and not limitation. For example, although the concepts are described with regard to particular implementations, the concepts can be practiced in any number of arrangements, sizes, components, configurations, and the like. In addition, the terminology and phraseology used is for the purpose of describing the specification to enable a person skilled in the art to make or use the disclosure. The terminology and phraseology used should not be considered as limiting; but rather as descriptive. For example, the terms "comprising," "including," "containing," etc. shall be construed as open-ended terms (i.e., the composition of the application includes at least the recited elements). Further, the terms "a," "an," and "the" followed by a noun, are intended to refer to a singular object only in some versions of the examples, but can, in other versions of the examples, mean two or more such objects, unless otherwise indicated by the context of the example. The terms "first," "second," "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0109] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0110] FIG. 1 is a cross-sectional schematic view illustrating a semiconductor element 100A in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor element 100A includes a source / drain structure 109 disposed on a semiconductor substrate 101, and a dielectric layer 113 disposed on the source / drain structure 109. The source / drain structure 109 includes an epitaxial layer 103 and a silicide layer 105, and the silicide layer 105 is disposed on the epitaxial layer 103. In some embodiments, the epitaxial layer 103 is completely covered by the silicide layer 105, such that the epitaxial layer 103 is separated from the dielectric layer 113 by the silicide layer 109. In some embodiments, the epitaxial layer 103 includes silicon (Si), and the silicide layer 105 includes cobalt silicide (CoSi x ).

[0111] Furthermore, the semiconductor element 100A also includes a plurality of gate structures 125 that extend through the dielectric layer 113, the silicide layer 105, and the epitaxial layer 103. In some embodiments, the plurality of gate structures 125 extend into the semiconductor substrate 101. In some embodiments, the semiconductor element 100A also includes a polysilicon stack 139 disposed in the dielectric layer 113 and on the source / drain structures 109, and a contact structure 159 disposed directly on the polysilicon stack 139. In some embodiments, the polysilicon stack 139 and the contact structure 159 are surrounded by the dielectric layer 113. In some embodiments, the polysilicon stack 139 and the contact structure 159 are disposed between the plurality of gate structures 125.

[0112] The polysilicon stack 139 includes a first polysilicon layer 133 and a second polysilicon layer 135, and the second polysilicon layer 135 is disposed on and surrounded by the first polysilicon layer 133. In some embodiments, the second polysilicon layer 135 is separated from the dielectric layer 113 by the first polysilicon layer 133. It should be understood that, according to some embodiments, the first polysilicon layer 133 is undoped, and the second polysilicon layer 135 is doped. In some embodiments, the second polysilicon layer 135 is doped with arsenic (As), boron (B), or phosphorus (P).

[0113] Furthermore, in some embodiments, the contact structure 159 includes a barrier layer 153 and a conductive layer 155, and the conductive layer 155 is disposed on and surrounded by the barrier layer 153. In some embodiments, the barrier layer 153 includes titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer 155 includes tungsten (W). In some embodiments, the conductive layer 155 is separated from the polysilicon stack 139 by the barrier layer 153. In some embodiments, the barrier layer 153 has a lower portion 153L that is surrounded by the polysilicon stack 139. In some embodiments, the contact structure 159 is electrically connected to the source / drain structures 109 through the polysilicon stack 139. In some embodiments, the semiconductor element 100A is part of a dynamic random access memory (DRAM).

[0114] FIG. 2 is a cross-sectional schematic view illustrating a semiconductor element 100B according to some embodiments of the present disclosure. The semiconductor element 100B can be similar to the semiconductor element 100A, like elements are numbered alike, and certain details or descriptions of the like elements are not repeated.

[0115] In some embodiments, semiconductor element 100B includes a source / drain structure 111 disposed on a semiconductor substrate 101, and a dielectric layer 113 disposed on source / drain structure 111. In some embodiments, source / drain structure 111 includes an epitaxial layer 103 and a silicide layer 107, and silicide layer 107 is disposed on epitaxial layer 103. It is understood that silicide layer 111 partially covers epitaxial layer 107, and other portions of epitaxial layer 107 not covered by silicide layer 111 are covered by dielectric layer 113, which is different from semiconductor element 100A. In some embodiments, epitaxial layer 103 includes silicon, and silicide layer 105 includes cobalt silicide.

[0116] Further, semiconductor element 100B also includes a plurality of gate structures 125 that extend through dielectric layer 113 and epitaxial layer 103. In some embodiments, the plurality of gate structures 125 extend into semiconductor substrate 101. In some embodiments, semiconductor element 100B also includes a polysilicon stack 149 disposed in dielectric layer 113 and on silicide layer 107 of source / drain structure 111, and a contact structure 169 disposed directly on polysilicon stack 149. In some embodiments, polysilicon stack 149 and contact structure 169 are surrounded by dielectric layer 113. In some embodiments, polysilicon stack 149 and contact structure 169 are disposed between the plurality of gate structures 125.

[0117] In some embodiments, polysilicon stack 149 includes a first polysilicon layer 141, a second polysilicon layer 143 disposed on first polysilicon layer 141, a third polysilicon layer 145 disposed on second polysilicon layer 143, and a fourth polysilicon layer 147 disposed on third polysilicon layer 145. In some embodiments, each of first polysilicon layer 141, second polysilicon layer 143, third polysilicon layer 145, and fourth polysilicon layer 147 directly contacts dielectric layer 113.

[0118] It is understood that first polysilicon layer 141 and third polysilicon layer 145 are undoped, and second polysilicon layer 143 and fourth polysilicon layer 147 are doped. In some embodiments, a doping concentration of second polysilicon layer 143 is greater than a doping concentration of fourth polysilicon layer 147. In some embodiments, second polysilicon layer 143 and fourth polysilicon layer 147 are doped with arsenic, boron, or phosphorus. In some embodiments, each of first polysilicon layer 141, second polysilicon layer 143, and third polysilicon layer 145 has a concave upper surface facing contact structure 169. In some embodiments, first polysilicon layer 141, second polysilicon layer 143, and third polysilicon layer 145 have a U-shaped or V-shaped profile.

[0119] In some embodiments, the contact structure 169 includes a barrier layer 163 and a conductive layer 165, and the conductive layer 165 is disposed on and surrounded by the barrier layer 163. In some embodiments, the barrier layer 163 includes titanium, titanium nitride, or a combination thereof, and the conductive layer 165 includes tungsten. In some embodiments, the conductive layer 165 is separated from the polysilicon stack 149 by the barrier layer 163. In some embodiments, the contact structure 169 is electrically connected to the source / drain structure 111 through the polysilicon stack 149. In some embodiments, the upper surface 113T of the dielectric layer 113 is higher than the upper surface 163T of the barrier layer 163 and the upper surface 165T of the conductive layer 165. Further, the upper surface 163T of the barrier layer 163 is substantially coplanar with the upper surface 165T of the conductive layer 165. In some embodiments, the semiconductor element 100B is part of a dynamic random access memory (DRAM).

[0120] FIG. 3 FIG. 1C is a schematic cross-sectional view illustrating a semiconductor element 100C according to some embodiments of the present disclosure. The semiconductor element 100C can be similar to the semiconductor element 100A, and like element numbers represent like elements, and some details or descriptions of the like elements are not repeated.

[0121] In some embodiments, the semiconductor element 100C includes a source / drain structure 109 disposed on a semiconductor substrate 101, and a dielectric layer 113 disposed on the source / drain structure 109. The source / drain structure 109 has an epitaxial layer 103 and a silicide layer 105, and the silicide layer 105 is disposed on the epitaxial layer 103. In some embodiments, the epitaxial layer 103 is completely covered by the silicide layer 105, such that the epitaxial layer 103 is separated from the dielectric layer 113 by the silicide layer 109. In some embodiments, the epitaxial layer 103 includes silicon, and the silicide layer 105 includes cobalt silicide.

[0122] Further, the semiconductor element 100C also includes a plurality of contact structures 179 that penetrate through the dielectric layer 113, the silicide layer 105, and the epitaxial layer 103. In some embodiments, the plurality of contact structures 179 extend into the semiconductor substrate 101. Each of the contact structures 179 includes a barrier layer 173 and a conductive layer 175, and the conductive layer 175 is disposed on and surrounded by the barrier layer 173. In some embodiments, the plurality of barrier layers 173 includes titanium, titanium nitride, or a combination thereof, and the plurality of conductive layers 175 includes tungsten. In some embodiments, the plurality of conductive layers 175 is separated from the dielectric layer 113, the source / drain structure 109, and the semiconductor substrate 101 by the plurality of barrier layers 173.

[0123] It is to be understood that each barrier layer 173 has a first thickness T1 on each sidewall 175S of the corresponding conductive layer 175, and each barrier layer 173 has a second thickness T2 under each bottom surface 175B of the corresponding conductive layer 175. In some embodiments, the fabrication technique of the plurality of barrier layers 173 includes a non-isotropic deposition process such that the first thickness is less than the second thickness. In some embodiments, the non-isotropic deposition process to form the plurality of barrier layers 173 includes a physical vapor deposition (PVD) process. In some embodiments, the semiconductor element 100C is part of a dynamic random access memory (DRAM).

[0124] FIG. 4 is a flowchart illustrating a fabrication method 10A of a semiconductor element (e.g., the semiconductor element 100A) according to some embodiments of the present disclosure, and the fabrication method 10A includes steps S11, S13, S15, S17, S19, and S21. FIG. 5 is a flowchart illustrating a fabrication method 10B of a semiconductor element (e.g., the semiconductor element 100B) according to some embodiments of the present disclosure, and the fabrication method 10B includes steps S31, S33, S35, S37, S39, and S41. FIG. 6 is a flowchart illustrating a fabrication method 10C of a semiconductor element (e.g., the semiconductor element 100C) according to some embodiments of the present disclosure, and the fabrication method 10C includes steps S51, S53, S55, S57, and S59. FIG. 4 steps S11 to S21 of FIG. 5 steps S31 to S41 of FIG. 6 steps S51 to S59 of

[0125] FIG. 7 to FIG. 15 is a cross-sectional view illustrating intermediate stages of forming the semiconductor element 100A according to some embodiments of the present disclosure. As shown in FIG. 7 According to some embodiments, a source / drain structure 105 including an epitaxial layer 103 and a silicide layer 105 is formed on a semiconductor substrate 101. Each step is described in step S11 of the fabrication method 10A as shown in FIG. 4

[0126] ​The semiconductor substrate 101 can be a semiconductor wafer, such as a silicon wafer. Additionally or alternatively, the semiconductor substrate 101 can include elementary semiconductor material, compound semiconductor material, and / or alloy semiconductor material. Examples of elementary semiconductor material can include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor material can include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor material can include, but are not limited to, silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP).

[0127] The source / drain structure 109 can be a raised (or elevated) source / drain structure formed on the semiconductor substrate 101. In some embodiments, the epitaxial layer 103 of the source / drain structure 109 includes silicon, and the silicide layer 105 of the source / drain structure 109 includes cobalt silicide. In some embodiments, the fabrication technique of the epitaxial layer 103 includes an epitaxial growth method, which can include metal-organic chemical vapor deposition (MOCVD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Further, in some embodiments, the fabrication technique of the silicide layer 105 includes a process that includes depositing a metal layer, such as cobalt, and annealing the metal layer to allow the metal layer to react with the epitaxial layer 103 to form the silicide layer 105.

[0128] According to some embodiments, after the source / drain structure 109 is formed, a dielectric layer 113 is formed on the silicide layer 105 of the source / drain structure 109. The various steps are described in more detail as follows: FIG. 4Step S13 in fabrication method 10A is shown. In some embodiments, dielectric layer 113 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with low dielectric constant, or a combination thereof. Fabrication techniques for dielectric layer 113 can include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable process.

[0129] Next, as shown in FIG. 8 , according to some embodiments, a plurality of openings 120 is formed through dielectric layer 113 and source / drain structure 109. In some embodiments, the plurality of openings 120 extends into an upper portion of semiconductor substrate 101 such that a lower surface of each of the plurality of openings 120 is disposed within semiconductor substrate 101. Fabrication techniques for the plurality of openings 120 can include an etching process, and the location of the plurality of openings 120 can be defined by a patterned mask (not shown) formed on dielectric layer 113. The etching process can include a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned mask can be removed.

[0130] Next, as shown in FIG. 9 , according to some embodiments, a plurality of gate structures 125 is formed in the plurality of openings 120. Each of the steps is described in Step S15 in fabrication method 10A, which is shown in FIG. 4 . In some embodiments, the plurality of gate structures 125 is a recessed gate structure for DRAM. Each gate structure 125 includes a gate dielectric (not shown) and a gate electrode (not shown) disposed on and surrounded by the gate dielectric. Each gate dielectric can include silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with high dielectric constant, or a combination thereof, and each gate electrode can include a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, or can be a multi-layer structure including any combination of the above materials.

[0131] In addition, the formation of the plurality of gate structures 125 can include depositing a gate dielectric material (not shown) to line the plurality of openings 120 (see FIG. 8 ) and cover an upper surface of dielectric layer 113; depositing a gate electrode material (not shown) in the remaining portions of the plurality of openings 120 and on the upper surface of dielectric layer 113; and performing a planarization process on the gate dielectric material and the gate electrode material. The deposition process can include CVD, PVD, ALD, or other suitable process. The planarization process can include a chemical mechanical polishing (CMP) process, an etching process, or other suitable process.

[0132] As FIG. 10As shown, according to some embodiments, after the plurality of gate structures 125 is formed, an opening 130 is formed to pass through the dielectric layer 113. In some embodiments, the opening 130 is disposed between the plurality of gate structures 125, and an upper surface 105T of the silicide layer 105 is exposed through the opening 130. Each step is described in FIG. 10A as step S17. FIG. 4 The opening 130 can be formed by an etching process, and the position of the opening 130 can be defined by a patterned mask (not shown) formed on the dielectric layer 113. The etching process can include a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned mask can be removed.

[0133] Then, as shown, according to some embodiments, a first polysilicon layer 133 and a second polysilicon layer 135 are formed in the opening 130 and extend over the upper surface of the dielectric layer 113. In some embodiments, the first polysilicon layer 133 and the second polysilicon layer 135 are formed by a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. FIG. 11

[0134] In some embodiments, the first polysilicon layer 133 is undoped, and the second polysilicon layer 135 is doped with arsenic, boron, or phosphorus. In some embodiments, the second polysilicon layer 135 is in-situ doped during the deposition process. In some embodiments, the second polysilicon layer 135 is not in-situ doped, and an implantation process is performed to dope the second polysilicon layer 135.

[0135] Next, as shown, according to some embodiments, an etch-back process is performed on the first polysilicon layer 133 and the second polysilicon layer 135 to remove some portions of the first polysilicon layer 133 and the second polysilicon layer 135 over the upper surface of the dielectric layer 113, and to remove some portions of the first polysilicon layer 133 and the second polysilicon layer 135 occupying the upper portion of the opening 130. As shown, the remaining portions of the first polysilicon layer 133 and the second polysilicon layer 135 form a polysilicon stack 139. The etch-back process can include a dry etching process, a wet etching process, or a combination thereof. Each step is described in FIG. 10A as step S19. FIG. 12 Further, the first polysilicon layer 133 can be etched back before the deposition process to form the second polysilicon layer 135 is performed. FIG. 4

[0136] ​​It should be understood that although only two polysilicon layers (e.g., first polysilicon layer 133 and second polysilicon layer 135) are displayed in the polysilicon stack 139, the polysilicon stack 139 may have more than two polysilicon layers. In some embodiments, the process of forming the first polysilicon layer 133 and the second polysilicon layer 136 is repeated in a cycle to form more polysilicon layers on the second polysilicon layer 135. For example, an undoped third polysilicon layer is formed on the second polysilicon layer 135, and a fourth polysilicon layer doped with arsenic, boron, or phosphorus is formed on the third polysilicon layer. In this example, the doping concentration of the second polysilicon layer 135 is greater than the doping concentration of the fourth polysilicon layer.

[0137] Next, as FIG. 13 As shown, according to some embodiments, a barrier layer 153 is formed in the opening 130 and on the polysilicon stack 139, and the barrier layer 153 extends on the upper surface of the dielectric layer 113. In some embodiments, the barrier layer 153 comprises titanium, titanium nitride, or a combination thereof. Furthermore, the fabrication technique of the barrier layer 153 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0138] Then, as FIG. 14 As shown, according to some embodiments, an etching process is performed on the barrier layer 153 to remove excess portions of the barrier layer 153 on the upper surface of the dielectric layer 113. This excess portion of the barrier layer 153 can be removed by an etch-back process or a planarization process (e.g., CMP, polishing, or similar processes). In some embodiments, the lower portion 153L of the barrier layer 153 is surrounded by a second polysilicon layer 135. In some embodiments, the barrier layer 153 directly contacts the first polysilicon layer 133 and the second polysilicon layer 135.

[0139] Next, as FIG. 15 As shown, the remaining portion of the opening 130 is filled with a conductive layer 155, and the conductive layer 155 extends on the upper surface of the dielectric layer 113. In some embodiments, the conductive layer 135 comprises tungsten. Furthermore, the fabrication technique of the conductive layer 155 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0140] Next, as FIG. 1 As shown, according to some embodiments, a planarization process is performed on the conductive layer 155 to remove excess portions of the conductive layer 155 on the upper surface of the dielectric layer 113. After the planarization process, a contact structure 159 including the barrier layer 153 and the conductive layer 155 is formed on the polysilicon stack 139 and surrounded by the dielectric layer 113. The various steps are described in... FIG. 4 Step S21 in the preparation method 10A shown.

[0141] The planarization process may include a CMP process. After the contact structure 159 is formed, the semiconductor device 100A is obtained. Since a polysilicon stack 139 having an undoped polysilicon layer (e.g., a first polysilicon layer 133) and a doped polysilicon layer on top of the undoped polysilicon layer (e.g., a second polysilicon layer 135) is formed between the source / drain structure 109 and the contact structure 159, the contact resistance can be reduced. Therefore, the device performance of the semiconductor device 100A can be enhanced.

[0142] FIG. 16 to FIG. 22 This is a cross-sectional schematic diagram, illustrating a semiconductor element 100B from a structure similar to... FIG. 9 The steps shown are intermediate stages in a series of steps. As shown, one difference between semiconductor elements 100A and 100B is the location of the silicide layer. FIG. 16 As shown, according to some embodiments, an epitaxial layer 103 is formed between a dielectric layer 113 and a semiconductor substrate 101, and the plurality of gate structures 125 are formed to pass through the dielectric layer 113 and the epitaxial layer 103 and extend into the upper portion of the semiconductor substrate 101. The various steps are described in... FIG. 5 Steps S31 to S35 in the fabrication method 10B shown. Some materials and processes used to form the epitaxial layer 103, dielectric layer 113 and the plurality of gate structures 125 in the semiconductor device 100A are similar to or the same as those used to form the epitaxial layer 103, dielectric layer 113 and gate structures 125 in the semiconductor device 100A, and their detailed descriptions will not be repeated herein.

[0143] like FIG. 16 As shown, according to some embodiments, after the plurality of gate structures 125 are formed, an opening 130 is formed to pass through the dielectric layer 113 and expose the upper surface 103T of the epitaxial layer 103. The various steps are described in... FIG. 5 Step S37 in the fabrication method 10B shown. Some processes for forming the opening 130 in the semiconductor element 100B are similar to or the same as those for forming the opening 130 in the semiconductor element 100A, and their detailed descriptions will not be repeated herein.

[0144] Next, as FIG. 17 As shown, according to some embodiments, a silicide layer 107 and a first polysilicon layer 141 are formed in the opening 130. In some embodiments, the silicide layer 107 includes cobalt silicide. The silicide layer 107 and the underlying epitaxial layer 103 together form the source / drain structure 111 of the semiconductor device 100B.

[0145] In some embodiments, during the formation of the first polysilicon layer 141, a silicide layer 107 is formed between the epitaxial layer 103 and the first polysilicon layer 141, and the silicide layer 107 is surrounded by a dielectric layer 113. In some embodiments, the first polysilicon layer 141 is undoped, and its fabrication technique includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. After the deposition process, an etch-back process may be performed to remove excess portions of the first polysilicon layer 141 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0146] Next, as FIG. 18 As shown, according to some embodiments, a second polysilicon layer 143 is formed in the opening 130 and on the first polysilicon layer 141. In some embodiments, the fabrication technique of the second polysilicon layer 143 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. In some embodiments, the second polysilicon layer 143 is doped with arsenic, boron, or phosphorus, and the second polysilicon layer 143 is in-situ doped during the deposition process. In some embodiments, the second polysilicon layer 143 is not in-situ doped, but rather an implantation process is performed to dope the second polysilicon layer 143. After the deposition process, an etch-back process may be performed to remove the removed portion of the second polysilicon layer 143 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0147] Then, as FIG. 19 As shown, according to some embodiments, a third polysilicon layer 145 is formed in the opening 130 and on the second polysilicon layer 143. In some embodiments, the third polysilicon layer 145 is undoped, and its fabrication technique includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. After the deposition process, an etching process may be performed to remove excess portions of the third polysilicon layer 145 on the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0148] Next, as FIG. 20 As shown, according to some embodiments, a fourth polysilicon layer 147 is formed in the opening 130 and on the third polysilicon layer 145. In some embodiments, the fabrication technique of the fourth polysilicon layer 147 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. In some embodiments, the fourth polysilicon layer 147 is doped with arsenic, boron, or phosphorus, and the doping concentration of the second polysilicon layer 143 is greater than the doping concentration of the fourth polysilicon layer 147.

[0149] In some embodiments, the fourth polysilicon layer 147 is in-situ doped during the deposition process. In some embodiments, the fourth polysilicon layer 147 is not in-situ doped, and an implantation process is performed to dope the fourth polysilicon layer 147. After the deposition process, an etch-back process can be performed to remove excess portions of the fourth polysilicon layer 147 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113. After the etch-back process is performed, the plurality of excess portions of the fourth polysilicon layer 147, the third polysilicon layer 145, the second polysilicon layer 143, and the first polysilicon layer 141 form a polysilicon stack 149 occupying the lower portion of the opening 130, according to some embodiments. The steps are described in steps S39 of the fabrication method 10B as shown in FIG. 5 In some embodiments, the polysilicon stack 149 has a substantially planar upper surface.

[0150] It should be appreciated that the polysilicon stack 149 can have more than four polysilicon layers. In some embodiments, the process of forming the third polysilicon layer 145 and the fourth polysilicon layer 147 is repeated for one cycle to form more polysilicon layers on the fourth polysilicon layer 147. For example, an undoped fifth polysilicon layer is formed on the fourth polysilicon layer 147, and a sixth polysilicon layer doped with arsenic, boron, or phosphorus is formed on the fifth polysilicon layer. In these examples, the doping concentration of the fourth polysilicon layer 147 is greater than the doping concentration of the sixth polysilicon layer, and the uppermost polysilicon layer has a substantially planar upper surface.

[0151] Next, as shown in FIG. 21 According to some embodiments, a barrier layer 163 is formed in the opening 130 and on the polysilicon stack 149, and the barrier layer 163 extends on the upper surface of the dielectric layer 113. In some embodiments, the barrier layer 163 includes titanium, titanium nitride, or a combination thereof. Further, the fabrication technique of the barrier layer 163 can include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0152] Then, as shown in FIG. 2 According to some embodiments, a conductive layer 165 is formed on the barrier layer 163, and the remaining portion of the opening 130 on the barrier layer 163 is filled with the conductive layer 165. In some embodiments, the conductive layer 165 includes tungsten. Further, the fabrication technique of the conductive layer 165 can include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0153] Next, as shown in FIG. 2As shown, according to some embodiments, a planarization process can be performed to remove the plurality of excess portions of the barrier layer 163 and the conductive layer 165 on the upper surface of the dielectric layer 113. After the planarization process, a contact structure 169 including the barrier layer 163 and the conductive layer 165 is formed on the polysilicon stack 149 and surrounded by the dielectric layer 113. The various steps are described in... FIG. 5 Step S41 in the preparation method 10B shown.

[0154] The planarization process may include a CMP process, a polishing process, an etch-back process, or similar methods. In some embodiments, after the planarization process, the upper surface 113T of the dielectric layer 113 is higher than the upper surface 163T of the barrier layer 163 and the upper surface 165T of the conductive layer 165. In some embodiments, after the planarization process, the upper surface 113T of the dielectric layer 113 is substantially coplanar with the upper surface of the barrier layer 163 and the upper surface 165T of the conductive layer 165. After the contact structure 169 is formed, the semiconductor device 100B is obtained.

[0155] Because a polysilicon stack 149 with multiple interleaved undoped polysilicon layers (e.g., the first polysilicon layer 141 and the third polysilicon layer 145) and multiple doped polysilicon layers (e.g., the second polysilicon layer 143 and the fourth polysilicon layer 147) is formed between the source / drain structure 111 and the contact structure 169, the contact resistance can be reduced. Therefore, the device performance of the semiconductor device 100B can be enhanced.

[0156] FIG. 23 and FIG. 24 This is a cross-sectional schematic diagram, illustrating a semiconductor device 100C from a structure similar to... FIG. 7 The steps shown are intermediate stages in the sequence of steps that continue. For example... FIG. 23 As shown, a source / drain structure 109, including an epitaxial layer 103 and a silicide layer 105, is formed on a semiconductor substrate 101, and a dielectric layer 113 is formed on the source / drain structure 109. The various steps are described in... FIG. 6 Steps S51 and S53 in the fabrication method 10C shown. Some materials and processes used to form the epitaxial layer 103, silicide layer 105 and dielectric layer 113 in the semiconductor device 100C are similar to or the same as those used to form the epitaxial layer 103, silicide layer 105 and dielectric layer 113 in the semiconductor device 100A, and their detailed descriptions will not be repeated herein.

[0157] Please refer to the following: FIG. 23 According to some embodiments, a plurality of openings 170 are formed to pass through the dielectric layer 113 and the source / drain structure 109. The various steps are described in... FIG. 6Step S55 in fabrication method 10C is shown. Some processes for forming the plurality of openings 170 in semiconductor element 100C are similar to or the same as those for forming the plurality of openings 120 (please refer to FIG. 8 ) in semiconductor element 100A, and detailed descriptions thereof are not repeated herein. In some embodiments, the plurality of openings 170 extend into the upper portion of semiconductor substrate 101.

[0158] Next, as shown in FIG. 24 , according to some embodiments, a non-isotropic deposition process is performed to form a plurality of barrier layers 173 to cover the sidewalls 170S and the bottom surfaces 170B of the plurality of openings 170. Each step is described in step S57 in fabrication method 10C as shown in FIG. 6 . In some embodiments, the plurality of barrier layers 173 comprises titanium, titanium nitride, or a combination thereof. In some embodiments, the non-isotropic deposition process is performed to ensure that a first thickness T1 of the plurality of barrier layers 173 on the sidewalls 170S of the plurality of openings 170 is less than a second thickness T2 of the plurality of barrier layers 173 on the bottom surfaces 170B of the plurality of openings 170. In some embodiments, the non-isotropic deposition process comprises a physical vapor deposition (PVD) process.

[0159] Next, as shown in FIG. 3 , according to some embodiments, a plurality of conductive layers 175 is formed in the plurality of excess portions of the plurality of openings 170 on the plurality of barrier layers 173, and the plurality of contact point structures 179 comprising the plurality of barrier layers 173 and the plurality of conductive layers 175 is formed. Each step is described in step S59 in fabrication method 10C as shown in FIG. 6 . In some embodiments, the plurality of conductive layers 175 comprises tungsten. Furthermore, the fabrication technique of the plurality of conductive layers 175 can comprise a deposition process and a subsequent planarization process. After the plurality of contact point structures 179 is formed, semiconductor element 100C is obtained.

[0160] Since the first thickness of the plurality of barrier layers 173 is less than the second thickness T2 of the plurality of barrier layers 173, the plurality of barrier layers 173 can avoid overhanging at the upper corners of the plurality of openings 170. Therefore, the element performance of semiconductor element 100C can be enhanced.

[0161] Multiple embodiments of semiconductor elements 100A, 100B, 100C and methods of making the same are provided in the present disclosure. In some embodiments, each semiconductor element 100A, 100B includes a polysilicon stack (e.g., polysilicon stack 139, 149) disposed on a source / drain structure (e.g., source / drain structure 109, 111), and a contact (e.g., contact structure 159, 169) disposed directly on the polysilicon stack. The polysilicon stack includes an undoped polysilicon layer (e.g., polysilicon layer 133, 141, 145) and a doped polysilicon layer (e.g., polysilicon layer 135, 143, 147) disposed on the undoped polysilicon layer. By forming the polysilicon stack between the contact structure and the source / drain structure, the contact resistance can be reduced, and the element performance is improved.

[0162] In some embodiments, semiconductor element 100C includes a contact structure (e.g., contact structure 179) having a barrier layer (e.g., barrier layer 173) and a conductive layer (e.g., conductive layer 175) disposed on and surrounded by the barrier layer. The barrier layer has a first thickness on the sidewall of the conductive layer and a second thickness under the lower surface of the conductive layer. Since the first thickness is less than the second thickness, the conductive layer can be formed without voids, and the element performance is improved.

[0163] An embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a source / drain structure disposed on a semiconductor substrate, and a dielectric layer disposed on the source / drain structure. The semiconductor element also includes a polysilicon stack disposed on the source / drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor element further includes a contact structure disposed directly on the polysilicon stack and surrounded by the dielectric layer.

[0164] Another embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a source / drain structure disposed on a semiconductor substrate, and a dielectric layer disposed on the source / drain structure. The semiconductor element also includes a conductive contact penetrating through the dielectric layer and the source / drain structure. The conductive contact includes a conductive layer and a barrier layer covering a sidewall and a lower surface of the conductive layer. A first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the lower surface of the conductive layer.

[0165] Yet another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming an epitaxial layer on a semiconductor substrate; and forming a dielectric layer on the epitaxial layer. The method also includes etching the dielectric layer to form an opening; and forming a polysilicon stack in the opening, wherein forming the polysilicon stack includes forming a first polysilicon layer; and forming a second polysilicon layer on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The method further includes forming a contact structure in the opening and on the polysilicon stack.

[0166] Yet another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a source / drain structure on a semiconductor substrate; and forming a dielectric layer on the source / drain structure. The method also includes etching the dielectric layer and the source / drain structure to form an opening; and forming a conductive contact in the opening. Forming the conductive contact includes performing a non-isotropic deposition process to form a barrier layer covering a sidewall and a bottom surface of the opening; and after forming the barrier layer, filling a remaining portion of the opening with a conductive layer.

[0167] The embodiments of the present disclosure have some advantageous features. In some embodiments, by forming a polysilicon stack between the source / drain structure and the contact structure, the contact resistance can be reduced, and the device performance can be improved. In some embodiments, by forming a conductive contact with a barrier layer having different thicknesses, a conductive layer formed on the barrier layer can be void-free, and the device performance can be enhanced.

[0168] While the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, various processes described above can be implemented in different methodologies and in other sequences, and various steps can be modified, eliminated or added.

[0169] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the present application is intended to be illustrative, but not limiting, of the scope of the present application. Thus, it is intended that the scope of the present application should be governed by the appended claims and their equivalents, rather than by the recited method steps, combinations of elements, or groups of elements.

Claims

1. A semiconductor element, comprising: A source / drain structure is disposed on a semiconductor substrate; A dielectric layer is disposed on the source / drain structure; A polysilicon stack is disposed on the source / drain structure and surrounded by the dielectric layer, wherein the polysilicon stack includes a first polysilicon layer and a second polysilicon layer, the second polysilicon layer is disposed on the first polysilicon layer, the first polysilicon layer is undoped, and the second polysilicon layer is doped. as well as A contact point structure is directly disposed on the polysilicon stack and surrounded by the dielectric layer. The polysilicon stack further includes: a third polysilicon layer disposed on the second polysilicon layer, wherein the third polysilicon layer is undoped; And a fourth polysilicon layer is disposed on the third polysilicon layer, wherein the fourth polysilicon layer is doped. The doping concentration of the second polysilicon layer is greater than that of the fourth polysilicon layer.

2. The semiconductor device of claim 1, wherein the second polysilicon layer is doped with arsenic, boron or phosphorus.

3. The semiconductor device of claim 1, wherein the second polysilicon layer is separated from the dielectric layer by the first polysilicon layer.

4. The semiconductor device of claim 1, wherein the second polysilicon layer is in direct contact with the dielectric layer.

5. The semiconductor device of claim 1, wherein the contact structure includes a barrier layer and a conductive layer, the conductive layer being disposed on and surrounded by the barrier layer, wherein the barrier layer comprises titanium, titanium nitride, or a combination thereof, and the conductive layer comprises tungsten.

6. The semiconductor device of claim 5, wherein the barrier layer has a lower portion surrounded by the polysilicon stack.

7. The semiconductor device of claim 1, wherein the source / drain structure includes an epitaxial layer and a silicide layer, the silicide layer being disposed on the epitaxial layer.

8. The semiconductor device of claim 7, wherein the silicide layer comprises tungsten silicide.

9. The semiconductor device of claim 7, further comprising a gate structure passing through the dielectric layer, the silicide layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate and is adjacent to the polysilicon stack and the contact structure.

10. The semiconductor device of claim 7, further comprising a gate structure passing through the dielectric layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate and is separated from the silicide layer by the dielectric layer.

11. A method for fabricating a semiconductor device, comprising: An epitaxial layer is formed on a semiconductor substrate; A dielectric layer is formed on the epitaxial layer; The dielectric layer is etched to form an opening; A polysilicon stack is formed in the opening, wherein the step of forming the polysilicon stack includes: Forming a first polysilicon layer, wherein the first polysilicon layer is undoped; and A second polysilicon layer is formed on the first polysilicon layer, wherein the second polysilicon layer is doped; A contact point structure is formed in the opening and on the polysilicon stack; and A gate structure is formed to pass through the dielectric layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is formed before the opening is formed.

12. The method for fabricating a semiconductor device as claimed in claim 11, wherein the step of forming the polysilicon stack further comprises: A third polysilicon layer is formed on the second polysilicon layer, wherein the third polysilicon layer is undoped; as well as A fourth polysilicon layer is formed on the third polysilicon layer, wherein the fourth polysilicon layer is doped.

13. The method for fabricating a semiconductor device as claimed in claim 12, wherein a doping concentration of the second polysilicon layer is greater than a doping concentration of the fourth polysilicon layer.

14. The method for fabricating a semiconductor element as claimed in claim 11, wherein the step of forming the contact structure comprises: A barrier layer is formed to reinforce the opening and is placed on the polysilicon stack; as well as After the barrier layer is formed, a remaining portion of the opening is filled with a conductive layer, wherein the conductive layer is separated from the polysilicon stack by the barrier layer.

15. The method for fabricating a semiconductor device as claimed in claim 11, further comprising forming a silicide layer between the epitaxial layer and the dielectric layer before the opening is formed, wherein an upper surface of the silicide layer is exposed through the opening before the polysilicon stack is formed.

16. The method of fabricating a semiconductor device as claimed in claim 11, wherein an upper surface of the epitaxial layer is exposed through the opening prior to the formation of the polysilicon stack, and a silicide layer is formed between the epitaxial layer and the polysilicon stack during the formation of the first polysilicon layer.

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