Multi-threshold CMOS based ternary D flip-flop

Abstract

The application discloses a kind of three-value D-type flip-flop based on multi-threshold CMOS, including inverter, three-value or gate, first three-value and gate and second three-value and gate, inverter includes 1 PMOS tube and 1 NMOS tube, first three-value and gate and second three-value and gate include 8 PMOS tubes and 6 NMOS tubes respectively, three-value or gate includes 6 PMOS tubes and 8 NMOS tubes, by setting the width-length ratio of PMOS tube and NMOS tube in inverter, three-value or gate, first three-value and gate and second three-value and gate sets threshold voltage, inverter, three-value or gate, first three-value and gate and second three-value and gate are connected to realize three-value data storage function;Advantages are capable of processing three-value signal, when used in large-scale digital integrated circuit system, the processing amount of redundant signal can be reduced, so that the processing speed of large-scale digital integrated circuit system is improved, the amount of use of transistor and the area of chip are reduced, cost is reduced.

Description

Technical Field

[0001] This invention relates to a ternary D-type flip-flop, and more particularly to a ternary D-type flip-flop based on multi-threshold CMOS. Background Technology

[0002] Flip-flops, capable of temporarily storing data, have always been a fundamental and crucial component of sequential logic circuits. Modern flip-flops are typically binary, with the most common type being the binary D-type flip-flop. While existing binary D-type flip-flops have a simple circuit structure, in large-scale digital integrated circuit systems, they can only process binary signals. This increases the amount of redundant signal processing, resulting in slower processing speeds, larger transistor counts, larger chip area, and higher costs for large-scale digital integrated circuit systems. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a ternary D-type flip-flop based on multi-threshold CMOS. This ternary D-type flip-flop can process ternary signals. When used in large-scale digital integrated circuit systems, it can reduce the amount of redundant signal processing, thereby increasing the processing speed of large-scale digital integrated circuit systems, reducing the number of transistors used and the chip area, and reducing costs.

[0004] The technical solution adopted by this invention to solve the above-mentioned technical problem is as follows: a ternary D-type flip-flop based on multi-threshold CMOS, comprising an inverter, two ternary AND gates, and a ternary OR gate. The inverter has an input terminal and an output terminal. The two ternary AND gates and the ternary OR gate each have a first input terminal, a second input terminal, and an output terminal. The two ternary AND gates are referred to as the first ternary AND gate and the second ternary AND gate, respectively. The input terminal of the inverter is connected to the first input terminal of the second ternary AND gate, and its connection terminal is the clock terminal of the ternary D-type flip-flop for receiving a clock signal. The second input terminal of the second ternary AND gate is the input terminal of the ternary D-type flip-flop. The output terminal of the inverter is connected to the first input terminal of the second ternary AND gate. The first three-valued AND gate is connected to the second input terminal of the first three-valued AND gate, and the first input terminal of the first three-valued OR gate is connected to the output terminal of the three-valued D-type flip-flop. The output terminal of the first three-valued AND gate is connected to the first input terminal of the three-valued OR gate, and the output terminal of the second three-valued AND gate is connected to the second input terminal of the three-valued OR gate. The inverter includes a first MOS transistor and a second NMOS transistor. The first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor. The width-to-length ratio of the first MOS transistor is 355n / 60n, and the width-to-length ratio of the second MOS transistor is 120n / 60n. The source and substrate of the first MOS transistor are both connected to a power supply. The gate of the first MOSFET is connected to the gate of the second MOSFET, and their connection terminal is the input terminal of the inverter. The drain of the first MOSFET is connected to the drain of the second MOSFET, and their connection terminal is the output terminal of the inverter. The source and substrate of the second MOSFET are both grounded. Each of the three-valued AND gates includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, and a sixteenth MOSFET. The third MOSFET, the fifth MOSFET, the seventh MOSFET, the fifth MOSFET, the seventh MOSFET, the fifth MOSFET, the seventh MOSFET, the sixth MOSFET, the seventh ... The OS transistor, the eighth MOS transistor, the tenth MOS transistor, and the twelfth MOS transistor are all PMOS transistors. The fourth MOS transistor, the sixth MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, and the sixteenth MOS transistor are all NMOS transistors. The aspect ratio of the third MOS transistor is 355n / 60n, the aspect ratio of the fourth MOS transistor is 120n / 60n, the aspect ratio of the fifth MOS transistor is 200n / 60n, the aspect ratio of the sixth MOS transistor is 200n / 60n, and the aspect ratio of the seventh MOS transistor is 200n / 60n.The aspect ratio of the eighth MOS transistor is 355n / 60n, the aspect ratio of the ninth MOS transistor is 120n / 60n, the aspect ratio of the tenth MOS transistor is 200n / 60n, the aspect ratio of the eleventh MOS transistor is 200n / 60n, the aspect ratio of the twelfth MOS transistor is 355n / 60n, the aspect ratio of the thirteenth MOS transistor is 120n / 60n, the aspect ratio of the fourteenth MOS transistor is 200n / 60n, the aspect ratio of the fifteenth MOS transistor is 200n / 60n, the aspect ratio of the sixteenth MOS transistor is 200n / 60n, and the source of the third MOS transistor, the substrate of the third MOS transistor, and the aspect ratio of the... The source of the fifth MOSFET, the substrate of the seventh MOSFET, the source of the eighth MOSFET, the substrate of the tenth MOSFET, the source of the twelfth MOSFET, and the substrate of the twelfth MOSFET are all connected to a power supply. The gates of the third MOSFET, the fourth MOSFET, the fifth MOSFET, the sixth MOSFET, and the source of the sixteenth MOSFET are connected, and their connection terminals are the second input terminals of the AND gate. The drains of the third MOSFET, the fourth MOSFET, and the sixth MOSFET are connected. The fourth MOSFET... The source, substrate of the fourth MOS transistor, and substrate of the sixth MOS transistor are all grounded. The drain of the fifth MOS transistor, the drain of the sixth MOS transistor, the gate of the seventh MOS transistor, and the gate of the fifteenth MOS transistor are connected. The drain of the seventh MOS transistor, the drain of the fourteenth MOS transistor, and the drain of the fifteenth MOS transistor are connected, and their connection terminals are the output terminals of the AND gate. The gate of the eighth MOS transistor, the gate of the ninth MOS transistor, the source of the seventh MOS transistor, the gate of the tenth MOS transistor, and the gate of the eleventh MOS transistor are connected, and their connection terminals are the first input terminals of the AND gate. The drain of the ninth MOS transistor, the drain of the tenth MOS transistor, and the source of the eleventh MOS transistor are connected. The source of the ninth MOS transistor, the substrate of the ninth MOS transistor, the source of the eleventh MOS transistor, the substrate of the eleventh MOS transistor, the source of the thirteenth MOS transistor, the substrate of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, the substrate of the fourteenth MOS transistor, the substrate of the fifteenth MOS transistor, and the substrate of the sixteenth MOS transistor are all grounded. The drain of the tenth MOS transistor, the drain of the eleventh MOS transistor, the gate of the twelfth MOS transistor, the gate of the thirteenth MOS transistor, and the gate of the fourteenth MOS transistor are connected.The drain of the twelfth MOSFET, the drain of the thirteenth MOSFET, and the gate of the sixteenth MOSFET are connected; the source of the fifteenth MOSFET and the drain of the sixteenth MOSFET are connected; the ternary OR gate includes the seventeenth, eighteenth, nineteenth, twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, twenty-ninth, and thirtieth MOSFETs. All twenty-ninth MOSFETs are PMOS transistors, while the eighteenth, twentieth, twenty-second, twenty-sixth, twenty-eighth, and thirtieth MOSFETs are NMOS transistors. The seventeenth MOSFET has a width-to-length ratio of 355n / 60n, the eighteenth MOSFET has a width-to-length ratio of 120n / 60n, the nineteenth MOSFET has a width-to-length ratio of 200n / 60n, the twentieth MOSFET has a width-to-length ratio of 200n / 60n, the twenty-first MOSFET has a width-to-length ratio of 355n / 60n, and the twenty-second MOSFET has a width-to-length ratio of 1. The aspect ratios of the 23rd, 24th, 25th, 26th, 27th, 28th, 29th, and 30th MOSFETs are 200n / 60n, respectively. The 23rd MOSFET has a width-to-length ratio of 200n / 60n. The 24th MOSFET has a width-to-length ratio of 200n / 60n. The 25th MOSFET has a width-to-length ratio of 355n / 60n. The 26th MOSFET has a width-to-length ratio of 120n / 60n. The 27th MOSFET has a width-to-length ratio of 200n / 60n. The 28th MOSFET has a width-to-length ratio of 200n / 60n. The 29th MOSFET has a width-to-length ratio of 200n / 60n. The 30th MOSFET has a width-to-length ratio of 200n / 60n. The source and substrate of the 17th MOSFET are also mentioned. The substrate of the nineteenth MOS transistor, the source of the twenty-first MOS transistor, the substrate of the twenty-first MOS transistor, the source of the twenty-third MOS transistor, the substrate of the twenty-third MOS transistor, the substrate of the twenty-fourth MOS transistor, the substrate of the twenty-ninth MOS transistor, the source of the twenty-fifth MOS transistor, the substrate of the twenty-fifth MOS transistor, and the substrate of the twenty-seventh MOS transistor are all connected to a power supply. The gate of the seventeenth MOS transistor, the gate of the eighteenth MOS transistor, the source of the nineteenth MOS transistor, and the source of the thirtieth MOS transistor are connected, and their connection terminals are the first input terminals of the ternary OR gate.The drains of the seventeenth MOSFET, the eighteenth MOSFET, the gate of the nineteenth MOSFET, and the gate of the twentieth MOSFET are connected. The sources, substrates, and groundings of the eighteenth MOSFET, the twentieth MOSFET, the twentieth MOSFET, the twentieth MOSFET, the twentieth MOSFET, and the twenty-second MOSFET are all grounded. The drains of the nineteenth MOSFET, the twentieth MOSFET, the twenty-first MOSFET, the twenty-second MOSFET, and the twenty-fourth MOSFET are connected. The drains of the twenty-first MOSFET, the twenty-second MOSFET, and the twenty-third MOSFET are connected. The drains of the twenty-third MOSFET, the twenty-ninth MOSFET, and the thirtieth MOSFET are connected, and their connection terminals are as described above. The output terminal of the ternary OR gate is connected to the source of the 24th MOSFET, the gate of the 25th MOSFET, the gate of the 26th MOSFET, the gate of the 27th MOSFET, and the gate of the 28th MOSFET, with the connection terminal serving as the second input terminal of the ternary OR gate. The drain of the 24th MOSFET is connected to the source of the 29th MOSFET, and the drains of the 25th MOSFET, the 26th MOSFET, and the 27th MOSFET are connected. The source, substrate, source, substrate, and substrate of the 26th MOSFET, and the 30th MOSFET are all grounded. The drains of the 27th MOSFET, the 28th MOSFET, the gate of the 29th MOSFET, and the gate of the 30th MOSFET are connected.

[0005] Compared with the prior art, the advantage of this invention lies in constructing a ternary D-type flip-flop based on multi-threshold CMOS using an inverter, two ternary AND gates, and a ternary OR gate. The inverter has an input terminal and an output terminal. The two ternary AND gates and the ternary OR gate each have a first input terminal, a second input terminal, and an output terminal. The two ternary AND gates are referred to as the first ternary AND gate and the second ternary AND gate, respectively. The input terminal of the inverter and the first input terminal of the second ternary AND gate are connected, and their connection terminal is the clock terminal of the ternary D-type flip-flop for receiving a clock signal. The second input terminal of the second ternary AND gate is the input terminal of the ternary D-type flip-flop. The output terminal of the inverter is connected to the second input terminal of the first ternary AND gate, and the first input terminal of the first ternary AND gate is connected to the output terminal of the ternary OR gate. The output terminals are connected to the output terminals of a ternary D-type flip-flop. The output terminal of the first ternary AND gate is connected to the first input terminal of the ternary OR gate, and the output terminal of the second ternary AND gate is connected to the second input terminal of the ternary OR gate. The inverter includes two MOS transistors, the first and the second. Each ternary AND gate includes 16 MOS transistors, from the third to the sixteenth. The ternary OR gate includes 16 MOS transistors, from the seventeenth to the thirtieth. Each MOS transistor in the inverter, the two ternary AND gates, and the ternary OR gate has a specific width-to-length ratio, i.e., a set threshold voltage, thus enabling the implementation of ternary logic functions. When the input signal connected to the second input terminal of the ternary AND gate is logic 0, ... When the seventh MOSFET is off, the output of the AND gate is logic 0. When the input signal to the first input of the AND gate is logic 0, the source input of the seventh MOSFET is 0V, and the fifth MOSFET is off. At this time, the output of the AND gate is logic 0. When the input signal to the second input of the AND gate is logic 2, the seventh MOSFET is on. When the input signal to the first input is logic 1, both the fourteenth and sixteenth MOSFETs are off, and the output signal of the AND gate is the same as the source voltage of the seventh MOSFET, which is logic 1. When the input signal to the first input is logic 2, both the fourteenth and sixteenth MOSFETs are off, and the output of the AND gate is logic 0. The output signal is the same as the source voltage of the seventh MOSFET, which is logic 2. The ternary AND gate can correctly implement the logic function of the ternary AND gate. When the input signal connected to the first input terminal of the ternary OR gate is logic 2, the twenty-third MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 2. When the input signal connected to the second input terminal of the ternary OR gate is logic 2, the twenty-ninth MOSFET is turned on, the source of the twenty-fourth MOSFET is at a high level, and when the input signal connected to the first input terminal of the ternary OR gate is logic 0 or 1, the twenty-fourth MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 2. When the input signal connected to the first input terminal of the ternary OR gate is logic 2, the twenty-third MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 2.When the input signal to the first input terminal of the ternary OR gate is logic 1, the 24th MOSFET is turned on and the 23rd MOSFET is turned off. When the input signal to the second input terminal of the ternary OR gate is logic 0, the 29th MOSFET is turned off and the 26th MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 1. When the input signal to the second input terminal of the ternary OR gate is logic 1, the 29th MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 1. When the input signal to the first input terminal of the ternary OR gate is logic 0, the 24th MOSFET is turned on and the 23rd MOSFET is turned off. When the S-MOSFET is turned on and the input signal to the second input terminal of the ternary OR gate is logic 0, the twenty-ninth MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 0. When the input signal to the second input terminal of the ternary OR gate is logic 1, the twenty-ninth MOSFET is turned on, and the output terminal of the ternary OR gate outputs logic 1. When the input signal to the second input terminal of the ternary OR gate is logic 0, the thirtieth MOSFET is turned on, and the output terminal of the ternary OR gate outputs the input signal to its first input terminal. The ternary OR gate can correctly implement the logic function of a ternary OR gate, that is, the output signal value is two... The input signal takes the larger value. When the clock input of the ternary D-type flip-flop is connected to the clock signal CP and the input input is connected to the input signal D, when the clock signal CP=0, the output of the second ternary AND gate outputs logic 0, and the output of the first ternary AND gate outputs the signal previously output by the output of the ternary D-type flip-flop. The logic 0 output by the second ternary AND gate and the signal output by the first ternary AND gate are passed through a ternary OR gate to output signal Q at the output of the ternary D-type flip-flop. When the clock signal CP=2, the output of the second ternary AND gate outputs the input signal D, and the output of the first ternary AND gate outputs logic 0. The input signal D and logic 0 are passed through a ternary OR gate to output signal Q at the output of the ternary D-type flip-flop. At this time, the output signal Q is equal to the input signal D. Both the input signal Q and the output signal D are ternary signals. Therefore, the ternary D-type flip-flop of this invention can directly process ternary signals. When used in large-scale digital integrated circuit systems, it can reduce the amount of redundant signal processing, thereby increasing the processing speed of large-scale digital integrated circuit systems, reducing the number of transistors used and the chip area, and reducing costs. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating the structural principle of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention.

[0007] Figure 2 The circuit diagram of the inverter of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown below;

[0008] Figure 3 The circuit diagram of the ternary AND gate of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown below.

[0009] Figure 4 The circuit diagram of the ternary OR gate of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown below.

[0010] Figure 5 The simulation waveform of the ternary AND gate of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown.

[0011] Figure 6 The simulation waveform diagram of the ternary OR gate of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown.

[0012] Figure 7 The above is a simulation waveform diagram of the three-valued D-type flip-flop based on multi-threshold CMOS of the present invention. Detailed Implementation

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0014] Example: Figure 1 As shown, a ternary D-type flip-flop based on multi-threshold CMOS includes an inverter T1, two ternary AND gates, and a ternary OR gate R1. The inverter T1 has an input terminal and an output terminal. The two ternary AND gates and the ternary OR gate R1 each have a first input terminal, a second input terminal, and an output terminal. The two ternary AND gates are referred to as the first ternary AND gate A1 and the second ternary AND gate A2, respectively. The input terminal of the inverter T1 and the first input terminal of the second ternary AND gate A2 are connected, and the connection terminal is a ternary D-type flip-flop. The clock terminal is used to receive the clock signal. The second input terminal of the second ternary AND gate A2 is the input terminal of the ternary D flip-flop. The output terminal of the inverter T1 is connected to the second input terminal of the first ternary AND gate A1. The first input terminal of the first ternary AND gate A1 is connected to the output terminal of the ternary OR gate R1, and its connection terminal is the output terminal of the ternary D flip-flop. The output terminal of the first ternary AND gate A1 is connected to the first input terminal of the ternary OR gate R1. The output terminal of the second ternary AND gate A2 is connected to the second input terminal of the ternary OR gate R1.

[0015] like Figure 2 As shown, inverter T1 includes a first MOS transistor Q1 and a second MOS transistor Q2. The first MOS transistor Q1 is a PMOS transistor, and the second MOS transistor Q2 is an NMOS transistor. The width-to-length ratio of the first MOS transistor Q1 is 355n / 60n, and the width-to-length ratio of the second MOS transistor Q2 is 120n / 60n. The source and substrate of the first MOS transistor Q1 are both connected to the power supply. The gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2 are connected, and their connection terminal is the input terminal of inverter T1. The drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected, and their connection terminal is the output terminal of inverter T1. The source and substrate of the second MOS transistor Q2 are both grounded.

[0016] like Figure 3As shown, each ternary AND gate includes a third MOSFET Q3, a fourth MOSFET Q4, a fifth MOSFET Q5, a sixth MOSFET Q6, a seventh MOSFET Q7, an eighth MOSFET Q8, a ninth MOSFET Q9, a tenth MOSFET Q10, an eleventh MOSFET Q11, a twelfth MOSFET Q12, a thirteenth MOSFET Q13, a fourteenth MOSFET Q14, a fifteenth MOSFET Q16, and a sixteenth MOSFET Q16. The third MOSFET Q3, fifth MOSFET Q5, seventh MOSFET Q7, eighth MOSFET Q8, tenth MOSFET Q10, and twelfth MOSFET Q12 are all PMOS transistors. The fourth MOSFET Q4, sixth MOSFET Q6, ninth MOSFET Q9, and eleventh MOSFET Q11 are PMOS transistors. 9. The eleventh MOSFET Q11, thirteenth MOSFET Q13, fourteenth MOSFET Q14, fifteenth MOSFET Q16, and sixteenth MOSFET Q16 are all NMOS transistors. The aspect ratio of the third MOSFET Q3 is 355n / 60n, the fourth MOSFET Q4 is 120n / 60n, the fifth MOSFET Q5 is 200n / 60n, the sixth MOSFET Q6 is 200n / 60n, the seventh MOSFET Q7 is 200n / 60n, the eighth MOSFET Q8 is 355n / 60n, the ninth MOSFET Q9 is 120n / 60n, and the tenth MOSFET Q10 is 200n / 60n. The aspect ratio of the eleventh MOSFET Q11 is 200n / 60n; the aspect ratio of the twelfth MOSFET Q12 is 355n / 60n; the aspect ratio of the thirteenth MOSFET Q13 is 120n / 60n; the aspect ratio of the fourteenth MOSFET Q14 is 200n / 60n; the aspect ratio of the fifteenth MOSFET Q15 is 200n / 60n; the aspect ratio of the sixteenth MOSFET Q16 is 200n / 60n; the source and substrate of the third MOSFET Q3; the source and substrate of the fifth MOSFET Q5; the substrate of the seventh MOSFET Q7; the source and substrate of the eighth MOSFET Q8; and the substrate of the tenth MOSFET Q10. The source and substrate of the twelfth MOSFET Q12 are both connected to the power supply. The gates of the third MOSFET Q3, the fourth MOSFET Q4, the fifth MOSFET Q5, the sixth MOSFET Q6, and the source of the sixteenth MOSFET Q16 are connected, and their connection terminals are the second input terminals of a ternary AND gate. The drains of the third MOSFET Q3, the fourth MOSFET Q4, and the sixth MOSFET Q6 are connected. The source, substrate, and substrate of the fourth MOSFET Q4 and the sixth MOSFET Q6 are all grounded. The drains of the fifth MOSFET Q5, the sixth MOSFET Q6, the gate of the seventh MOSFET Q7, and the gate of the fifteenth MOSFET Q16 are connected.The drains of the seventh MOSFET Q7, the fourteenth MOSFET Q14, and the fifteenth MOSFET Q16 are connected, and their connection terminals form the output of a ternary AND gate. The gates of the eighth MOSFET Q8, the ninth MOSFET Q9, the source of the seventh MOSFET Q7, the gate of the tenth MOSFET Q10, and the eleventh MOSFET Q11 are connected, and their connection terminals form the first input of a ternary AND gate. The drains of the eighth MOSFET Q8, the ninth MOSFET Q9, and the tenth MOSFET Q10 are connected. The source of the ninth MOSFET Q9, the substrate of the ninth MOSFET Q9, the source of the eleventh MOSFET, the substrate of the eleventh MOSFET Q11, and the thirteenth MOSFET Q16 are connected. The source of MOSFET Q13, the substrate of MOSFET Q13, the source of MOSFET Q14, the substrate of MOSFET Q14, the substrate of MOSFET Q16, and the substrate of MOSFET Q16 are all grounded. The drain of MOSFET Q10, the drain of MOSFET Q11, the gate of MOSFET Q12, the gate of MOSFET Q13, and the gate of MOSFET Q14 are connected. The drain of MOSFET Q12, the drain of MOSFET Q13, and the gate of MOSFET Q16 are connected. The source of MOSFET Q15 and the drain of MOSFET Q16 are connected.

[0017] like Figure 4As shown, the ternary OR gate R1 includes the seventeenth MOSFET Q17, the eighteenth MOSFET Q18, the nineteenth MOSFET Q19, the twentieth MOSFET Q20, the twenty-first MOSFET Q21, the twenty-second MOSFET Q22, the twenty-third MOSFET Q23, the twenty-fourth MOSFET Q24, the twenty-fifth MOSFET Q25, the twenty-sixth MOSFET Q26, the twenty-seventh MOSFET Q27, the twenty-eighth MOSFET Q28, the twenty-ninth MOSFET Q29, and the thirtieth MOSFET Q30. The seventeenth MOSFET Q17, the nineteenth MOSFET Q19, the twenty-first MOSFET Q21, the twenty-third MOSFET Q23, the twenty-fourth MOSFET Q24, and the twenty-fifth MOSFET Q25 are also mentioned. S-MOSFET Q25, the 27th MOSFET Q27, and the 29th MOSFET Q29 are all PMOS transistors. The 18th MOSFET Q18, the 20th MOSFET Q20, the 22nd MOSFET Q22, the 26th MOSFET Q26, the 28th MOSFET Q28, and the 30th MOSFET Q30 are all NMOS transistors. The aspect ratio of the 17th MOSFET Q17 is 355n / 60n, the 18th MOSFET Q18 is 120n / 60n, the 19th MOSFET Q19 is 200n / 60n, the 20th MOSFET Q20 is 200n / 60n, the 21st MOSFET Q21 is 355n / 60n, and the 22nd MOSFET Q26... The aspect ratio of MOSFET Q22 is 120n / 60n; the aspect ratio of MOSFET Q23 is 200n / 60n; the aspect ratio of MOSFET Q24 is 200n / 60n; the aspect ratio of MOSFET Q25 is 355n / 60n; the aspect ratio of MOSFET Q26 is 120n / 60n; the aspect ratio of MOSFET Q27 is 200n / 60n; the aspect ratio of MOSFET Q28 is 200n / 60n; the aspect ratio of MOSFET Q29 is 200n / 60n; the aspect ratio of MOSFET Q30 is 200n / 60n; the source of MOSFET Q17 and the MOSFET Q28 are also mentioned. The substrates of S-MOSFET Q17, Q19, Q21, Q23, Q24, Q29, Q25, Q26, and Q27 are all connected to a power supply. The gates of Q17, Q18, Q19, and Q30 are connected, with their connection terminals serving as the first input of a ternary OR gate R1.The drain of the seventeenth MOSFET Q17, the drain of the eighteenth MOSFET Q18, the gate of the nineteenth MOSFET Q19, and the gate of the twentieth MOSFET Q20 are connected. The source, substrate, source, substrate, and substrate of the eighteenth MOSFET Q18, the twentieth MOSFET Q20, and the source and substrate of the twenty-second MOSFET Q22 are all grounded. The drain of the nineteenth MOSFET Q19, the drain of the twentieth MOSFET Q20, the gate of the twenty-first MOSFET Q21, the gate of the twenty-second MOSFET Q22, and the gate of the twenty-fourth MOSFET Q24 are connected. The drain of the twenty-first MOSFET Q21, the drain of the twenty-second MOSFET Q22, and the gate of the twenty-third MOSFET Q23 are connected. The drain of the twenty-third MOSFET Q23, the drain of the twenty-ninth MOSFET Q29, and the drain of the thirtieth MOSFET Q30 are connected, and their connection terminals are three-way junctions. The output of the OR gate R1 is connected to the source of the 24th MOSFET Q24, the gate of the 25th MOSFET Q25, the gate of the 26th MOSFET Q26, the gate of the 27th MOSFET Q27, and the gate of the 28th MOSFET Q28, and this connection is the second input of the OR gate R1. The drain of the 24th MOSFET Q24 is connected to the source of the 29th MOSFET Q29. The drains of the 25th MOSFET Q25, the drains of the 26th MOSFET Q26, and the source of the 27th MOSFET Q27 are connected. The source, substrate, source, substrate, and substrate of the 28th MOSFET Q28, and the substrate of the 30th MOSFET Q30 are all grounded. The drains of the 27th MOSFET Q27, the drains of the 28th MOSFET Q28, the gates of the 29th MOSFET Q29, and the gate of the 30th MOSFET Q30 are connected.

[0018] When the clock input of the ternary D-type flip-flop of the present invention is connected to a clock signal CP and the input input is connected to an input signal D, when the clock signal CP=0, the output of the second ternary AND gate A2 outputs logic 0, the output of the first ternary AND gate A1 outputs the signal previously output by the output of the ternary D-type flip-flop, and the logic 0 output by the second ternary AND gate A2 and the signal output by the first ternary AND gate A1 are passed through a ternary OR gate R1 to output signal Q at the output of the ternary D-type flip-flop; when the clock signal CP=2, the output of the second ternary AND gate A2 outputs the input signal D, the output of the first ternary AND gate A1 outputs logic 0, and the input signal D and logic 0 are passed through a ternary OR gate R1 to output signal Q at the output of the ternary D-type flip-flop, at which time the output signal Q is equal to the input signal D; the simulation waveform diagram of the ternary AND gate of the ternary D-type flip-flop based on multi-threshold CMOS of the present invention is shown below. Figure 5 As shown, Figure 5In the middle, the topmost waveform represents the input signal connected to the first input terminal of the ternary AND gate. A The second waveform is the input signal connected to the second input terminal of the ternary AND gate. B The bottom waveform is the output signal from the output terminal of the AND gate. OUT .analyze Figure 5 It can be seen that the output signal of the ternary AND gate OUT Input signal A and input signal B For signals with smaller values, the ternary AND gate produces the correct result and has the correct logical function. The simulation waveform of the ternary OR gate based on the multi-threshold CMOS ternary D-type flip-flop of this invention is shown below. Figure 6 As shown, Figure 6 In the middle, the topmost waveform is the input signal connected to the first input terminal of the ternary OR gate. A The second waveform is the input signal connected to the second input terminal of the ternary OR gate. B The bottom waveform is the output signal from the output terminal of the ternary OR gate. OUT .analyze Figure 6 It can be seen that the output signal of the ternary OR gate OUT Input signal A and input signal B For signals with large values, the ternary OR gate outputs the correct result and performs the correct logical function. The simulation waveform of the ternary D-type flip-flop based on multi-threshold CMOS of this invention is shown below. Figure 7 As shown, Figure 7 In the diagram, waveform D represents the input signal connected to the input terminal of the ternary D flip-flop, CP represents the clock signal connected to the clock terminal of the ternary D flip-flop, and Q represents the output signal output from the output terminal of the ternary D flip-flop. Analysis... Figure 7 As can be seen, the waveforms of the input signal D and the output signal Q are consistent. The input and output signals of the three-valued D-type flip-flop based on multi-threshold CMOS of the present invention are both three-valued signals, realizing the function of temporary storage and having correct logic.

Claims

1. A multi-threshold CMOS based ternary D flip-flop, characterized by The application relates to a three-value D-type flip-flop, which comprises an inverter, two three-value AND gates and a three-value OR gate, the inverter has an input end and an output end, the two three-value AND gates and the three-value OR gate each have a first input end, a second input end and an output end, the two three-value AND gates are respectively called a first three-value AND gate and a second three-value AND gate, the input end of the inverter and the first input end of the second three-value AND gate are connected and the connection end is the clock end of the three-value D-type flip-flop for inputting a clock signal, the second input end of the second three-value AND gate is the input end of the three-value D-type flip-flop, the output end of the inverter and the second input end of the first three-value AND gate are connected, the first input end of the first three-value AND gate and the output end of the three-value OR gate are connected and the connection end is the output end of the three-value D-type flip-flop, the output end of the first three-value AND gate and the first input end of the three-value OR gate are connected, and the output end of the second three-value AND gate and the second input end of the three-value OR gate are connected. The inverter comprises a first MOS transistor and a second MOS transistor, the first MOS transistor is a PMOS transistor, the second MOS transistor is an NMOS transistor, the width-length ratio of the first MOS transistor is 355n / 60n, the width-length ratio of the second MOS transistor is 120n / 60n, the source and the substrate of the first MOS transistor are connected to a power supply, the gate of the first MOS transistor and the gate of the second MOS transistor are connected and the connection end is the input end of the inverter, the drain of the first MOS transistor and the drain of the second MOS transistor are connected and the connection end is the output end of the inverter, and the source and the substrate of the second MOS transistor are connected to the ground. Each of the three-value AND gates comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor, the third MOS transistor, the fifth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the tenth MOS transistor and the twelfth MOS transistor are PMOS transistors, the fourth MOS transistor, the sixth MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor and the sixteenth MOS transistor are NMOS transistors, the width-length ratio of the third MOS transistor is 355n / 60n, the width-length ratio of the fourth MOS transistor is 120n / 60n, the width-length ratio of the fifth MOS transistor is 200n / 60n, the width-length ratio of the sixth MOS transistor is 200n / 60n, the width-length ratio of the seventh MOS transistor is 200n / 60n, the width-length ratio of the eighth MOS transistor is 355n / 60n, the width-length ratio of the ninth MOS transistor is 120n / 60n, the width-length ratio of the tenth MOS transistor is 200n / 60n, the width-length ratio of the eleventh MOS transistor is 200n / 60n, the width-length ratio of the twelfth MOS transistor is 355n / 60n, the width-length ratio of the thirteenth MOS transistor is 120n / 60n, the width-length ratio of the fourteenth MOS transistor is 200n / 60n, the width-length ratio of the fifteenth MOS transistor is 200n / 60n, the width-length ratio of the sixteenth MOS transistor is 200n / 60n, the source of the third MOS transistor, the substrate of the third MOS transistor, the source of the fifth MOS transistor, the substrate of the fifth MOS transistor, the substrate of the seventh MOS transistor, the source of the eighth MOS transistor, the substrate of the eighth MOS transistor, the substrate of the tenth MOS transistor, the source of the twelfth MOS transistor and the substrate of the twelfth MOS transistor are connected to a power supply, the gate of the third MOS transistor, the gate of the fourth MOS transistor, the gate of the fifth MOS transistor, the gate of the sixth MOS transistor and the source of the sixteenth MOS transistor are connected and the connection end is the second input end of the three-value AND gate, the drain of the third MOS transistor, the drain of the fourth MOS transistor and the source of the sixth MOS transistor are connected, the source of the fourth MOS transistor, the substrate of the fourth MOS transistor and the substrate of the sixth MOS transistor are grounded, the drain of the fifth MOS transistor, the drain of the sixth MOS transistor, the gate of the seventh MOS transistor and the gate of the fifteenth MOS transistor are connected,The drain of the seventh MOS, the drain of the fourteenth MOS and the drain of the fifteenth MOS are connected and the connection end is the output end of the three-value AND gate, the gate of the eighth MOS, the gate of the ninth MOS, the source of the seventh MOS, the gate of the tenth MOS and the gate of the eleventh MOS are connected and the connection end is the first input end of the three-value AND gate, the drain of the eighth MOS, the drain of the ninth MOS and the source of the tenth MOS are connected, the source of the ninth MOS, the substrate of the ninth MOS, the source of the eleventh MOS, the substrate of the eleventh MOS, the source of the thirteenth MOS, the substrate of the thirteenth MOS, the source of the fourteenth MOS, the substrate of the fourteenth MOS, the substrate of the fifteenth MOS and the substrate of the sixteenth MOS are grounded, the drain of the tenth MOS, the drain of the eleventh MOS, the gate of the twelfth MOS, the gate of the thirteenth MOS and the gate of the fourteenth MOS are connected, the drain of the twelfth MOS, the drain of the thirteenth MOS and the gate of the sixteenth MOS are connected, the source of the fifteenth MOS and the drain of the sixteenth MOS are connected. The ternary OR gate comprises a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, a twenty-ninth MOS transistor and a thirtieth MOS transistor, the seventeenth MOS transistor, the nineteenth MOS transistor, the twenty-first MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, the twenty-fifth MOS transistor, the twenty-seventh MOS transistor and the twenty-ninth MOS transistor are PMOS transistors, the eighteenth MOS transistor, the twentieth MOS transistor, the twenty-second MOS transistor, the twenty-sixth MOS transistor, the twenty-eighth MOS transistor and the thirtieth MOS transistor are NMOS transistors, the width-length ratio of the seventeenth MOS transistor is 355n / 60n, the width-length ratio of the eighteenth MOS transistor is 120n / 60n, the width-length ratio of the nineteenth MOS transistor is 200n / 60n, the width-length ratio of the twentieth MOS transistor is 200n / 60n, the width-length ratio of the twenty-first MOS transistor is 355n / 60n, the width-length ratio of the twenty-second MOS transistor is 120n / 60n, the width-length ratio of the twenty-third MOS transistor is 200n / 60n, the width-length ratio of the twenty-fourth MOS transistor is 200n / 60n, the width-length ratio of the twenty-fifth MOS transistor is 355n / 60n, the width-length ratio of the twenty-sixth MOS transistor is 120n / 60n, the width-length ratio of the twenty-seventh MOS transistor is 200n / 60n, the width-length ratio of the twenty-eighth MOS transistor is 200n / 60n, the width-length ratio of the twenty-ninth MOS transistor is 200n / 60n, the width-length ratio of the thirtieth MOS transistor is 200n / 60n, the source of the seventeenth MOS transistor, the substrate of the seventeenth MOS transistor, the substrate of the nineteenth MOS transistor, the source of the twenty-first MOS transistor, the substrate of the twenty-first MOS transistor, the source of the twenty-third MOS transistor, the substrate of the twenty-third MOS transistor, the substrate of the twenty-fourth MOS transistor, the substrate of the twenty-ninth MOS transistor, the source of the twenty-fifth MOS transistor, the substrate of the twenty-fifth MOS transistor and the substrate of the twenty-seventh MOS transistor are connected with a power supply, the gate of the seventeenth MOS transistor, the gate of the eighteenth MOS transistor, the source of the nineteenth MOS transistor and the source of the thirtieth MOS transistor are connected and the connection end is the first input end of the ternary OR gate, the drain of the seventeenth MOS transistor, the drain of the eighteenth MOS transistor, the gate of the nineteenth MOS transistor and the gate of the twentieth MOS transistor are connected,The eighteenth MOS transistor source, the eighteenth MOS transistor substrate, the twentieth MOS transistor source, the twentieth MOS transistor substrate, the twenty-second MOS transistor source and the twenty-second MOS transistor substrate are grounded, the nineteenth MOS transistor drain, the twentieth MOS transistor drain, the twenty-first MOS transistor gate, the twenty-second MOS transistor gate and the twenty-fourth MOS transistor gate are connected, the twenty-first MOS transistor drain, the twenty-second MOS transistor drain and the twenty-third MOS transistor gate are connected, the twenty-third MOS transistor drain, the twenty-ninth MOS transistor drain and the thirtieth MOS transistor drain are connected and the connected end is the three-value or gate output end, the twenty-fourth MOS transistor source, the twenty-fifth MOS transistor gate, the twenty-sixth MOS transistor gate, the twenty-seventh MOS transistor gate and the twenty-eighth MOS transistor gate are connected and the connected end is the second three-value or gate input end, the twenty-fourth MOS transistor drain and the twenty-ninth MOS transistor source are connected, the twenty-fifth MOS transistor drain, the twenty-sixth MOS transistor drain and the twenty-seventh MOS transistor source are connected, the twenty-sixth MOS transistor source, the twenty-sixth MOS transistor substrate, the twenty-eighth MOS transistor source, the twenty-eighth MOS transistor substrate and the thirtieth MOS transistor substrate are grounded, the twenty-seventh MOS transistor drain, the twenty-eighth MOS transistor drain, the twenty-ninth MOS transistor gate and the thirtieth MOS transistor gate are connected.

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