Current steering digital-to-analog converter with analog domain control multi-mode and design method thereof

Abstract

The application provides a current steering digital-to-analog converter of analog domain control multi-working mode and a design method thereof, two levels of switches, namely, a zero-return control switch module and a mixing control switch module, are additionally arranged between a current switch module and a current-voltage conversion module, the current steering digital-to-analog converter has three working modes, namely, a normal mode, a zero-return mode and a mixing mode, through the adjustment and control of the zero-return control switch module and the mixing control switch module, and the output bandwidth of the current steering digital-to-analog converter is expanded based on the free switching selection of the three working modes; meanwhile, compared with the conventional structure improvement of each current switch unit in the current switch module, the current steering digital-to-analog converter does not need to increase the number of switch tubes in each current switch unit, only two control switch modules are added, the number of switch tubes can be effectively reduced, the number of corresponding switch control signals is reduced, the structure of the current steering digital-to-analog converter is simplified and the energy consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of digital-to-analog converter technology, and in particular to a current-controlled digital-to-analog converter with multiple operating modes in analog domain control and its design method. Background Technology

[0002] The analog output signal power of a digital-to-analog converter (DAC) is limited by the sampling clock frequency. Theoretically, the output spectrum envelope of a DAC is a sin(x) / x curve with multiple blades. Therefore, the output spectrum of a DAC has a high attenuation near the clock frequency.

[0003] Therefore, to address the problem that digital-to-analog converters (DACs) struggle to obtain sufficiently strong output fundamental signal power within the sampling clock frequency range under conventional conditions, previous industry designs (see US Patent 20080224908) improved the traditional two-transistor differential pair switch of a current-controlled DAC into a four-transistor switch. Each switch is controlled by a control signal, resulting in four control signals. These four control signals originate from a logical operation between the input data logic value and the clock signal logic value. The result and purpose of this operation is to ensure that the signal on the current switch continuously and complementaryly changes regardless of data changes, and the change pattern does not change with the data pattern. Depending on the different control signals for the DAC's operating mode, the logical operation between the input data logic value and the clock signal logic value differs. Therefore, the DAC can select between three operating modes: normal, mixing, and return-to-zero, based on the different control signals. This allows users to choose different operating modes for the DAC according to the required fundamental frequency range.

[0004] However, the four-transistor switch design doubles the number of switching transistors in the digital-to-analog converter, doubles the control signals for the switches, increases the parasitic capacitance at the analog output of the digital-to-analog converter, and increases the chip layout area, etc., which makes the timing design of the switch control signals more tight, thus affecting the dynamic performance indicators of the digital-to-analog converter. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multi-mode design scheme for a digital-to-analog converter. By adding a zero-reset control switch module and a mixing control switch module to the differential output terminal of the current switching module of the current-steering digital-to-analog converter, the current-steering digital-to-analog converter can have three operating modes: normal mode, zero-reset mode, and mixing mode, and the output bandwidth of the current-steering digital-to-analog converter can be expanded.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A current-controlled digital-to-analog converter with multiple operating modes in analog domain control includes:

[0008] A current switching module includes multiple current switching units, wherein the differential output terminals of the multiple current switching units are connected in parallel;

[0009] The zero-reset control switch module includes a current transmission branch and a current zero-reset branch, wherein the input terminal of the current transmission branch and the input terminal of the current zero-reset branch are respectively connected to the output terminal of the current switch module.

[0010] A mixing control switch module includes a first mixing differential branch and a second mixing differential branch. The input terminal of the first mixing differential branch is connected to the negative differential output terminal of the current transmission branch, and the input terminal of the second mixing differential branch is connected to the positive differential output terminal of the current transmission branch.

[0011] The current-to-voltage conversion module includes a first differential conversion branch and a second differential conversion branch. The input terminal of the first differential conversion branch is connected to the first output terminal of the first differential mixing branch and the first output terminal of the second differential mixing branch, respectively. The input terminal of the second differential conversion branch is connected to the second output terminal of the first differential mixing branch and the second output terminal of the second differential mixing branch, respectively. The module converts the transmitted current into voltage and performs differential output.

[0012] The data synchronization latch module sequentially performs latch reception, decoding, synchronous latching and buffer output processing on the input digital data to obtain and output current control signals to each of the current switch units, and controls the current flow direction in the current switch units through the current control signals.

[0013] The mode control module generates and outputs a clock signal to the data synchronization latch module, generates and outputs a zero-reset control signal to the zero-reset control switch module, and generates and outputs a mixing control signal to the mixing control switch module. The zero-reset control signal controls the current flow in the zero-reset control switch module, and the mixing control signal controls the current flow in the mixing control switch module.

[0014] The adjustment and control based on the zero-reset control signal and the mixing control signal enable the current-steering digital-to-analog converter to operate in three modes: normal mode, zero-reset mode, and mixing mode.

[0015] Optionally, the current switching unit includes a first NPN transistor, a second NPN transistor, and a tail current source. The emitter of the first NPN transistor is grounded after being connected in series with the tail current source. The base of the first NPN transistor is connected to one of the current control signals. The emitter of the second NPN transistor is connected to the emitter of the first NPN transistor. The base of the second NPN transistor is connected to another current control signal. The collector of the first NPN transistor is the positive terminal of the differential output of the current switching unit, and the collector of the second NPN transistor is the negative terminal of the differential output of the current switching unit.

[0016] Optionally, the zero-reset control switch module includes a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a first current source, a second current source, a first resistor, a second resistor, a third resistor, and a fourth resistor. The zero-reset control signal includes a first zero-reset control signal and a second zero-reset control signal. The emitter of the third NPN transistor is grounded after being connected in series with the first current source. The emitter of the third NPN transistor is also connected to the collector of the first NPN transistor. The base of the third NPN transistor is connected to the first zero-reset control signal. The collector of the fourth NPN transistor is connected to the emitter of the third NPN transistor via the first resistor in series. The base of the fourth NPN transistor is connected to the second return-to-zero control signal. The collector of the fourth NPN transistor is connected to the operating voltage via the second resistor in series. The emitter of the fifth NPN transistor is grounded via the second current source in series. The emitter of the fifth NPN transistor is also connected to the collector of the second NPN transistor. The base of the fifth NPN transistor is connected to the second return-to-zero control signal. The electrode is connected to the operating voltage via the third resistor in series. The emitter of the sixth NPN transistor is connected to the emitter of the fifth NPN transistor. The base of the sixth NPN transistor is connected to the first zero-return control signal. The collector of the sixth NPN transistor is output via the fourth resistor in series. The third NPN transistor, the first resistor, the sixth NPN transistor, and the fourth resistor constitute the current transmission branch of the differential structure. The fourth NPN transistor, the second resistor, the fifth NPN transistor, and the third resistor constitute the current transmission branch of the differential structure. The current-to-zero branch has the emitter of the third NPN transistor as the positive differential input terminal, the emitter of the sixth NPN transistor as the negative differential input terminal, the end of the first resistor furthest from the third NPN transistor as the negative differential output terminal, the end of the fourth resistor furthest from the sixth NPN transistor as the positive differential output terminal, the emitter of the fourth NPN transistor as the positive differential input terminal, and the emitter of the fifth NPN transistor as the negative differential input terminal.

[0017] Optionally, the mixing control switch module includes a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, and a tenth NPN transistor. The mixing control signal includes a first mixing control signal and a second mixing control signal. The emitter of the seventh NPN transistor is connected to the end of the first resistor away from the third NPN transistor, and the base of the seventh NPN transistor is connected to the first mixing control signal. The emitter of the eighth NPN transistor is connected to the emitter of the seventh NPN transistor, and the base of the eighth NPN transistor is connected to the second mixing control signal. The emitter of the ninth NPN transistor is connected to the end of the fourth resistor away from the sixth NPN transistor, and the base of the ninth NPN transistor is connected to the second mixing control signal. The emitter of the tenth NPN transistor is connected to the emitter of the ninth NPN transistor. The emitter of the tenth NPN transistor is connected to the base of the first mixing control signal. The seventh and eighth NPN transistors constitute the first mixing difference branch. The emitter of the seventh NPN transistor is the input terminal of the first mixing difference branch, the collector of the seventh NPN transistor is the first output terminal of the first mixing difference branch, and the collector of the eighth NPN transistor is the second output terminal of the first mixing difference branch. The ninth and tenth NPN transistors constitute the second mixing difference branch. The emitter of the ninth NPN transistor is the input terminal of the second mixing difference branch, the collector of the ninth NPN transistor is the first output terminal of the second mixing difference branch, and the collector of the tenth NPN transistor is the second output terminal of the second mixing difference branch.

[0018] Optionally, the current-to-voltage conversion module includes a first load resistor and a second load resistor. One end of the first load resistor is connected to the collector of the seventh NPN transistor and the collector of the ninth NPN transistor, respectively, and the other end of the first load resistor is connected to the operating voltage. One end of the second load resistor is connected to the collector of the eighth NPN transistor and the collector of the tenth NPN transistor, respectively, and the other end of the second load resistor is connected to the operating voltage. The first load resistor constitutes the first differential conversion branch, with the end of the first load resistor connected to the collector of the seventh NPN transistor serving as the input terminal and the end of the first load resistor connected to the collector of the seventh NPN transistor serving as the output terminal of the first differential conversion branch. The second load resistor constitutes the second differential conversion branch, with the end of the second load resistor connected to the collector of the eighth NPN transistor serving as the input terminal and the end of the second load resistor connected to the collector of the eighth NPN transistor serving as the output terminal of the second differential conversion branch.

[0019] Optionally, the first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor, the fifth NPN transistor, the sixth NPN transistor, the seventh NPN transistor, the eighth NPN transistor, the ninth NPN transistor, and the tenth NPN transistor are all heterojunction NPN transistors.

[0020] Optionally, the data synchronization latch module includes a pre-decoding data latch unit, a decoding unit, a post-decoding synchronization latch unit, and a data buffer output unit. The data input terminal of the pre-decoding data latch unit is connected to the input digit, the clock input terminal of the pre-decoding data latch unit is connected to the first clock signal, the pre-decoding data latch unit performs latch reception processing on the input digit, the data output terminal of the pre-decoding data latch unit is connected to the data input terminal of the decoding unit, the decoding unit performs decoding processing on the input digit, the data output terminal of the decoding unit is connected to the data input terminal of the post-decoding synchronization latch unit, the clock input terminal of the post-decoding synchronization latch unit is connected to the second clock signal and the third clock signal respectively, the data output terminal of the post-decoding synchronization latch unit is connected to the data input terminal of the data buffer output unit, and the data output terminal of the data buffer output unit outputs the current control signal.

[0021] Optionally, the post-decoding synchronization latch unit includes a master-slave latch structure.

[0022] Optionally, the mode control module includes a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a first double-pole double-throw switch, and a second double-pole double-throw switch. The differential input terminal of the first buffer is connected to an external differential clock signal, and the differential output terminal of the first buffer outputs a first-path clock signal. The differential input terminal of the second buffer is connected to the differential output terminal of the first buffer, and the differential input terminal of the third buffer is connected to the differential output terminal of the first buffer. The differential input terminals of the second and third buffers are connected in opposite phases, and the differential output terminal of the second buffer outputs a second-path clock signal. The differential output of the three buffers outputs the third clock signal. The differential input of the fourth buffer is connected to the differential output of the second buffer. The differential output of the fourth buffer is connected to the second differential input of the first double-pole double-throw switch. The first differential input of the first double-pole double-throw switch is connected to the first DC differential level signal. The differential output of the first double-pole double-throw switch outputs the zero-return control signal. The differential output of the fifth buffer is connected to the second differential input of the second double-pole double-throw switch. The first differential input of the second double-pole double-throw switch is connected to the second DC differential level signal. The differential output of the second double-pole double-throw switch outputs the mixing control signal.

[0023] A design method for a current-controlled digital-to-analog converter with multiple operating modes in analog domain control is disclosed. A zero-reset control switch module and a mixing control switch module are added to the differential output terminal of the current switching module of the current-controlled digital-to-analog converter. Through the adjustment and control of the zero-reset control switch module and the mixing control switch module, the current-controlled digital-to-analog converter can have three operating modes: normal mode, zero-reset mode, and mixing mode, and the output bandwidth of the current-controlled digital-to-analog converter is expanded.

[0024] As described above, the analog domain control multi-mode current-controlled digital-to-analog converter and its design method provided by the present invention have at least the following beneficial effects:

[0025] Two levels of switches, a zero-reset control switch module and a mixing control switch module, are added between the current switching module and the current-voltage conversion module. Through the adjustment and control of the zero-reset control switch module and the mixing control switch module, the current-steering digital-to-analog converter has three operating modes: normal mode, zero-reset mode, and mixing mode. Based on the free switching selection of these three operating modes, the output bandwidth of the current-steering digital-to-analog converter is expanded. At the same time, compared with the conventional structural improvement of each current switching unit in the current switching module, it does not require increasing the number of switching transistors in each current switching unit. It only adds two control switch modules as a whole, which can effectively reduce the number of switching transistors and the number of corresponding switch control signals, simplifying the structure of the current-steering digital-to-analog converter and reducing energy consumption. Attached Figure Description

[0026] Figure 1 The diagram shows the output spectrum envelope of a current-driven digital-to-analog converter in the prior art under three operating modes.

[0027] Figure 2 The diagram shown is a circuit diagram of the current-driven digital-to-analog converter in this invention.

[0028] Figure 3 Displayed as Figure 2 Circuit diagram of the medium mode control module.

[0029] Figure 4 Displayed as Figure 2 Circuit diagram of the data synchronization latch module.

[0030] Figure 5 The diagram shows the analog output time-domain waveforms of the current-steering digital-to-analog converter in the present invention under three operating modes. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0033] As described in the background section, the inventors discovered that the analog output signal power of a digital-to-analog converter (DAC) is limited by the sampling clock frequency. Theoretically, the output spectrum envelope of the DAC is a sin(x) / x curve with multiple blades, such as... Figure 1 As shown, the output spectrum of the digital-to-analog converter therefore exhibits high attenuation near the clock frequency.

[0034] Therefore, in conventional mode, it is difficult for digital-to-analog converters (DACs) to obtain sufficiently strong output fundamental signal power in the vicinity of the sampling clock frequency. Previous industry designs (see US Patent 20080224908) improved the traditional two-transistor differential pair switch of a current-controlled DAC to a four-transistor switch, with each switch controlled by a control signal, for a total of four control signals. These four control signals originate from a certain logical operation between the input data logic value and the clock signal logic value. The result and purpose of this operation is to ensure that, regardless of data changes, the signal on the current switch continuously and complementaryly changes, and the change pattern does not change with the data pattern. Depending on the different control signals for the DAC's operating mode, the logical operation between the input data logic value and the clock signal logic value differs. Therefore, the DAC can select to operate in three modes: conventional, mixing, and return-to-zero. The output spectrum sin(x) / x envelope curves of the DAC in these three modes are shown in [reference needed]. Figure 1 As shown, users can select different operating modes of the digital-to-analog converter according to the required fundamental frequency range.

[0035] However, the four-transistor switch design doubles the number of switching transistors in the digital-to-analog converter, doubles the control signals for the switches, increases the parasitic capacitance at the analog output of the digital-to-analog converter, and increases the chip layout area, etc., which makes the timing design of the switch control signals more tight, thus affecting the dynamic performance indicators of the digital-to-analog converter.

[0036] Therefore, this invention proposes a multi-mode design scheme for a digital-to-analog converter: a zero-reset control switch module and a mixing control switch module are added to the differential output terminal of the current switching module of the current-steering digital-to-analog converter. Through the adjustment and control of the zero-reset control switch module and the mixing control switch module, the current-steering digital-to-analog converter has three working modes: normal mode, zero-reset mode and mixing mode, so as to expand the working modes of the current-steering digital-to-analog converter and expand the output bandwidth of the current-steering digital-to-analog converter.

[0037] First, such as Figure 2 As shown, the present invention provides a current-controlled digital-to-analog converter with multiple operating modes in analog domain control, comprising:

[0038] The current switching module includes multiple current switching units, and the differential output terminals of the multiple current switching units are connected in parallel;

[0039] The zero-reset control switch module includes a current transmission branch and a current zero-reset branch. The input terminals of the current transmission branch and the current zero-reset branch are respectively connected to the output terminals of the current switch module.

[0040] The mixing control switch module includes a first mixing differential branch and a second mixing differential branch. The input terminal of the first mixing differential branch is connected to the negative terminal of the differential output of the current transmission branch, and the input terminal of the second mixing differential branch is connected to the positive terminal of the differential output of the current transmission branch.

[0041] The current-to-voltage conversion module includes a first differential conversion branch and a second differential conversion branch. The input terminal of the first differential conversion branch is connected to the first output terminal of the first differential mixing branch and the first output terminal of the second differential mixing branch, respectively. The input terminal of the second differential conversion branch is connected to the second output terminal of the first differential mixing branch and the second output terminal of the second differential mixing branch, respectively. The module converts the transmitted current into voltage and performs differential output.

[0042] The data synchronization latch module sequentially performs latch reception, decoding, synchronous latching and buffer output processing on the input digital data, and obtains and outputs current control signals to each current switching unit, thereby controlling the current flow in the current switching unit through the current control signals.

[0043] The mode control module generates and outputs clock signals CLKN_1, CLKP_1, CLKN_2, CLKP_2, CLKN_3, and CLKP_3 to the data synchronization latch module. It also generates and outputs zero-reset control signals S1 and S1N to the zero-reset control switch module and generates and outputs mixing control signals S2 and S2N to the mixing control switch module. The zero-reset control signals S1 and S1N control the current flow in the zero-reset control switch module, and the mixing control signals S2 and S2N control the current flow in the mixing control switch module.

[0044] Among them, the adjustment control based on the zero-reset control signals S1, S1N and the mixing control signals S2, S2N enables the current-rudder digital-to-analog converter to operate in three modes: normal mode, zero-reset mode and mixing mode.

[0045] In detail, such as Figure 2 As shown, the current switching module comprises n current switching units. The entire current switching module includes 2n input terminals and 2 output terminals. The analog differential output terminals of all current switching units are connected in parallel at nodes AP and AN, respectively, and are also connected to the two analog input terminals of the zero-return control switch module. Each current switching unit has 2 digital signal input terminals and 2 analog output terminals. The specific number of current switching units is determined based on the number of input data bits of the current steering digital-to-analog converter and the specific segmented decoding of the current steering digital-to-analog converter. Here, n is a positive integer.

[0046] More in detail, such as Figure 2As shown, the current switching unit includes a first NPN transistor Q1, a second NPN transistor Q2, and a tail current source I0. The emitter of the first NPN transistor Q1 is grounded after being connected in series with the tail current source I0. The base of the first NPN transistor Q1 is connected to a current control signal D1P. The emitter of the second NPN transistor Q2 is connected to the emitter of the first NPN transistor Q1. The base of the second NPN transistor Q2 is connected to another current control signal D1N. The base of the first NPN transistor Q1 is a digital signal input terminal, and the base of the second NPN transistor Q2 is another digital signal input terminal. They are respectively connected to differential complementary current control signals D1P / D1N. The collector of the first NPN transistor Q1 is the positive terminal of the differential output of the current switching unit, and the collector of the second NPN transistor Q2 is the negative terminal of the differential output of the current switching unit.

[0047] In this unit, the two digital signal input terminals of the first current switching unit are connected to differential complementary current control signals D1P / D1N, and so on, ..., the two digital signal input terminals of the nth current switching unit are connected to differential complementary current control signals DnP / DnN.

[0048] In detail, such as Figure 2 As shown, the zero-reset control switch module includes a third NPN transistor Q3, a fourth NPN transistor Q4, a fifth NPN transistor Q5, a sixth NPN transistor Q6, a first current source I1, a second current source I2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The zero-reset control signals include a first zero-reset control signal S1 and a second zero-reset control signal S1N. The emitter of the third NPN transistor Q3 is grounded after being connected in series with the first current source I1. The emitter of transistor Q3 is also connected to the collector of the first NPN transistor Q1. The base of the third NPN transistor Q3 is connected to the first zero-reset control signal S1. The collector of the third NPN transistor Q3 is output externally through the first resistor R1 connected in series. The emitter of the fourth NPN transistor Q4 is connected to the emitter of the third NPN transistor Q3. The base of the fourth NPN transistor Q4 is connected to the second zero-reset control signal S1N. The collector of the fourth NPN transistor Q4 is connected to the operating voltage V through the second resistor R2 connected in series. CC The emitter of the fifth NPN transistor Q5 is grounded after being connected in series with the second current source I2. The emitter of the fifth NPN transistor Q5 is also connected to the collector of the second NPN transistor Q2. The base of the fifth NPN transistor Q5 is connected to the second zero-return control signal S1N. The collector of the fifth NPN transistor Q5 is connected to the operating voltage V after being connected in series with the third resistor R3. CCThe emitter of the sixth NPN transistor Q6 is connected to the emitter of the fifth NPN transistor Q5, the base of the sixth NPN transistor Q6 is connected to the first zero-reset control signal S1, and the collector of the sixth NPN transistor Q6 is output to the outside through the fourth resistor R4 connected in series.

[0049] In this circuit, the third NPN transistor Q3, the first resistor R1, the sixth NPN transistor Q6, and the fourth resistor R4 form the current transmission branch of the differential structure. The fourth NPN transistor Q4, the second resistor R2, the fifth NPN transistor Q5, and the third resistor R3 form the current zeroing branch of the differential structure. The emitter of the third NPN transistor Q3 is the positive differential input terminal of the current transmission branch, and the emitter of the sixth NPN transistor Q6 is the negative differential input terminal of the current transmission branch. The end of the first resistor R1 furthest from the third NPN transistor Q3 is the negative differential output terminal of the current transmission branch. The end of the fourth resistor R4 furthest from the sixth NPN transistor Q6 is the positive differential output terminal of the current transmission branch. The emitter of the fourth NPN transistor Q4 is the positive differential input terminal of the current zeroing branch, and the emitter of the fifth NPN transistor Q5 is the negative differential input terminal of the current zeroing branch.

[0050] In detail, such as Figure 2As shown, the mixing control switch module includes a seventh NPN transistor Q7, an eighth NPN transistor Q8, a ninth NPN transistor Q9, and a tenth NPN transistor Q10. The mixing control signals include a first mixing control signal S2 and a second mixing control signal S2N. The emitter of the seventh NPN transistor Q7 is connected to the end of the first resistor R1 furthest from the third NPN transistor Q3, and the base of the seventh NPN transistor Q7 is connected to the first mixing control signal S2. The emitter of the eighth NPN transistor Q8 is connected to the emitter of the seventh NPN transistor Q7, and the base of the eighth NPN transistor Q8 is connected to the second mixing control signal S2N. The emitter of the ninth NPN transistor Q9 is connected to the end of the fourth resistor R4 furthest from the sixth NPN transistor Q6, and the base of the ninth NPN transistor Q9 is connected to the second mixing control signal S2N. The emitter of the tenth NPN transistor Q10 is connected to the ninth NPN transistor. The emitter of transistor Q9 and the base of transistor Q10 are connected to the first mixing control signal S2. Transistors Q7 and Q8 form the first mixing differential branch. The emitter of transistor Q7 (at node BN) is the input of the first mixing differential branch, and the collector of transistor Q7 is the first output of the first mixing differential branch. The collector of transistor Q8 is the second output of the first mixing differential branch. Transistors Q9 and Q10 form the second mixing differential branch. The emitter of transistor Q9 is the input of the second mixing differential branch (at node BP), and the collector of transistor Q9 is the first output of the second mixing differential branch. The collector of transistor Q10 is the second output of the second mixing differential branch.

[0051] In detail, such as Figure 2 As shown, the current-to-voltage conversion module includes a first load resistor R. L1 Second load resistor R L2 First load resistor R L1 One end is connected to the collector of the seventh NPN transistor Q7 and the collector of the ninth NPN transistor Q9, respectively, and the first load resistor R L1 The other end is connected to the working voltage V. CC The second load resistor R L2 One end is connected to the collector of the eighth NPN transistor Q8 and the collector of the tenth NPN transistor Q10, respectively, and the second load resistor R L2 The other end is connected to the working voltage V. CC Wherein, the first load resistor R L1 This forms the first conversion differential branch, with the first load resistor R. L1 One end connected to the collector of the seventh NPN transistor Q7 is the input terminal (current input terminal) of the first differential switching branch, and the first load resistor R L1One end connected to the collector of the seventh NPN transistor Q7 is the output terminal (voltage output terminal) of the first differential switching branch, and the second load resistor R... L2 This forms the second conversion differential branch, with the second load resistor R. L2 One end of the collector of the eighth NPN transistor Q8 is the input terminal (current input terminal) of the second differential switching branch, and the second load resistor R... L2 One end connected to the collector of the eighth NPN transistor Q8 is the output terminal (voltage output terminal) of the second conversion differential branch.

[0052] More in detail, such as Figure 2 As shown, the first load resistor R L1 Second load resistor R L2 The first load resistor R acts as the analog output current-to-voltage converter of the current-steering digital-to-analog converter. L1 One end of the collector of the seventh NPN transistor Q7 is connected to the negative terminal OUTn of the differential analog output of the current-driven digital-to-analog converter, and the second load resistor R... L2 One end of the collector of the eighth NPN transistor Q8 is connected to the positive terminal OUTp of the differential analog output of the current-driven digital-to-analog converter. The current-to-voltage conversion module generates a voltage proportional to the sum of the branch currents, where the branches have the same positive or negative direction. Therefore, the differential output of the current-driven digital-to-analog converter is the voltage difference between the negative terminal OUTn and the positive terminal OUTp of the differential analog output of the current-driven digital-to-analog converter.

[0053] In this configuration, the first NPN transistor Q1, the second NPN transistor Q2, the third NPN transistor Q3, the fourth NPN transistor Q4, the fifth NPN transistor Q5, the sixth NPN transistor Q6, the seventh NPN transistor Q7, the eighth NPN transistor Q8, the ninth NPN transistor Q9, and the tenth NPN transistor Q10 are heterojunction NPN transistors (or heterojunction NPN bipolar transistors), such as germanium-silicon heterojunction NPN transistors. A heterojunction bipolar transistor (HBT) is a type of bipolar transistor where the emitter and base regions use different semiconductor materials, thus forming a heterojunction (the PN junction between the emitter and base regions). Heterojunction bipolar transistors offer better high-frequency signal characteristics and base region emitter efficiency than conventional bipolar transistors, and can operate at signals up to hundreds of GHz.

[0054] In detail, such as Figure 3As shown, in an optional embodiment of the present invention, the mode control module includes a first buffer BUF1, a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, a fifth buffer BUF5, a first double-pole double-throw switch SW1, and a second double-pole double-throw switch SW2. The differential input terminal of the first buffer BUF1 is connected to an external differential clock signal CLKP / CLKN, and the differential output terminal of the first buffer BUF1 outputs a first clock signal CLKP_1 / CLKN_1. The differential input terminal of the second buffer BUF2 is connected to the differential output terminal of the first buffer BUF1, and the differential input terminal of the third buffer BUF3 is connected to the differential output terminal of the first buffer BUF1. The differential input terminals of the second buffer BUF2 and the third buffer BUF3 are connected in opposite phases. The differential output terminal of the second buffer BUF2 outputs a second clock signal CLKP_2 / CLKN_2. The third buffer BUF5... The differential output of UF3 outputs the third clock signal CLKP_3 / CLKN_3. The differential input of the fourth buffer BUF4 is connected to the differential output of the second buffer BUF2. The differential output of the fourth buffer BUF4 (corresponding to the differential signal CLKP_4 / CLKN_4) is connected to the second differential input of the first double-pole double-throw switch SW1. The first differential input of the first double-pole double-throw switch SW1 is connected to the first DC differential level signal V1N / V1P. The differential output of the first double-pole double-throw switch SW1 outputs the zero-reset control signal S1 / S1N. The differential output of the fifth buffer BUF5 (corresponding to the differential signal CLKP_5 / CLKN_5) is connected to the second differential input of the second double-pole double-throw switch SW2. The first differential input of the second double-pole double-throw switch SW2 is connected to the second DC differential level signal V2N / V2P. The differential output of the second double-pole double-throw switch SW2 outputs the mixing control signal S2 / S2N.

[0055] The control terminal of the first double-pole double-throw switch SW1 is connected to the control signal MODE1, and the control terminal of the second double-pole double-throw switch SW2 is connected to the control signal MODE2.

[0056] In detail, such as Figure 4As shown, in an optional embodiment of the present invention, the data synchronization latch module includes a pre-decoding data latch unit, a decoding unit, a post-decoding synchronization latch unit, and a data buffer output unit. The data input terminal of the pre-decoding data latch unit is connected to the input digital DATA. The clock input terminal of the pre-decoding data latch unit is connected to the first clock signal CLKP_1 / CLKN_1. The pre-decoding data latch unit performs latch reception processing on the input digital DATA. The data output terminal of the pre-decoding data latch unit is connected to the data input terminal of the decoding unit. The decoding unit performs decoding processing on the input digital DATA. The data output terminal of the decoding unit is connected to the data input terminal of the post-decoding synchronization latch unit. The clock input terminal of the post-decoding synchronization latch unit is connected to the second clock signal CLKP_2 / CLKN_2 and the third clock signal CLKP_3 / CLKN_3, respectively. The data output terminal of the post-decoding synchronization latch unit is connected to the data input terminal of the data buffer output unit. The data output terminal of the data buffer output unit outputs current control signals D1N / D1P to DnN / DnP.

[0057] More in detail, such as Figure 4 As shown, the pre-decoding data latch unit, the post-decoding synchronous latch unit, and the data buffer output unit all include multiple parallel unit structures. The post-decoding synchronous latch unit includes a master-slave latch structure. The clock input of the master latch is connected to the second clock signal CLKP_2 / CLKN_2, and the clock input of the slave latch is connected to the third clock signal CLKP_3 / CLKN_3.

[0058] Specifically, in an optional embodiment of the present invention, the manufacturing process is a standard 0.13μm SiGe BiCMOS process, and the operating voltage V... CC The voltage is 5V. The logic high of the current control signals D1N / D1P~DnN / in the first-level current switching module is 2.15V~2.05V, and the logic low is 1.85V~1.75V. The logic high of the zero-reset control signals S1 / S1N in the second-level zero-reset control switching module is 3.95V~4.05V, and the logic low is 3.65V~3.75V. The logic high of the mixing control signals S2 / S2N in the third-level mixing control switching module is 4.85V~4.95V, and the logic low is 4.55V~4.65V. All switches in the three-level modules use HBT transistors. Specifically, the emitter area of ​​the HBT transistors Q1 and Q2 in the current switching module is 0.10μm. 2 ~0.15μm 2 The HBT transistors selected for the zero-reset control switch module, Q3, Q4, Q5, and Q6, have an emitter area of ​​0.80 μm. 2 ~0.90μm 2The HBT transistors Q7, Q8, Q9, and Q10 in the mixer control switching module have an emitter area of ​​0.80 μm. 2 ~0.90μm 2 In the second-level zero-reset control switch module, resistors R1, R2, R3, and R4 are all positive temperature coefficient Salicided polycrystalline resistors with a square resistance of 7 ohms, and each resistor is 50Ω. The load resistor R... L1 and R L2 All are unsalicided polycrystalline resistors with negative temperature coefficients, a sheet resistance of 250 ohms / square, and a load resistance R. L1 and R L The value is 50Ω; the pre-decoding data latch unit, decoding unit, post-decoding synchronous latch unit, and data buffer output unit are all CML logic designs, and the signal channels all use HBT transistors; the double-pole double-throw switches SW1 and SW2 are both conventional CMOS switches.

[0059] More in detail, such as Figures 2-5 As shown, the working principle of the analog-domain controlled multi-mode current-rudder digital-to-analog converter in this invention is as follows:

[0060] To enable operation in multiple modes, this invention employs... Figure 2 The architecture shown includes a three-layer cascaded switching unit consisting of a current switching module, a zero-return control switching module, and a mixer control switching module, as well as a current-voltage conversion module.

[0061] The control signal for the first-level current switching module comes from the output digital signal of the data synchronization latch module. The data synchronization latch module receives and latches the input data DATA before decoding. Decoding (decoding the high-order data from the segmented current-steering digital-to-analog converter from binary code to thermometer code, while the low-order data undergoes appropriate buffering and delay) is determined based on the segmentation of the current-steering digital-to-analog converter. Then, the decoded data is latched synchronously in a master-slave configuration and finally buffered and output to provide the control signal for the current switching module, controlling the current flow direction of the current switching transistor. The three pairs of differential clock signals of the data synchronization latch module all originate from the three pairs of differential output clock signals of the mode control module. This phase relationship ensures that the received input data DATA is correctly latched, decoded, and then latched again, thereby controlling the current flow direction in the current switching module.

[0062] The second-level zero-point control switch module directs current from the differential switch branch to the current-to-voltage conversion module, or conversely, transfers this current to the operating voltage Vcc. The current flow enable and transfer are controlled by the zero-point control signals S1 / S1N output from the mode control module. The first zero-point control signal S1 and the second zero-point control signal S1N are differentially complementary. The first zero-point control signal S1 controls transistors Q3 and Q6 of the zero-point control switch module, while the second zero-point control signal S1N controls transistors Q4 and Q5. Current flow is enabled by the high-level first zero-point control signal S1, turning on transistors Q3 and Q6. Simultaneously, the low-level second zero-point control signal S1N turns off transistors Q4 and Q5. Current transfer is controlled by the high-level second zero-point control signal S1N. The low-level first zero-point control signal S1 turns off transistors Q3 and Q6, while the high-level second zero-point control signal S1N turns on transistors Q4 and Q5.

[0063] For the third-level mixer control switch module, when the current passing through the zero-reset control switch module is not transferred to the operating voltage Vcc by the second-level zero-reset control switch module, the third-level mixer control switch module alternately switches the current of the transistor Q3 branch according to the clock cycle. During the first half of the clock cycle, it directs the current to the negative terminal OUTn of the differential analog output, while during the second half of the clock cycle, it allows the current to flow alternately to the positive terminal OUTp of the differential analog output. Simultaneously, it alternately switches the current of the transistor Q6 branch according to the clock cycle, allowing the current to flow alternately to the negative terminal OUTn of the differential analog output during the first half of the clock cycle, while during the second half of the clock cycle, it directs the current to the negative terminal OUTp of the differential analog output. This is achieved through the two load resistors R in the current-to-voltage conversion module. L1 / R L2 The voltage difference OUT between the two load resistors is a voltage signal modulated by a clock frequency. This modulation is symmetrical because, due to the cross-connection, the level of the analog voltage provided by this output alternately represents binary words and their complements.

[0064] Therefore, the current-driven digital-to-analog converter provided by this invention has three operating modes, and the working principles of the three modes are as follows:

[0065] 1) When control signals MODE1=0 and MODE2=0, Figure 3 The output of the first double-pole double-throw switch SW1 of the medium-mode control module is connected to the first DC differential level signal V1P / V1N, and the output of the second double-pole double-throw switch SW2 is connected to the second DC differential level signal V2P / V2N. At this time... Figure 2The second-level zero-reset control switch module receives a first zero-reset control signal S1 = 1 and a second zero-reset control signal S1N = 0. Transistors Q3 and Q6 are turned on, while transistors Q4 and Q5 are turned off. Therefore, the zero-reset control switch module always enables current flow. Similarly, Figure 2 In the third-level mixer control switch module, the first mixer control signal S2=1 and the second mixer control signal S2N=0 are input. Transistors Q7 and Q10 are turned on, while transistors Q8 and Q9 are turned off. Therefore, the mixer control switch module always enables current flow. In this operating mode, both the second-level zero-reset control switch module and the third-level mixer control switch module always enable current flow without changing the direction of current flow. Their function is as a two-stage cascaded common-base amplifier. Since the common-base amplifier has the advantages of low input impedance, high output impedance, and current amplification, the analog output signal bandwidth of the current-controlled digital-to-analog converter is wider. This mode is called the conventional mode.

[0066] 2) When control signals MODE1 = 1 and MODE2 = 0, Figure 3 In the medium-mode control module, the output of the first double-pole double-throw switch SW1 is connected to the differential clock signal CLKP_4 / CLKN_4, and the output of the second double-pole double-throw switch SW2 is connected to the second DC differential level signal V2P / V2N. Figure 2 The input control signal of the second-level zero-reset control switch module provides the mode control module with two complementary differential control signals CLKP_4 / CLKN_4. Current flow is enabled by a high-level CLKP_4, turning on transistors Q3 and Q6; simultaneously, a low-level CLKN_4 turns off transistors Q4 and Q5. Current transfer is controlled by a high-level CLKN_4; a low-level CLKP_4 turns off transistors Q3 and Q6, while a high-level CLKN_4 turns on transistors Q4 and Q5. The control signals CLKP_4 / CLKN_4 are periodic, with their period corresponding to the clock frequency of the current-driven digital-to-analog converter. Figure 3The intermediate mode control module ensures that the control signals CLKP_4 / CLKN_4 only enable the current supplied to the current-to-voltage conversion module when the logic level of the data output from the data synchronization latch circuit is stable. At this time, the first mixing control signal S2=1 and the second mixing control signal S2N=0 are input to the third-level mixing control switch module. Transistors Q7 and Q10 are turned on, and transistors Q8 and Q9 are turned off. Therefore, the mixing control switch module also always enables the flow of current. Its function is as a first-stage common-base amplifier. As the common-base amplifier has the advantages of low input impedance, high output impedance, and current amplification, it still makes the analog output signal bandwidth of the current-driven digital-to-analog converter wider. In this mode, due to the action of the zero-reset switch under the control signals of CLKP_4 / CLKN_4, the analog output current of the current-driven digital-to-analog converter is transferred to the operating voltage Vcc in the first half of the cycle, and switched to the current-to-voltage conversion module in the second half of the cycle. This cycle repeats periodically. This mode is called zero-reset mode. When the current-steering digital-to-analog converter operates in zero-level mode, it can operate in the second Nyquist zone, while extending dynamics and linearity by eliminating noise at transition edges.

[0067] 3) When control signals MODE1=0 and MODE2=1, Figure 3 In the medium-mode control module, the output of the first double-pole double-throw switch SW1 is connected to the first DC differential level signal V1P / V1N, and the output of the second double-pole double-throw switch SW2 is connected to the differential clock signal CLKP_5 / CLKN_5. Figure 2The first zero-reset control signal S1=1 and the second zero-reset control signal S1N=0 are input to the zero-reset control switch module of the second level. Transistors Q3 and Q6 are turned on, and transistors Q4 and Q5 are turned off. Therefore, the zero-reset control switch module always enables the flow of current. Simultaneously, two complementary differential signals CLKP_5 / CLKN_5, periodically controlled by the clock frequency of the current-driven digital-to-analog converter, control the mixer switch in the third-level zero-control switch module to alternately switch the currents of the two differential branches of transistors Q3 and Q6. During the half-cycle of CLKP_5 being high, the current of transistor Q3 flows directly to the negative terminal OUTn of the differential analog output; during the half-cycle of CLKP_5 being low, the current of transistor Q3 is switched and flows crosswise to the positive terminal OUTp of the differential analog output, ultimately being sent to the current-to-voltage conversion module. Similarly, during the half-cycle of CLKN_5 being high, the current of transistor Q6 flows directly to the positive terminal OUTp of the differential analog output; during the half-cycle of CLKN_5 being low, the current of transistor Q6 is switched and flows crosswise to the negative terminal OUTn of the differential analog output, ultimately being sent to the current-to-voltage conversion module. This cycle repeats periodically, and this mode is called the mixing mode. When the current-driven digital-to-analog converter operates in mixer mode, its sin(x) / x roll-off occurs at a higher frequency than in return-to-zero mode. Therefore, it can be optimized for performance in the lower half of the second Nyquist zone or the third Nyquist zone, and can also operate in the first half of the fourth Nyquist zone. Mixer mode is best suited for operation at high output frequencies.

[0068] Therefore, to address the different system requirements for the operating bandwidth and fundamental power of the current-controlled digital-to-analog converter (DC-ADC), this invention cascades a zero-reset control switch module and a mixer control switch module—a total of two layers of control switches—above the conventional first-level current switch module. The second-layer zero-reset control signal S1 / S1N controls the zero-reset mode of the DC-ADC, and the third-layer mixer control signal S2 / S2N controls the mixer mode. In this way, the zero-reset mode and the mixer mode extend the output spectrum sin(x) / x envelope roll-off of the DC-ADC, thereby expanding the analog output bandwidth of the DC-ADC. Figure 5 The diagram shows the analog output time-domain waveforms of the present invention in three operating modes.

[0069] Secondly, based on the above-mentioned design concept of a current-controlled digital-to-analog converter with multiple operating modes in the analog domain, this invention also provides a design method for a current-controlled digital-to-analog converter with multiple operating modes in the analog domain. A zero-reset control switch module and a mixing control switch module are added to the differential output terminal of the current switching module of the current-controlled digital-to-analog converter. Through the adjustment and control of the zero-reset control switch module and the mixing control switch module, the current-controlled digital-to-analog converter has three operating modes: normal mode, zero-reset mode and mixing mode, and the output bandwidth of the current-controlled digital-to-analog converter is expanded.

[0070] In summary, the current-controlled digital-to-analog converter (DAC) and its design method with multiple operating modes in analog domain control provided by this invention add two levels of switches—a zero-reset control switch module and a mixing control switch module—between the current switching module and the current-voltage conversion module. Through the adjustment and control of the zero-reset control switch module and the mixing control switch module, the DAC has three operating modes: normal mode, zero-reset mode, and mixing mode. The free switching between these three operating modes expands the output bandwidth of the DAC. Furthermore, compared to conventional structural improvements to each current switching unit in the current switching module, this method does not require increasing the number of switching transistors in each current switching unit; it only adds two control switch modules overall, effectively reducing the number of switching transistors and the corresponding switch control signals, simplifying the structure of the DAC and reducing energy consumption.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An analog domain controlled multi-mode current steering digital-to-analog converter, comprising: The application relates to a current digital-to-analog converter, comprising: a current switch module comprising a plurality of current switch units, differential outputs of the plurality of current switch units being connected in parallel; a zero-return control switch module comprising a current transmission branch and a current zero-return branch, an input end of the current transmission branch and an input end of the current zero-return branch being connected to outputs of the current switch module; a mixing control switch module comprising a first mixing differential branch and a second mixing differential branch, an input end of the first mixing differential branch being connected to a differential output negative end of the current transmission branch, and an input end of the second mixing differential branch being connected to a differential output positive end of the current transmission branch; a current-voltage conversion module comprising a first conversion differential branch and a second conversion differential branch, input ends of the first conversion differential branch being connected to a first output end of the first mixing differential branch and a first output end of the second mixing differential branch respectively, and input ends of the second conversion differential branch being connected to a second output end of the first mixing differential branch and a second output end of the second mixing differential branch respectively, so as to convert the transmitted current into voltage and perform differential output; a data synchronization latching module which sequentially performs latching receiving, decoding, synchronization latching and buffer output processing on input digital codes, obtains current control signals and outputs the current control signals to each current switch unit, and controls current flow directions in the current switch units through the current control signals; a mode control module which generates clock signals and outputs the clock signals to the data synchronization latching module, generates zero-return control signals and outputs the zero-return control signals to the zero-return control switch module, generates mixing control signals and outputs the mixing control signals to the mixing control switch module, controls current flow directions in the zero-return control switch module through the zero-return control signals, and controls current flow directions in the mixing control switch module through the mixing control signals; wherein, based on adjustment and control of the zero-return control signals and the mixing control signals, working modes of the current digital-to-analog converter include a normal mode, a zero-return mode and a mixing mode; the data synchronization latching module comprises a pre-decoding data latching unit, a decoding unit, a post-decoding synchronization latching unit and a data buffer output unit, a data input end of the pre-decoding data latching unit is connected to the input digital codes, a clock input end of the pre-decoding data latching unit is connected to a first clock signal, the pre-decoding data latching unit performs latching receiving processing on the input digital codes, a data output end of the pre-decoding data latching unit is connected to a data input end of the decoding unit, the decoding unit performs decoding processing on the input digital codes, a data output end of the decoding unit is connected to a data input end of the post-decoding synchronization latching unit, clock input ends of the post-decoding synchronization latching unit are connected to a second clock signal and a third clock signal respectively, a data output end of the post-decoding synchronization latching unit is connected to a data input end of the data buffer output unit, and a data output end of the data buffer output unit outputs the current control signals.

2. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 1, wherein, The current switch unit comprises a first NPN transistor, a second NPN transistor and a tail current source, the emitter of the first NPN transistor is connected to ground through the tail current source, the base of the first NPN transistor is connected to one of the current control signals, the emitter of the second NPN transistor is connected to the emitter of the first NPN transistor, the base of the second NPN transistor is connected to another of the current control signals, wherein the collector of the first NPN transistor is the differential output positive terminal of the current switch unit, and the collector of the second NPN transistor is the differential output negative terminal of the current switch unit.

3. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 2, wherein, The zero reset control switch module comprises a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a first current source, a second current source, a first resistor, a second resistor, a third resistor and a fourth resistor, the zero reset control signal comprises a first zero reset control signal and a second zero reset control signal, the emitter of the third NPN transistor is connected to ground through the first current source in series, the emitter of the third NPN transistor is also connected to the collector of the first NPN transistor, the base of the third NPN transistor is connected to the first zero reset control signal, the collector of the third NPN transistor is connected to an external output through the first resistor in series, the emitter of the fourth NPN transistor is connected to the emitter of the third NPN transistor, the base of the fourth NPN transistor is connected to the second zero reset control signal, the collector of the fourth NPN transistor is connected to a working voltage through the second resistor in series, the emitter of the fifth NPN transistor is connected to ground through the second current source in series, the emitter of the fifth NPN transistor is also connected to the collector of the second NPN transistor, the base of the fifth NPN transistor is connected to the second zero reset control signal, the collector of the fifth NPN transistor is connected to the working voltage through the third resistor in series, the emitter of the sixth NPN transistor is connected to the emitter of the fifth NPN transistor, the base of the sixth NPN transistor is connected to the first zero reset control signal, and the collector of the sixth NPN transistor is connected to an external output through the fourth resistor in series, wherein the third NPN transistor, the first resistor, the sixth NPN transistor and the fourth resistor constitute the current transmission branch in a differential structure, the fourth NPN transistor, the second resistor, the fifth NPN transistor and the third resistor constitute the current zero reset branch in a differential structure, the emitter of the third NPN transistor is a differential input positive terminal of the current transmission branch, the emitter of the sixth NPN transistor is a differential input negative terminal of the current transmission branch, one end of the first resistor away from the third NPN transistor is a differential output negative terminal of the current transmission branch, one end of the fourth resistor away from the sixth NPN transistor is a differential output positive terminal of the current transmission branch, the emitter of the fourth NPN transistor is a differential input positive terminal of the current zero reset branch, and the emitter of the fifth NPN transistor is a differential input negative terminal of the current zero reset branch.

4. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 3, wherein, The mixing control switch module comprises a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor and a tenth NPN transistor, the mixing control signal comprises a first mixing control signal and a second mixing control signal, the emitter of the seventh NPN transistor is connected to one end of the first resistor away from the third NPN transistor, the base of the seventh NPN transistor is connected to the first mixing control signal, the emitter of the eighth NPN transistor is connected to the emitter of the seventh NPN transistor, the base of the eighth NPN transistor is connected to the second mixing control signal, the emitter of the ninth NPN transistor is connected to one end of the fourth resistor away from the sixth NPN transistor, the base of the ninth NPN transistor is connected to the second mixing control signal, the emitter of the tenth NPN transistor is connected to the emitter of the ninth NPN transistor, and the base of the tenth NPN transistor is connected to the first mixing control signal, wherein the seventh NPN transistor and the eighth NPN transistor constitute the first mixing differential branch, the emitter of the seventh NPN transistor is the input end of the first mixing differential branch, the collector of the seventh NPN transistor is the first output end of the first mixing differential branch, the collector of the eighth NPN transistor is the second output end of the first mixing differential branch, the ninth NPN transistor and the tenth NPN transistor constitute the second mixing differential branch, the emitter of the ninth NPN transistor is the input end of the second mixing differential branch, the collector of the ninth NPN transistor is the first output end of the second mixing differential branch, and the collector of the tenth NPN transistor is the second output end of the second mixing differential branch.

5. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 4, wherein, The current-voltage conversion module comprises a first load resistor and a second load resistor, one end of the first load resistor is connected to the collector of the seventh NPN transistor and the collector of the ninth NPN transistor respectively, the other end of the first load resistor is connected to the working voltage, one end of the second load resistor is connected to the collector of the eighth NPN transistor and the collector of the tenth NPN transistor respectively, and the other end of the second load resistor is connected to the working voltage, wherein the first load resistor constitutes the first conversion differential branch, one end of the first load resistor connected to the collector of the seventh NPN transistor is the input end of the first conversion differential branch, and the other end of the first load resistor connected to the collector of the seventh NPN transistor is the output end of the first conversion differential branch, the second load resistor constitutes the second conversion differential branch, one end of the second load resistor connected to the collector of the eighth NPN transistor is the input end of the second conversion differential branch, and the other end of the second load resistor connected to the collector of the eighth NPN transistor is the output end of the second conversion differential branch.

6. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 5, wherein, The first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor, the fifth NPN transistor, the sixth NPN transistor, the seventh NPN transistor, the eighth NPN transistor, the ninth NPN transistor and the tenth NPN transistor are heterojunction NPN transistors.

7. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 1, wherein, The decoding synchronous latch unit comprises a master-slave latch structure.

8. The analog-domain controlled multi-mode current steering digital-to- analog converter of claim 7, wherein, The mode control module comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a first double-pole double-throw switch and a second double-pole double-throw switch, differential input terminals of the first buffer are connected with an external differential clock signal, differential output terminals of the first buffer output a first clock signal, differential input terminals of the second buffer are connected with differential output terminals of the first buffer, differential input terminals of the third buffer are connected with differential output terminals of the first buffer, differential input terminals of the second buffer and the third buffer are connected with each other in an inverting manner, a differential output terminal of the second buffer outputs a second clock signal, a differential output terminal of the third buffer outputs a third clock signal, a differential input terminal of the fourth buffer is connected with a differential output terminal of the second buffer, a differential output terminal of the fourth buffer is connected with a second differential input terminal of the first double-pole double-throw switch, a first differential input terminal of the first double-pole double-throw switch is connected with a first DC differential level signal, differential output terminals of the first double-pole double-throw switch output the zero-return control signal, a differential output terminal of the fifth buffer is connected with a second differential input terminal of the second double-pole double-throw switch, a first differential input terminal of the second double-pole double-throw switch is connected with a second DC differential level signal, and differential output terminals of the second double-pole double-throw switch output the mixing control signal.

9. A design method for a current steering digital-to-analog converter (DAC) for analog domain control multi-mode operation as claimed in any one of claims 1 to 8, characterized in that, The zero-return control switch module and the mixing control switch module are additionally arranged on differential output terminals of the current switch module of the current steering digital-to-analog converter, the current steering digital-to-analog converter has three working modes, i.e., a normal mode, a zero-return mode and a mixing mode, through adjustment and control of the zero-return control switch module and the mixing control switch module, and the output bandwidth of the current steering digital-to-analog converter is expanded.

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