Column analog-to-digital converter and its local counting method

Abstract

This disclosure provides a column analog-to-digital converter (ADC) and a local counting method. The column ADC includes multiple ADCs connected in parallel with each other. Each ADC includes a comparator and a counting circuit. The comparator compares a ramp voltage with one of a plurality of column signals to generate a comparator output signal. The counting circuit triggers a delay line circuit of the counting circuit according to the comparator output signal to generate first delayed data, re-triggers the delay line circuit according to a base clock to generate first re-triggered delayed data, and compares the first delayed data with the first re-triggered delayed data to generate a first count output.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more specifically, to a column analog-to-digital converter (ADC) and its local counting method. Background Technology

[0002] Conventional CMOS image sensors (CIS) typically employ column analog-to-digital converters (CADCs). A CADC usually consists of multiple successive-approximation register analog-to-digital converters (SAR ADCs) or multiple single-slope ADCs. Each single-slope ADC receives the column signal corresponding to the pixel row, and multiple single-slope ADCs share a digital-to-analog converter (DAC), a high-speed clock generator, and a sense amplifier.

[0003] Single-slope ADCs use a counter to calculate the output length of a signal generated by comparing a ramp voltage with a column signal that serves as the ADC output. Therefore, the ADC's resolution depends on the available counting time and counting frequency. However, the counting frequency is typically limited by the clock tree load, which increases the ADC's counting time at high resolutions. Furthermore, due to the high counting frequency, the CADC counter faces a significant challenge in power consumption.

[0004] The widespread use of Correlated Double Sampling (CDS) and High Dynamic Range Imaging (HDR) in applications such as touch control, image sensing, and fingerprint recognition reduces available counting time. Furthermore, the frame rate is limited by the ADC's conversion time.

[0005] Conventional techniques employ phase delays to improve ADC resolution without increasing the counting frequency. For example, three phase delays are added to the least significant bit (LSB) of a high-speed clock. That is, half a cycle of bit [0] is divided into four equal parts to increase the ADC resolution by two bits. However, the phase delay of the LSB is typically generated by a delay-locked loop (DLL) or a phase-locked loop (PLL), which amplifies the layout area and power consumption. Furthermore, different phase delays require path balancing in the layout to avoid increasing the ADC's differential nonlinearity (DNL), but this increases the complexity of the layout design.

[0006] Another conventional technique uses a local delay line to generate multiple phases in the LSB, and the logic circuit determines which phase the transition time of the input signal falls into in order to output the corresponding binary code based on the determination result. However, it requires additional correction circuitry to eliminate PVT variations. Summary of the Invention

[0007] The present invention provides a column analog-to-digital converter (CADC) with a local counting method, which can improve counting resolution by means of a local delay circuit.

[0008] Embodiments of the present invention provide a column analog-to-digital converter (ADC). The column ADC comprises multiple ADCs connected in parallel with each other. Each ADC includes a comparator and a counting circuit. The comparator compares a ramp voltage with one of a plurality of column signals to generate a comparator output signal. The counting circuit triggers a delay line circuit of the counting circuit according to the comparator output signal to generate first delayed data, re-triggers the delay line circuit according to a base clock to generate first re-triggered delayed data, and compares the first delayed data with the first re-triggered delayed data to generate a first count output.

[0009] Embodiments of the present invention provide a local counting method. A column analog-to-digital converter (ADC) comprises multiple ADCs connected in parallel with each other. The local counting method for each ADC includes the following: Each ADC compares a ramp voltage with one of the column signals to generate a comparator output signal. Each ADC triggers a delay line circuit of the counting circuit according to the comparator output signal to generate first delayed data. Each ADC re-triggers the delay line circuit according to a base clock to generate first re-triggered delayed data. Each ADC compares the first delayed data with the first re-triggered delayed data to generate a first count output.

[0010] Based on the above, in an embodiment of the present invention, in order to solve the frequency limitation caused by timing violations and long wires and reduce system complexity, an embodiment of the present invention provides a column analog-to-digital converter (CADC) with a local counting method, which can perform local counting by comparing the triggering result and re-triggering result of the local delay line circuit, so as to improve the counting resolution and perform self-compensation without correction circuitry.

[0011] To make the above features and advantages of the present invention more readily understood, embodiments with accompanying drawings are described in detail below. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 This is a schematic diagram illustrating a column analog-to-digital converter according to an embodiment of the present invention.

[0014] Figure 2 A circuit block diagram illustrating a counting circuit according to an embodiment of the present invention is provided.

[0015] Figure 3A A timing diagram illustrating local counting according to an embodiment of the present invention is provided.

[0016] Figure 3B A timing diagram illustrating local counting according to another embodiment of the present invention is provided.

[0017] Figure 4A and Figure 4B This is a schematic diagram illustrating local counting according to an embodiment of the present invention.

[0018] Figure 5 A circuit block diagram of a counting circuit according to another embodiment of the present invention is shown.

[0019] Figure 6 A flowchart illustrating local counting according to an embodiment of the present invention.

[0020] Explanation of icon numbers

[0021] 0, 1: Logic;

[0022] 100: Column analog-to-digital converter;

[0023] 110_1, 110_2, 110_3…110_N: Analog-to-digital converters;

[0024] 120: Digital-to-analog converter;

[0025] 130: Readout amplifier;

[0026] 140_1, 140_2, 140_3…140_N: comparators;

[0027] 150_1, 150_2, 150_3…150_N: Counting circuit;

[0028] 160_1, 160_2, 160_3…160_N: Delay line circuits;

[0029] 210: Main counting circuit;

[0030] 220: Local counting circuit;

[0031] 231: First multiplexer;

[0032] 232: First delay line;

[0033] 233: Data storage circuit;

[0034] 234: Second multiplexer;

[0035] 235: Second delay line;

[0036] 240: Re-trigger circuit;

[0037] 241: Edge detector;

[0038] 242: Re-trigger source;

[0039] 250: Determine the circuit;

[0040] CLKB: Base clock;

[0041] CMP, CMP1, CMP2, CMP3…CMPN: Comparator output signals;

[0042] CO1, CO2, CO3…CON: Count output;

[0043] CO1A, CO2A, CO3A…CONA: First count output;

[0044] CO1B, CO2B, CO3B…CONB: Second count output;

[0045] CS1, CS2, CS3…CSN: column signals;

[0046] DET_LAT: Latch signal;

[0047] DET_OUT: Determine the signal;

[0048] DL_INACT: Re-trigger signal;

[0049] DL_LAT: Delay line data latch signal;

[0050] DL1A, DL1A2, DL1A3…DL1AN: First delayed data;

[0051] DL1B, DL1B2, DL1B3…DL1BN: First re-trigger delay data;

[0052] DL1, DL2: Second delayed data;

[0053] DOUT: Output;

[0054] S1, S2, S3, S4, S5, S6, S610, S620, S630, S640: Steps;

[0055] T1: First cycle;

[0056] T2: Second cycle;

[0057] T3: Third cycle;

[0058] VRAMP: Ramp voltage. Detailed Implementation

[0059] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and this specification to refer to the same or similar parts.

[0060] refer to Figure 1 The column analog-to-digital converter 100 includes multiple analog-to-digital converters 110_1 to 110_N, a digital-to-analog converter 120, and a sense amplifier 130 connected in parallel with each other. The digital-to-analog converter 120 generates a ramp voltage VRAMP. The analog-to-digital converters 110_1 to 110_N receive the ramp voltage VRAMP, column signals CS1 to CSN, and a base clock CLKB to generate count outputs CO1 to CON. Column signals CS1 to CSN are provided by corresponding pixel columns of an image sensor (e.g., a CMOS image sensor). The base clock CLKB can be implemented using a conventional VCO, PLL, or DLL, but is not limited thereto. The sense amplifier 130 receives and reads the count outputs CO1 to CON (data) to generate an output DOUT (logic), and the output DOUT can be provided to a bit line in memory. The implementation of the digital-to-analog converter 120 and the sense amplifier 130 is not limited in any particular manner.

[0061] An analog-to-digital converter 110_1 is provided as an example. The ADC 110_1 includes a comparator 140_1 and a counting circuit 150_1, with the counting circuit 150_1 including a built-in delay line circuit 160_1. The comparator 140_1 compares a ramp voltage VRAMP with a column signal CS1 to generate a comparator output signal CMP1. Subsequently, the counting circuit 150_1 triggers the delay line circuit 160_1 according to the comparator output signal CMP1 to generate first delayed data DL1A, and then triggers the delay line circuit 160_1 again according to a base clock CLKB to generate first re-triggered delayed data DL1B. The first delayed data DL1A is compared with the first re-triggered delayed data DL1B to generate a first count output CO1A. The implementation of the comparator 140_1 is not limited.

[0062] In this embodiment, the counting circuit 150_1 further counts the base clock CLKB based on the comparator output signal CMP1 to generate a second counting output CO2B, and combines the first counting output CO1A and the second counting output CO1B to generate a counting output CO1.

[0063] Furthermore, since analog-to-digital converters 110_2 to 110_N are repeated in columns and are similar to analog-to-digital converter 110_1, their details with the corresponding comparators 140_2 to 140_N, counting circuits 150_2 to 150_N, delay line circuits 160_2 to 160_N, comparator output signal CMP2 to comparator output signal CMPN, first delayed data DL1A2 to first delayed data DL1AN, first re-trigger delayed data DL1B2 to first re-trigger delayed data DL1BN, first count output CO2A to first count output CONA, and second count output CO2B to second count output CONB will not be repeated.

[0064] Figure 2 According to an embodiment of the present invention Figure 1 The circuit block of the counting circuit 150_1 is shown in the figure. Figure 2In this embodiment, the counting circuit 150_1 includes a main counting circuit 210 and a local counting circuit 220. The main counting circuit 210 counts the base clock CLKB to generate a second count output CO1B before the comparator output signal CMP1 enables it, and is implemented based on a conventional single-slope ADC, but is not limited thereto. The local counting circuit 220 triggers the delay line circuit 160_1 according to the comparator output signal CMP1 after it is enabled to generate a first delayed data DL1A, and then triggers the delay line circuit 160_1 again according to the base clock CLKB to generate a first re-triggered delayed data DL1B. The first delayed data DL1A is compared with the first re-triggered delayed data DL1B to generate the first count output CO1A. The relevant timing will be described subsequently. It should be noted that this architecture effectively improves the resolution of the CADC due to the addition of the local counting circuit 220. For example, if the second count output CO1B provided by the main counting circuit 210 is 10 bits and the first count output CO1A provided by the local counting circuit 220 is 1 bit, then the resolution of the CADC will be increased to 11 bits. If the second count output CO1B provided by the main counting circuit 210 is 10 bits and the first count output CO1A provided by the local counting circuit 220 is 2 bits, then the resolution of the CADC will be increased to 12 bits.

[0065] The local counting circuit 220 includes a delay line circuit 160_1, a re-trigger circuit 240, and a judgment circuit 250. (Reference) Figure 2 and Figure 3A The delay line circuit 160_1 receives the comparator output signal CMP1 and is triggered during the first cycle T1 of the base clock CLKB after the comparator output signal CMP1 is enabled to generate the first delayed data DL1A.

[0066] The re-trigger circuit 240 is coupled to the delay line circuit 160_1. The re-trigger circuit 240 receives the base clock CLKB. During the second cycle T2, when the edge of the base clock CLKB is detected, the re-trigger circuit 240 outputs a re-trigger signal DL_INACT to the delay line circuit 160_1. During the third cycle T3, the re-trigger circuit 240 re-triggers the delay line circuit 160_1 based on the re-trigger signal DL_INACT to generate the first re-trigger delayed data DL1B. The second cycle T2 is later than the first cycle T1, and the third cycle T3 is later than the second cycle T2.

[0067] The determination circuit 250 is coupled to the delay line circuit 160_1. The determination circuit 250 receives first delayed data DL1A and first re-trigger delayed data DL1B from the delay line circuit 160_1, and compares the first delayed data DL1A with the first re-trigger delayed data DL1B to generate a first count output CO1A. Details will be described later.

[0068] refer to Figure 2 and Figure 3A The delay line circuit 160_1 includes a first multiplexer 231, a first delay line 232, a data storage circuit 233, a second multiplexer 234, and a second delay line 235. The first multiplexer 231 receives the comparator output signal CMP1 and the second delayed data DL2, and selects to output the comparator output signal CMP1 during the first period T1 and selects to output the second delayed data DL2 during the third period T3. In this embodiment, the second delayed data DL2 received by the first multiplexer 231 only includes the output DL2[0].

[0069] The first delay line 232 is coupled to the first multiplexer 231 and includes a plurality of first buffers (not shown) connected in series. During a first period T1, the first delay line 232 sequentially delays the comparator output signal CMP1 by means of the first buffers to generate first delayed data DL1A, and during a third period T3, sequentially delays the second delayed data DL2 to generate first re-trigger delayed data DL1B. The first delayed data DL1A includes, as shown below... Figure 3A The first delay data DL1A[0] to DL1A

[14] shown in the figure correspond to the outputs DL1[0] to DL1

[14] of the first buffer during the first period T1, respectively. The first re-trigger delay data DL1B includes, as shown in the figure. Figure 3A The first re-trigger data DL1B[0] to DL1B

[14] shown in the figure correspond to the outputs DL1[0] to DL1

[14] of the first buffer during the third cycle T3.

[0070] Data storage circuit 233 is coupled between first delay line 232 and judgment circuit 250. Data storage circuit 233 stores first delayed data DL1A[0] to first delayed data DL1A

[14] during the second period T2 in response to delay line data latch signal DL_LAT.

[0071] In one embodiment, a second multiplexer 234 is coupled between a re-trigger circuit 240 and a second delay line circuit 235, and the second delay line circuit 235 is coupled between the second multiplexer 234 and a first multiplexer 231. The second delay line 235 is coupled between the second multiplexer 234 and the first multiplexer 231, and the second delay line 235 includes a plurality of second buffers (not shown) connected in series with each other.

[0072] During the second period T2, the first buffer of the first delay line 232 and the second buffer of the second delay line 235 corresponding to the non-inverted first delayed data DL1A during the first period T1 are disabled according to the re-trigger signal DL_INACT. For example, refer to Figure 3A During the first cycle T1, outputs DL1[0] to DL1[3] are inverted while outputs DL1[4] to DL1

[14] are not inverted. Therefore, during the second cycle T2, the first buffer corresponding to outputs DL1[4] to DL1

[14] and the second buffer corresponding to outputs DL2[4] to DL2

[14] are both disabled according to the re-trigger signal DL_INACT until the end of the third cycle T3.

[0073] During the third cycle T3, the second buffer corresponding to the output DL2[3] is selected by the second multiplexer 234 as the input of the second delay line 235, so that the second buffer of the second delay line 235 generates output DL2[0] to output DL2[3] according to the re-trigger signal DL_INACT and the base clock CLKB under pulse shift and output DL2[4] to output DL2

[14] disabled. In this embodiment, the first buffer of the first delay line 232 sequentially delays the second delayed data DL2 to generate the first re-trigger delayed data DL1B[0] to the first re-trigger delayed data DL1B

[14] . It should be noted that in Figure 3A In the embodiment illustrated, the output DL1[0] delays the second delayed data DL2 to first generate the first re-trigger delayed data DL1B[0]. Figure 3B In another embodiment illustrated herein, the first re-trigger delay data DL1B[0] is finally generated.

[0074] refer to Figure 2 and Figure 3A The re-trigger circuit 240 includes an edge detector 241 and a re-trigger source 242. The edge detector 241 receives the base clock CLKB at the start of the second period T2 and detects the transition state of the base clock CLKB to generate a delay-line data latch signal DL_LAT. The re-trigger source 242 is coupled to the edge detector 241, and the re-trigger source 242 performs a step transformation on the delay-line data latch signal DL_LAT during the second period T2 to generate a re-trigger signal DL_INACT.

[0075] Please refer to Figure 4A , Figure 4B , Figure 2As shown in Figure 3, in step S1, the first delay line 232 resets the outputs DL1[0] to DL1

[14] of the first buffer, such that the outputs DL1[0] to DL1

[14] are reset to logic 0 before the comparator output signal CMP1 is enabled. Then, in step S2, when the comparator output signal CMP1 is enabled, the first delay line 232 begins to sequentially delay the comparator output signal CMP1 so that the first delayed data DL1A[0] to DL1A

[14] are generated when the base clock CLKB transitions from logic high to logic low. In this embodiment, the first delayed data DL1A[0] to DL1A[3] are logic 1 and the first delayed data DL1A[4] to DL1A

[14] are logic 0, because the base clock CLKB transitions from logic high to logic low immediately after the output DL1[3] transitions to logic high, thus stopping the delay operation of the first delay line 232.

[0076] In step S3, when the delay line data latch signal DL_LAT is enabled, the data storage circuit 233 is activated to store the first delayed data DL1A[0] to the first delayed data DL1A

[14] . For example, Figure 4A The memory [0] to memory [3] shown in the figure are logic 1, the same as the first delayed data DL1A[0] to first delayed data DL1A[3], and the memory [4] to memory

[14] are logic 0, the same as the first delayed data DL1A[4] to first delayed data DL1A

[14] . In addition, when the trigger signal DL_INACT is enabled, the first buffer of the first delay line 232 and the second buffer of the second delay line 235 corresponding to the non-inverted first delayed data DL1A[4] to first delayed data DL1A

[14] are disabled. For example, depending on the design requirements, the outputs DL1[4] to DL1

[14] of the disabled first buffer and the outputs DL2[4] to DL2

[14] of the disabled second buffer are set to 1, but there is no restriction.

[0077] Next, in step S4, when the re-trigger signal DL_INACT is enabled, the first delay line 232 resets the outputs DL1[0] to DL1[3] of the first buffer, so that the outputs DL1[0] to DL1[3] are reset to logic 0. In step S5, when the base clock CLKB transitions to logic high again as detected by the edge detector 241, the re-trigger source 242 re-triggers the enabled second buffer of the second delay line 235 by selecting the second buffer corresponding to the output DL2[3] as the input of the second delay line 235 with a fixed output through the second multiplexer 234 to generate the outputs DL2[3] to DL2[0] in sequence, so that the second delayed data DL2 is generated and provided to the first delay line 232 through the first multiplexer 231. Next, the first delay line 232 sequentially delays the second delay data DL2 so that when the base clock CLKB transitions from logic high to logic low again, the first re-trigger delay data DL1B[0] to the first re-trigger delay data DL1B

[14] are generated. Figure 3A , Figure 4A as well as Figure 4B In the embodiment illustrated, the pulse direction is shifted from output DL2[3] to output DL2[0], and then from output DL1[0] to output DL1[3].

[0078] Next, in step S6, the judgment circuit 250 compares the first delayed data DL1A[0] to the first delayed data DL1A[3] with the first re-trigger delayed data DL1B[0] to the first re-trigger delayed data DL1B[3] based on the judgment signal DET_OUT to generate the first count output CO1A after the end of step S5. Figure 3A , Figure 4A as well as Figure 4B In the embodiment illustrated, the judgment circuit 250 determines whether the first delayed data DL1A[0] to the first delayed data DL1A[3] from the data storage circuit 233 is the same as the first re-trigger delayed data DL1B[0] to the first re-trigger delayed data DL1B[3] from the first delay line 232, and latches the judgment result based on the latch signal DET_LAT and waits to output the first count output CO1A. Specifically, if the first delayed data DL1A[0] to the first delayed data DL1A[3] is the same as the first re-trigger delayed data DL1B[0] to the first re-trigger delayed data DL1B[3], or if the first delayed data DL1A[0] to the first delayed data DL1A[3] and the first re-trigger delayed data DL1B[0] to the first re-trigger delayed data DL1B[3] are both logic 1, then the first count output CO1A, which is equal to logic 1, will be output. This indicates that the comparator output signal CMP1 is enabled after half the duty cycle of the base clock CLKB. Figure 3AAs shown in the figure. On the other hand, if the first delay data DL1A[0] to the first delay data DL1A[3] are not the same as the first re-trigger delay data DL1B[0] to the first re-trigger delay data DL1B[3], or if the first delay data DL1A[0] to the first delay data DL1A[3] and the first re-trigger delay data DL1B[0] to the first re-trigger delay data DL1B[3] are not all logic 1, then the first count output CO1A, which is equal to logic 0, will be output. This means that the comparator output signal CMP1 is enabled before half of the duty cycle of the base clock CLKB (not shown).

[0079] exist Figure 3B In another embodiment illustrated, the judgment circuit 250 only determines whether the first delayed data DL1A[0] (the starting data from the first delayed data DL1A[0] to the first delayed data DL1A

[14] ) is the same as the first re-trigger delayed data DL1B[0] (the starting data from the first delayed data DL1A[0] to the first delayed data DL1A

[14] ), thereby further saving computational resources. It should be noted that in this embodiment, the shift pulse direction shifts from output DL2[3] to output DL2[0], and then from output DL1[3] to output DL1[0]. This is different from... Figure 4B Step S5 is different (not shown).

[0080] Therefore, the judgment will inevitably be made in Figure 3A and Figure 3B The timing of the enable comparator output signal CMP1 is shown before or after half the duty cycle of the first cycle T1. In other words, in this embodiment, the resolution of CADC is increased by an extra bit.

[0081] exist Figure 5 In another embodiment illustrated, the second multiplexer 234 is coupled between the second delay line 235 and the first multiplexer 231, and the second delay line circuit 235 is coupled between the re-trigger circuit 240 and the second multiplexer 234. In this embodiment, when the base clock CLKB transitions again to a logic high detected by the edge detector 241 (similar to...), Figure 4B In step S5), the source 242 triggers the second delay line 235 to enable the second buffer to sequentially generate output DL2[3] to output DL2[0]. Then, the second buffer corresponding to the output DL2[0] is selected by the second multiplexer 234 as the output of the second delay line 235 with a fixed input, so that the second delay data DL2[0] is output to the first delay line 232 via the first multiplexer 231.

[0082] Figure 6A flowchart illustrating a local counting method according to one of the exemplary embodiments of the present disclosure is shown. The column analog-to-digital converter (ADC) comprises multiple ADCs connected in parallel with each other. The local counting method for each ADC is shown below. In step S610, each ADC compares a ramp voltage with one of the column signals to generate a comparator output signal. Next, in step S620, each ADC triggers its delay line circuitry based on the comparator output signal to generate first delayed data. In step S630, each ADC re-triggers the delay line circuitry based on a base clock to generate first re-trigger delayed data. Next, in step S640, each ADC compares the first delayed data with the first re-trigger delayed data to generate a first count output.

[0083] Based on the above, in an embodiment of the present invention, in order to solve the frequency limitation caused by timing violations and long wires and reduce system complexity, an embodiment of the present invention provides a column analog-to-digital converter (CADC) with a local counting method, which can perform local counting by comparing the triggering result and re-triggering result of the local delay line circuit, so as to improve the counting resolution and perform self-compensation without correction circuitry.

[0084] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from its scope or spirit. In view of the foregoing, it is intended that this invention cover modifications and variations thereof, provided that such modifications and variations are within the scope of the appended claims and their equivalents.

Claims

1. A column analog-to-digital converter (ADC) comprising a plurality of ADCs connected in parallel with each other, wherein each of the plurality of ADCs comprises: A comparator configured to compare a ramp voltage with one of a plurality of column signals to produce a comparator output signal; as well as A counting circuit is configured to trigger a delay line circuit of the counting circuit according to the comparator output signal to generate a plurality of first delayed data, to further trigger the delay line circuit according to a base clock to generate a plurality of first re-trigger delayed data, and to compare the plurality of first delayed data with the plurality of first re-trigger delayed data to generate a first count output. The delay line circuit includes: A first multiplexer is configured to receive the comparator output signal and the second delayed data, and to select outputting the comparator output signal during a first period and to select outputting the second delayed data during a third period. A first delay line, coupled to the first multiplexer, includes a plurality of first buffers connected in series, configured to sequentially delay the comparator output signal during the first period to generate the first delayed data, and sequentially delay the second delayed data during the third period to generate the first re-trigger delayed data. Data storage circuitry, coupled to the first delay line; and The second multiplexer and the second delay line are coupled to the first multiplexer.

2. The column analog-to-digital converter of claim 1, wherein the counting circuit further counts the base clock based on the comparator output signal to generate a second counting output, and combines the first counting output with the second counting output to generate a counting output.

3. The column analog-to-digital converter according to claim 1, further comprising: A digital-to-analog converter configured to generate the ramp voltage; as well as The readout amplifier is configured to receive a count output generated by each of the plurality of analog-to-digital converters to produce an output.

4. The column analog-to-digital converter according to claim 1, wherein the counting circuit comprises: The main counting circuit is configured to count the base clock before the comparator output signal is enabled to generate a second counting output. A local counting circuit is configured to, after being enabled by the comparator output signal, trigger the delay line circuit according to the comparator output signal to generate the first delay data, trigger the delay line circuit again according to the base clock to generate the first re-trigger delay data, and compare the first delay data with the first re-trigger delay data to generate a first counting output.

5. The column analog-to-digital converter according to claim 4, wherein the local counting circuit comprises: The delay line circuit is configured to be triggered during the first cycle of the base clock according to the comparator output signal to generate the first delay data; A re-trigger circuit, coupled to the delay line circuit, is configured to output a re-trigger signal to the delay line circuit according to the base clock during a second cycle, and to re-trigger the delay line circuit according to the re-trigger signal during a third cycle to generate the first re-trigger delay data, wherein the second cycle is later than the first cycle, and the third cycle is later than the second cycle. as well as A determination circuit, coupled to the delay line circuit, is configured to compare the first delay data with the first re-trigger delay data to generate the first count output.

6. The column analog-to-digital converter according to claim 5, wherein The data storage circuit, coupled between the first delay line and the judgment circuit, is configured to store the first delay data according to the delay line data latch signal during the second period. The second delay line includes multiple second buffers connected in series with each other. During the second period, the first buffer and the second buffer corresponding to the non-inverted first delay data are disabled according to the re-trigger signal. During the third cycle, the second buffer generates the second delay data based on the re-trigger signal and the base clock, and the first buffer sequentially delays the second delay data to generate the first re-trigger delay data.

7. The column analog-to-digital converter of claim 6, wherein the second multiplexer is coupled between the re-trigger circuit and the second delay line, or coupled between the second delay line and the first multiplexer.

8. The column analog-to-digital converter of claim 5, wherein the re-trigger circuit comprises: An edge detector is configured to receive the base clock and detect the transition of the base clock to generate a delay line data latch signal at the start of the second cycle. as well as A re-trigger source, coupled to the edge detector, is configured to perform a step transformation on the delay line data latch signal during the second period to generate the re-trigger signal.

9. The column analog-to-digital converter according to claim 5, wherein the determining circuit further determines whether the undisabled first delay data is the same as the undisabled first re-trigger delay data to generate the first counting output.

10. The column analog-to-digital converter according to claim 5, wherein the determining circuit further determines whether the starting data of the first delayed data is the same as the starting data of the first re-trigger delayed data to generate the first counting output.

11. A local counting method applicable to a column analog-to-digital converter comprising multiple analog-to-digital converters connected in parallel with each other, wherein the local counting method includes: The ramp voltage is compared with one of multiple column signals to produce a comparator output signal; The delay line circuit of each of the plurality of analog-to-digital converters is triggered according to the comparator output signal to generate a plurality of first delayed data; The delay line circuit is retriggered according to the base clock to generate multiple first retriggered delay data; The plurality of first delay data are compared with the plurality of first re-trigger delay data to generate a first count output, wherein During the first cycle, the comparator output signal is selected to be output, and the comparator output signal is sequentially delayed to generate the first delayed data; as well as During the third cycle, the second delayed data is selected to be output, and the second delayed data is sequentially delayed to generate the first re-trigger delayed data.

12. The local counting method according to claim 11, further comprising: The base clock is counted based on the comparator output signal to generate a second count output; as well as The first count output and the second count output are combined to generate a count output.

13. The local counting method of claim 11, wherein the step of comparing the ramp voltage with one of a plurality of column signals to generate a comparator output signal comprises: The ramp voltage is generated; as well as Receive the count output generated by each of the plurality of analog-to-digital converters to generate an output.

14. The local counting method according to claim 11, further comprising: The comparator output signal triggers the delay line circuit during the first cycle of the base clock to generate the first delay data; During the second cycle, a re-trigger signal is output to the delay line circuit according to the base clock, and during the third cycle, the delay line circuit is re-triggered according to the re-trigger signal to generate the first re-trigger delay data, wherein the second cycle is later than the first cycle, and the third cycle is later than the second cycle; as well as The first delay data is compared with the first re-trigger delay data to generate the first count output.

15. The local counting method according to claim 14, wherein During the second cycle, the first delayed data is stored according to the delay line data latch signal, and the buffer corresponding to the non-inverted first delayed data is disabled according to the re-trigger signal; and During the third cycle, the second delay data is generated based on the re-trigger signal and the base clock.

16. The local counting method according to claim 14, further comprising: At the beginning of the second cycle, the state transition of the base clock is detected to generate a delay line data latch signal; as well as During the second cycle, a step transformation is performed on the delay line data latch signal to generate the re-trigger signal.

17. The local counting method of claim 14, wherein the step of comparing the first delay data with the first re-trigger delay data to generate the first counting output further comprises: Determine whether the first delay data that is not disabled is the same as the first re-trigger delay data that is not disabled in order to generate the first count output.

18. The local counting method of claim 14, wherein the step of comparing the first delay data with the first re-trigger delay data to generate the first counting output further comprises: Determine whether the starting data of the first delay data is the same as the starting data of the first re-trigger delay data to generate the first count output.

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