Detection of intensity modulated optical signals by low bandwidth receiving equipment

Abstract

A method for detecting an intensity modulated optical signal by a low bandwidth receiving device comprises: a processor receives the intensity modulated optical signal. A first multi-level detection of M levels is performed on the intensity modulated optical signal, wherein M>1. In addition, a second multi-level detection of N levels is performed on the intensity modulated optical signal, wherein N>M. The detected M-level signal is converted into an expected N-level signal. An error in the detected M-level signal is detected based on a comparison between the expected N-level signal and the detected N-level signal. Based on the detected error, the detected M-level signal is corrected.

Description

Technical Field

[0001] The present disclosure relates generally to the field of optical communications, and more particularly to methods and apparatus for detecting intensity modulated optical signals by a low bandwidth receiving device. Background Art

[0002] Existing telecommunication infrastructure deploys various types of optical networks, such as from long-haul core networks to edge / regional / metropolitan areas and even short-haul transmission systems (such as access networks). However, due to the increasing demand for bandwidth, such infrastructure is under great pressure to upgrade transmission capacity and bandwidth in an economical and efficient manner. Currently, the cost of optical components for 10Gb / s data rates is very high compared to the optical components used in gigabit passive optical networks (GPON) (2.5Gb / s), especially the cost of optical components for 25Gb / s and 50Gb / s data rates. Specifically, optical network unit (ONU) receivers are based on avalanche photodiodes (APDs) mainly used in access networks, so they cannot be expected to have economies of scale that other applications have. In addition, ONU receivers need to detect the complete signal, so they can only be commercially attractive if they have very low costs. In order to reduce the cost of optical transceivers, lower bandwidth components (such as low-bandwidth receivers) can be used to help achieve smooth interoperability of several bit rates.

[0003] Currently, one of the main challenges that arise in optical communications is the correct detection of intensity modulated signals (such as non-return to zero (NRZ) signals) using low-bandwidth receivers. When using low-bandwidth optical receivers to detect NRZ signals, if the photodiode bandwidth is low (<0.5*bit rate), multiple levels appear in the electrical signal. If the bandwidth is large enough (>0.3*bit rate), the signal can still be recovered based on a single threshold using traditional two-level detection. However, at high bit rates (such as 50Gb / s), dispersion can cause a penalty of more than 1dB. Dispersion further causes intersymbol interference (ISI), which can be seen as a multi-level signal (such as a 1-bit memory system).

[0004] At present, some attempts have been made to detect intensity modulated signals by low bandwidth receivers and simple electronic processing to compensate for errors, while the transmitter can optionally have a precoder. However, the traditional methods and systems for such detection require precoders that limit interoperability and inherently reduce the sensitivity of the receiver, require a very power-consuming digital signal processor, and reduce the gain of lower frequencies when compensating for the frequencies of higher data rates. For example, in some traditional methods (such as electrical dual binary detection), a precoder is used in the transmitter to detect three levels when transmitting NRZ signals. However, the disadvantage is that it requires a precoder, which may limit interoperability, and the receiver sensitivity is inherently reduced. In another example, some traditional methods can be used, such as complex digital signal processing (digital signal processing, DSP) technology, such as maximum likelihood sequence estimation (maximum likelihood sequence estimation, MLSE) or decision feedback equalization (decision feedback equalizer, DFE). However, the main disadvantage of this method is that it requires a very power-consuming DSP, and the calculation of coefficients may cause problems. In yet another example, some traditional methods (e.g., continuous time linear equalization (CTLE)) can be used after the receiver to enhance high frequencies. While this may be useful for 10Gb / s data rates, it may not be the case for 25Gb / s or 50Gb / s because the frequencies to be compensated are very high, and therefore, the gain at lower frequencies is reduced.

[0005] Therefore, in light of the foregoing discussion, there exists a need to overcome the shortcomings associated with conventional dispersion estimation and compensation techniques. Summary of the invention

[0006] The present disclosure seeks to provide a method, apparatus, and computer program product for detecting intensity modulated optical signals by a low bandwidth receiver. The present disclosure seeks to provide a solution to the existing detection problem, which requires a precoder that limits interoperability and inherently reduces receiver sensitivity, requires a power-consuming digital signal processor, and reduces the gain of lower frequencies while compensating for frequencies with higher data rates. The purpose of the present disclosure is to provide a solution that at least partially overcomes the problems encountered in the prior art and provides an improved method and apparatus that is capable of detecting intensity modulated signals and compensating for errors using a low bandwidth receiver, while the transmitter can optionally have a precoder. Therefore, the improved method and apparatus minimizes complexity to avoid high cost and high power consumption, and can operate with several transmitters from different vendors, thereby limiting the use of precoding technology.

[0007] The objects of the present disclosure are achieved by what is presented in the attached independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

[0008] In one aspect, the present disclosure provides a computer-implemented method for detecting an intensity modulated optical signal at a receiving device. The method includes a processor receiving an input optical signal. The method also includes the processor performing a first multi-level detection of M levels on the input signal, where M>1. The method also includes the processor performing a second multi-level detection of N levels on the input signal, where N>M. The method also includes the processor converting the detected M-level signal into an expected N-level signal. The method also includes the processor detecting an error in the detected M-level signal based on a comparison of the expected N-level signal and the detected N-level signal. The method also includes the processor correcting the detected M-level signal based on the detected error.

[0009] The method enables accurate detection of intensity modulated optical signals by low bandwidth receiving devices. The method is based on the simultaneous detection of two and more levels and electronically combining the decision process to detect and correct errors of traditional detection (such as 2 levels) with values ​​of multi-level detection (such as >2 levels). The method implements simple electronic processing to compensate for errors, while the transmitter can optionally have a precoder. Therefore, the method is very simple to implement digitally. The only computational element is the element that provides the level threshold. In one embodiment, a simple feed-forward equalizer (FFE) filter can also be implemented to improve performance. In addition, it is shown that it is not limited by a single value of the receiver bandwidth and the performance is even better than that of electrical dual binary detection.

[0010] Furthermore, the method can be implemented with low complexity and computational load since only logic gates and slicers are used, thereby avoiding an analog to digital converter (ADC). Therefore, the processing is simple and can be done with logic gates.

[0011] In one implementation, the input optical signal includes a string of symbols.

[0012] The use of symbol strings enables more precise detection and correction of bit errors.

[0013] In another implementation, the symbol string is a binary string or an amplitude modulated string having multiple levels.

[0014] The disclosed method is applicable to both analog signals and digital signals. Therefore, the input optical signal includes a symbol string, such as a binary string or an amplitude modulated string with multiple levels. In one example, the symbol string can be a sequence of "0" and "1", such as 111000110001. In another example, the symbol string can correspond to an amplitude modulated string with multiple levels.

[0015] In another implementation, the transforming includes generating a sum of the current symbol and the immediately previous symbol.

[0016] The sum of the current symbol and the immediately previous symbol results in a high transition, making error detection and correction more precise.

[0017] In another implementation, detecting an error in the detected M-level signal includes detecting a discrepancy between an expected N-level signal and a detected N-level signal for two consecutive symbols.

[0018] Based on the comparison of the expected N-level signal with the detected N-level signal, the inconsistency between the expected N-level signal and the detected N-level signal is detected. Due to the addition of consecutive bits (adding one bit in the current symbol and the past symbol), one error in the M-level detection is converted into two consecutive errors in the N-level detection. Based on this information, consecutive error symbols are searched for error correction.

[0019] In another implementation, the comparison of the expected N-level signal with the detected N-level signal includes further converting the expected N-level signal and the detected N-level signal according to a double symbol delay.

[0020] Before an error is detected, the comparison provides a signal difference. When the expected N-level signal is compared (or XORed) with the detected N-level signal, this comparison enables the bit position of the erroneous bit to be identified.

[0021] In another implementation, M=2.

[0022] Since the value of M is 2, conventional clock and data recovery (CDR) can be used for 2-level signals. When the value of M is higher, the power penalty will increase significantly, thereby reducing system performance.

[0023] In another implementation, N=2M-1.

[0024] The value of N is based on the value of M, which indicates a higher level signal that can be used to correct any errors in the M-level signal.

[0025] In another implementation, receiving includes receiving the input optical signal using a photodiode, wherein the photodiode is limited in bandwidth.

[0026] Several bit rates can be detected using a single PD and can be extended to higher bit rates. In addition, the receiver sensitivity is limited compared to a full bandwidth receiver.

[0027] In another implementation, receiving further includes applying an electrical filter to the input optical signal.

[0028] This method facilitates several enhancements, such as using a specific filter for each level detector in the case of using an ADC. To detect M levels, a simple electrical filter (or equalizer) can be added. To separate the N levels to make the N levels more distinct, another electrical filter (or equalizer) can be added.

[0029] In another implementation, performing the second multi-level detection includes applying a low pass filter for separating the N levels.

[0030] The low pass filter is used to improve the detection and separation of the multiple levels of the input optical signal.

[0031] In another implementation, the method further includes applying a technique to compensate for low bandwidth to detect the M levels.

[0032] The disclosed method applies to a range of bandwidths rather than a single value of bandwidth.

[0033] On the other hand, the present disclosure provides a receiving device for detecting an intensity modulated optical signal. The receiving device includes a control circuit for receiving an input optical signal. The control circuit is also used to perform a first multi-level detection of M levels on the input signal, where M>1. The control circuit is also used to perform a second multi-level detection of N levels on the input signal, where N>M. The control circuit is also used to convert the detected M-level signal into an expected N-level signal. The control circuit is also used to detect an error in the detected M-level signal based on a comparison of the expected N-level signal and the detected N-level signal. The control circuit is also used to correct the detected M-level signal based on the detected error.

[0034] In another implementation, the control circuit is configured to perform the features of the implementation of the method according to the first aspect. Therefore, the implementation of the receiving device includes the features of the corresponding implementation of the method of the first aspect.

[0035] The receiving device achieves all the advantages and effects of the method of the first aspect.

[0036] In yet another aspect, the present disclosure provides a computer program product comprising a non-transitory computer-readable storage medium having computer-readable instructions stored therein, the computer-readable instructions being executable by a computerized device comprising processing hardware to perform the method of the first aspect.

[0037] The computer program product of the third aspect achieves all the advantages and effects of the method of the first aspect.

[0038] It should be noted that all devices, elements, circuits, units and modules described in this application can be implemented by software or hardware elements or any type of combination thereof. All steps performed by various entities described in this application and the described functions to be performed by various entities are intended to indicate that the corresponding entities are used to perform the corresponding steps and functions. Although in the description of the following specific embodiments, the specific functions or steps performed by the external entity are not reflected in the description of the specific detailed elements of the execution of the specific steps or functions of the entity, it should be clear to the technician that these methods and functions can be implemented by corresponding hardware or software elements or any combination thereof. It should be understood that, without departing from the scope of the present disclosure defined in the appended claims, various combinations of features of the present disclosure can be performed.

[0039] Additional aspects, advantages, features and objects of the present disclosure will become apparent from the accompanying drawings and detailed description of illustrative implementations which is interpreted in conjunction with the following appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above summary and the detailed description of the following illustrative embodiments may be better understood by reading in conjunction with the accompanying drawings. In order to illustrate the present disclosure, exemplary structures of the present disclosure are shown in the accompanying drawings. However, the present disclosure is not limited to the specific methods and tools disclosed herein. In addition, it should be understood by those skilled in the art that the accompanying drawings are not drawn to scale. Where possible, the same elements are represented by the same numbers.

[0041] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following drawings.

[0042] Figure 1 is a flowchart of a method for detecting an intensity modulated optical signal by a receiving device according to an embodiment of the present disclosure.

[0043] Figure 2A A network environment of a system having a transmitting device and a receiving device according to an embodiment of the present disclosure.

[0044] Figure 2B is a first block diagram of various exemplary components of a receiving device according to an embodiment of the present disclosure.

[0045] Figure 2Cis a second block diagram of various exemplary components of a receiving device according to an embodiment of the present disclosure.

[0046] Figure 3A is an illustration of a first eye diagram of an NRZ signal at a high bandwidth optical front end according to an embodiment of the present disclosure.

[0047] Figure 3B is an illustration of a second eye diagram of an NRZ signal at a low bandwidth optical front end according to an embodiment of the present disclosure.

[0048] Figure 3C is a diagram of sampling instants and a threshold provided by a middle level slicer according to an embodiment of the present disclosure.

[0049] Figure 3D is a diagram of sampling instants and two thresholds provided by an upper level slicer and a lower level slicer according to an embodiment of the present disclosure.

[0050] Figure 4A is a network environment of a first exemplary system for detecting an intensity modulated optical signal according to an embodiment of the present disclosure.

[0051] Figure 4B is a detailed diagram of various components in a processor according to an embodiment of the present disclosure.

[0052] Figure 4C is a network environment of a second exemplary system for detecting an intensity modulated optical signal according to another embodiment of the present disclosure.

[0053] Figure 5A and Figure 5B is a graphical representation of comparison results of measurements of different target bit error rates (BER) in an exemplary system for detecting intensity modulated optical signals according to an embodiment of the present disclosure.

[0054] Figure 5C and Figure 5D is a graphical representation of comparison results of measurements of BER versus received optical power (RoP) for B2B and 20 km transmission for different detection techniques according to an embodiment of the present disclosure.

[0055] In the drawings, an underlined number is used to indicate the item in which the underlined number is located or an item adjacent to the underlined number. A non-underlined number refers to the item identified by the line connecting the non-underlined number to the item. When a number is not underlined and has an associated arrow, the non-underlined number is used to identify the general item to which the arrow points. DETAILED DESCRIPTION

[0056] The following detailed description describes embodiments of the present disclosure and ways in which these embodiments can be implemented. Although some modes of implementing the present disclosure have been disclosed, those skilled in the art will recognize that there may be other embodiments for implementing or practicing the present disclosure.

[0057] Figure 1 1 is a flow chart of a method 100 for detecting an intensity modulated optical signal by a receiving device according to an embodiment of the present disclosure. Figure 2A , Figure 2C , Figure 4A , Figure 4B and Figure 4C The method 100 includes steps 102, 104, 106, 108, 110, 112 and 114.

[0058] At step 102, method 100 includes a processor receiving an input optical signal. The received input optical signal is detected by a processor at a receiving device. The optical signal is sent by a remotely located transmitting device. In one example, data (in the form of an optical signal) can be transmitted between two remotely located points (e.g., a data center) (e.g., a transmitting device and a receiving device in a metropolitan area network) via an optical link.

[0059] According to one embodiment, receiving includes receiving an input optical signal using a photodiode that is limited in bandwidth at an optical front end of a receiving device. The photodiode converts an optical field in the input optical signal into an electrical current. According to another embodiment, receiving includes applying an electrical filter to the input optical signal. The electrical filter has a cutoff frequency and outputs a filtered signal corresponding to the electrical signal received from the photodiode.

[0060] It should be noted that according to method 100, the receiving device corresponds to a low-bandwidth optical receiving device, which has low cost and can operate at a much lower power level than the optical input power of a high-speed receiving device, because the noise power decreases as the bandwidth of the optical receiving device decreases.

[0061] The input optical signal includes a symbol string, which may be one of a binary string or an amplitude modulated string having multiple levels. For example, the input optical signal may have a multi-level amplitude modulation format, where multiple bits are represented by a given signal level (e.g., x[n]) within a given clock cycle of the optical signal.

[0062] At step 104, method 100 further includes performing a first multi-level detection of M levels on the input optical signal, where M>1. According to one embodiment, M represents a number corresponding to the number of possible conditions, levels, or combinations of a given number of binary variables. For example, a digital optical signal with four possible conditions (voltage level, frequency, phase, etc.) is an M-ary system with M=4. If there are 8 possible conditions, then M=8, and so on. The number of bits required to generate a given number of conditions can be mathematically represented as 2 n = M, where n = the number of bits required and M = the number of possible conditions, levels or combinations for n bits. For example, for 1 bit, there are only 2 possible 1 = 2 conditions. For 2 bits, there may be 2 2 = 4 conditions, for 3 bits, there may be 2 3 = 8 conditions, and so on. In one illustrative embodiment, if Figure 3A As described in , a two-level signal is detected within a given clock cycle of an input optical signal of a high bandwidth optical front end.

[0063] According to one embodiment, the processor in the receiving device may include an intermediate level slicer that provides a threshold value (e.g., "Th0"). With respect to the threshold value, e.g., "Th0", two levels (or states) of the input optical signal are detected, such as Figure 3C In addition, Figure 3C An example of a sampling instant enclosed between two vertical dashed lines is also shown in FIG. In one example, for a given input optical signal x[n], the two levels detected can be expressed as It should be noted that Figure 3C An example of a preferred sampling instant corresponding to two samples per bit is shown, however, a single sampling instant for such detection, ie, 1 sample per bit, may also be employed.

[0064] In step 106, the method 100 further includes the processor performing a second multi-level detection of N levels on the input optical signal, wherein N>M. It should be noted that the method 100 performs steps 104 and 106 simultaneously. Alternatively, the method 100 detects an M-level signal and an N-level signal simultaneously, wherein the latter may be offset by about half a bit from the decision time of the former. According to one embodiment, based on the first multi-level detection of M levels, N represents a number corresponding to the number of possible conditions, levels or combinations of a given number of binary variables. Mathematically, the second multi-level detection of N levels can be represented as 2M-1 levels. For example, a digital optical signal with two possible conditions (voltage level, frequency, phase, etc.) is an M-ary system with M=2. Therefore, the second multi-level detection can be determined as (2*2)-1 levels, i.e., 3 levels.

[0065] like Figure 3B As shown, a three-level signal is detected within a given clock cycle of an input optical signal of a low-bandwidth optical front end. However, it should be understood that the use of two levels and three levels in the illustrative embodiments is only by way of example, and more levels can be used so that a given level represents more than two bits within a given cycle of the signal. The number of levels to be detected can grow to (p*n-1), where p is the initial modulation order (e.g., p=2 for NRZ, p=4 for PAM4), and n starts at 1 for full bandwidth. It should be noted that for better performance, the value of n can be limited to 2, but without departing from the scope of the present disclosure, this limitation depends on the bandwidth of the receiving device.

[0066] According to one embodiment, the processor in the receiving device may include two level slicers, such as a high slicer and a low slicer, which respectively provide two thresholds, such as "Th1" and "Th2". With respect to the two thresholds, such as "Th1" and "Th2", three levels (or states) of the input optical signal are determined, such as Figure 3D In addition, Figure 3D An example of sampling instants enclosed between two vertical dashed lines is also shown in FIG. For a given input optical signal x[n], the detected three levels can be expressed as Because the three-level is the addition of the detected continuous two-level signals.

[0067] According to one embodiment, the second multi-level detection performed at N levels may include applying a low pass filter for separating the N levels.

[0068] At step 108, the method 100 further includes the processor converting the detected M-level signal into the expected N-level signal. According to one embodiment, the detected two-level signal can be converted into the expected three-level signal. By using a one-bit delay encoding technique, the detected two-level signal is converted into a three-level signal by delaying and adding (1+D). Therefore, for a given received optical signal x[n], if the detected two-level signal is Then the expected three-level signal can be expressed as The detected two-level signal is converted into a three-level signal by delaying and adding (1+D). For example, for a given input optical signal x[n]=110001110011, if the detected two-level The expected three-level A bit as shown below is "0", indicating As a result of the delay and add operation, an error bit in the expected three-level Two consecutive error bits are generated in the , namely "11" as shown by the underline.

[0069] In another embodiment, for a given input optical signal x[n]=110001110011, if the two-level signal is detected to be The expected three-level signal is The detected three-level signal is It can be observed that the detected two-level signal The two consecutive errors in the signal are both "0" bits as shown below. The detected two-level signal (i.e. 110001 00 0011) will result in two consecutive errors when converted to a three-level signal (i.e. 121001 100 012), it will result in three consecutive errors.

[0070] In yet another embodiment, for a given input optical signal x[n]=110001110011, if the detected two-level signal is The expected three-level signal is The detected three-level signal is It can be observed that the two consecutive errors in the detected two-level signal are different, namely "1" and "0". 10 110011), the two errors in the conversion to a three-level signal (i.e., 1210 1 1 1 21012), two non-continuous errors will result as shown by the underline. According to such an embodiment, the method 100 also includes converting the expected N-level signal, such as the expected three-level signal, based on the two symbol delays. and the detected N-level signal, for example, the detected three-level signal

[0071] At step 110, the method 100 further includes the processor comparing the expected N-level signal with the detected N-level signal. According to one embodiment, the expected three-level signal (i.e., ) and the detected three-level signal (i.e. ) for comparison. The processor can provide a bit sequence of "0" and "1" bits as the result of the comparison, where the "1" bit corresponds to the expected three-level signal (i.e. ) relative to the detected three-level signal (i.e. ) error bit.

[0072] At step 112, method 100 further includes the processor detecting an error in the detected M-level signal based on a comparison of the expected N-level signal and the detected N-level signal. According to one embodiment, the inconsistency between the expected N-level signal and the detected N-level signal for two consecutive symbols is detected. As shown in step 110, based on the comparison, a "1" corresponds to the expected three-level signal (i.e., ) relative to the detected three-level signal (i.e. ) is an error bit. The number of "1" bits in the bit sequence corresponds to the expected three-level signal (i.e. ), which in turn indicates the number of error bits in the detected two-level signal (i.e. ) is the number of error bits in .

[0073] At step 114, method 100 also includes the processor correcting the detected M-level signal based on the detected error. According to one embodiment, as described in step 110, a single error detected in the detected two-level signal results in two errors in the expected three-level signal because the error bit is counted in the current decision bit and the next (i.e., previous) decision bit. Therefore, if the conditions y[n]+y[n-1]≠z[n] and y[n-1]+y[n-2]≠z[n-1] are met, then y[n-1] is a detected error. This detected error can be corrected based on the negation of the bit value. Refer to the above An example that satisfies the condition and but is the error bit. Therefore, The bit "0" in (as shown by the underline) is negated, i.e., converted to "1". Thus, the error is corrected.

[0074] In another embodiment, as described in step 110, there may be a situation where two consecutive errors detected in the detected two-level detection signal lead to further errors in the expected three-level signal based on the bit memory. Therefore, when the conditions y[n]-y[n-2]≠z[n]-z[n-1] and y[n-1]-y[n-3]≠z[n-1]-z[n-2] are met, y[n-1] is a detected error. This detected error can be corrected based on the negation of the bit value. Referring again to the above example, if the condition is met and but is the error bit. Therefore, The bit "00" in (as shown by the underline) is negated, i.e., converted to "11". Thus, the error is corrected.

[0075] According to one embodiment, method 100 also includes a processor applying a technique to compensate for low bandwidth to detect M levels. This technique takes into account the correlation between consecutive bits. By sampling at different points from the middle of the eye diagram and using different thresholds or slicers, the current bit and the sum of the current bit and the previous bit are determined. Thereafter, errors occurring in the current bit (due to eye closure caused by the limited bandwidth of the receiving device or the n-bit delay channel) are corrected by decoding the relationship between the detected levels. In order to detect M levels, a simple electrical filter (or equalizer) can be added as a technique. In order to separate the N levels to make the N levels more obvious, another electrical filter (or equalizer) can be added.

[0076] Steps 102, 104, 106, 108, 110, 112, and 114 are merely illustrative, and other alternatives may be provided in which one or more steps are added, one or more steps are deleted, or one or more steps are provided in a different order without departing from the scope of the claims herein.

[0077] Figure 2A 2 is a network environment of a system 200 having a transmitting device and a receiving device according to an embodiment of the present disclosure. Figure 2A , shows a network environment of a system 200 including a transmitting device 202 and a receiving device 204. Also shown is an optical link 206 between the transmitting device 202 and the receiving device 204. The receiving device 204 is communicatively coupled to the transmitting device 202 via the optical link 206.

[0078] The transmitting device 202 comprises suitable logic, circuitry, interfaces and / or code that may be operable to transmit information in the form of optical signals to the receiving device 204 via the optical link 206. Examples of the transmitting device 202 include, but are not limited to, an optical transmitter, a transceiver, or a fiber optic transmitter.

[0079] The receiving device 204 may comprise suitable logic, circuitry, interfaces and / or code that may be operable to receive an optical signal (as an input optical signal) via the optical link 206 and convert the optical signal into an electrical signal. Examples of the receiving device 204 include, but are not limited to, an optical receiver, a transceiver, or a fiber optic receiver.

[0080] Optical link 206 is a communication link comprising a single end-to-end optical circuit that provides a data connection medium between two points. Examples of optical link 206 include, but are not limited to, optical fiber (e.g., multimode fiber, single-mode fiber, or plastic fiber) or active optical cable (AOC) or full-duplex optical link.

[0081] In operation, the transmitting device 202 is used to transmit input data in the form of optical signals to the receiving device 204 via the optical link 206. Typically, the input data in the digital domain (representing an electrical signal) is converted to an analog signal (e.g., using a digital-to-analog converter) and modulated (e.g., modulated into a carrier) to propagate as an intensity modulated signal via the optical link 206. The system 200 including the transmitting device 202 and the receiving device 204 is suitable for using any type of modulation (e.g., WDM, O-OFDM, SDM, etc.).

[0082] According to one embodiment, the receiving device 204 is used to receive an input optical signal, such as an intensity modulated signal, via the optical link 206. The receiving device 204 receives this intensity modulated signal at a low bandwidth front end and detects various levels simultaneously by using different thresholds. The receiving device 204 can also determine the current bit of the intensity modulated signal and the sum of the current bit and the previous bit based on sampling performed at a point different from the middle of the eye diagram of the intensity modulated signal. Then, electronic signal processing performed by one or more processors of the receiving device 204 can combine the detected intensity modulated signals to eliminate correlation between consecutive bits. The one or more processors use a traditional two-level signal (based on Figure 3C A threshold value shown) and a three-level signal (according to Figure 3D For example, if y[n] is the currently detected two-level signal and z[n] is the currently detected three-level signal, then according to the following formula, the mathematical relationship between y[n] and z[n] is:

[0083] z[n]=y[n]+y[n-1]

[0084] Therefore, the one or more processors detect errors by adding the current decision bit to the previous bit and comparing it with the value obtained from the three-level signal. Since one error in the two-level signal can cause two errors in the three-level signal because the bit is counted in the current bit and the previous decision bit, the one or more processors detect and correct a single error according to the condition satisfied by the following formula:

[0085] y[n]+y[n-1]≠z[n], and

[0086] y[n-1]+y[n-2]≠z[n-1]

[0087] Once detected, a single error can be corrected by one or more processors by negating the bit value of y[n-1].

[0088] In another embodiment, one or more processors can further detect and correct two consecutive errors, depending on the memory to be used. In this embodiment, one or more processors detect and correct two errors according to the condition satisfied by the following formula:

[0089] y[n]-y[n-2]≠z[n]-z[n-1]

[0090] y[n-1]-y[n-3]≠z[n-1]-z[n-2]

[0091] Once detected, both errors can be corrected by one or more processors by negating the bit values ​​of y[n-1].

[0092] In yet another embodiment, one or more processors may further detect and correct "m" consecutive errors, depending on the memory to be used. In this embodiment, one or more processors detect and correct "m" errors according to the condition satisfied by the following formula:

[0093] y[n]+(-1)^(m-1)*y[nm]=z[n]-z[n-1]+z[n-2]-z[n-3]+…+(-1)^(m-1)*z[nm]

[0094] Once detected, the m errors can be corrected by one or more processors by negating the bit values ​​of y[n-1].

[0095] In this way, electronic signal processing performed by one or more processors of receiving device 204 can decode the relationship between the various detected levels to correct errors that occur in the current bit (due to eye closure caused by the limited bandwidth of receiving device 204 or an n-bit delay channel).

[0096] Figure 2Bis a first block diagram of various exemplary components of a receiving device according to an embodiment of the present disclosure. Figure 2A Component Description Figure 2B . refer to Figure 2B , shows a transmitting device 202, which includes a light source (hereinafter referred to as light source 208), a pseudorandom binary sequence (PRBS) generator 210, a precoder 212, a modulation circuit 214, and a control circuit 216.

[0097] The light source 208 may correspond to a continuous wave optical signal input from a laser source in the transmitting device 202 .

[0098] The PRBS generator 210 may comprise suitable logic, circuitry, interfaces and / or code for generating a serial sequence of a binary test pattern corresponding to an NRZ electrical signal. The binary test pattern may be timed by a clock signal having a specified base frequency. The size of the serial sequence of the binary test pattern may be expressed in terms of symbol 2 k -1 indicates, where k represents the size of a unique data word in the serial sequence. In an exemplary embodiment, PRBS generator 210 may generate 2 15 -1 bit, and the bit rate is 50 Gbps. However, this exemplary embodiment should not be construed as limiting, and other configurations are possible without departing from the scope of the present disclosure.

[0099] The precoder 212 may include appropriate logic, circuits, interfaces and / or codes for encoding NRZ electrical signals. The precoder 212 may be a conventional precoder having a structure including an exclusive OR (XOR) gate and a time delay unit for delaying the output signal of the exclusive OR gate by one data bit. However, it should be noted that the implementation of the precoder 212 is optional, and therefore, it may be omitted from the transmitting device 202 without departing from the scope of the present disclosure.

[0100] The modulation circuit 214 may include appropriate logic, circuitry, interfaces and / or code for modulating the optical intensity of the carrier output from the laser source (not shown). The NRZ electrical signal generated by the PRBS generator 210 may be optionally amplified by a pair of modulator driver amplifiers and output as a drive signal for the modulation circuit 214. Based on the modulator drive signal input to the modulation terminal of the modulation circuit 214, the modulation circuit 214 modulates the optical intensity of the carrier output from the light source 208 and outputs the modulated signal (as an intensity modulated optical signal) for transmission to the receiving device 204 via the optical link 206.

[0101] The control circuit 216 is used to send a signal to the receiving device 204 through the optical link 206. In one implementation, the control circuit 216 can be a general-purpose processor. Examples of the control circuit 216 include, but are not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set computing (RISC) processor, a very long instruction word (VLIW) processor, a central processing unit (CPU), a state machine, a data processing unit, and other processors or circuits. In addition, the control circuit 216 can refer to one or more separate processors, processing devices, or processing units as part of a machine. It should be understood that the operations performed at the sending device 202 may be performed by the control circuit 216 of the sending device 202.

[0102] Figure 2C is a second block diagram of various exemplary components of a receiving device according to an embodiment of the present disclosure. Figure 2A Component Description Figure 2C . refer to Figure 2C , shows a receiving device 204 , which includes a photodiode (PD) 218 ​​, a transimpedance amplifier (TIA) 220 , an electrical filter 222 , and a processor 224 .

[0103] PD 218 is a highly sensitive semiconductor photodiode that can be used to receive an intensity modulated optical signal from a transmitting device 202 via an optical link 206. PD 218 utilizes the photoelectric effect of the intensity modulated optical signal and converts it into an electrical signal. According to one embodiment, PD 218 can be an avalanche photodiode (APD), which can amplify a carrier through an avalanche breakdown mechanism. Examples of PD 218 include, but are not limited to, laser rangefinders, long-distance fiber optic communications, and quantum sensing for control algorithms.

[0104] The TIA 220 is a current-to-voltage converter that amplifies the current output of a photodetector (e.g., PD 218) to a usable voltage. The configuration of the TIA 220, such as the gain, bandwidth, input offset current, and input offset voltage of the TIA 220, can be based on the type of PD 218 implemented in the receiving device 204.

[0105] The electrical filter 222 allows electrical signal components below its cut-off frequency to pass through, and can cut off other signal components above the cut-off frequency. The electrical filter 222 can be one of an analog filter or a digital filter. An example of the electrical filter 222 can be a Bessel-Thomson filter type, etc.

[0106] The processor 224 is used to receive the optical signal sent by the sending device 202 through the optical link 206. In one implementation, the processor 224 may be a general-purpose processor. Examples of the processor 224 include, but are not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set computing (RISC) processor, a very long instruction word (VLIW) processor, a central processing unit (CPU), a state machine, a data processing unit, and other processors or circuits. In addition, the processor 224 may refer to one or more separate processors, processing devices, or processing units as part of a machine, such as Figure 4A It should be understood that the operations performed at the receiving device 204 may be performed by the processor 224 of the receiving device 204.

[0107] Figure 3A is an illustration of a first eye diagram of an NRZ signal at a high bandwidth optical front end according to an embodiment of the present disclosure. Figure 3A , shows a first eye diagram 300A of an NRZ electrical signal at a high bandwidth (e.g., 0.75*bit rate) optical front end. In the first eye diagram 300A, the eye amplitude marked by a solid double-sided arrow is significant because the high bandwidth optical front end has sufficient bandwidth.

[0108] Figure 3B is a diagram of a second eye diagram of an NRZ signal at a low bandwidth optical front end according to an embodiment of the present disclosure. Figure 3B , shows a second eye diagram 300B of an NRZ electrical signal at a low bandwidth (e.g., 0.25*bit rate) optical front end, with the eye amplitude decreasing (marked by a solid double-sided arrow) while the crossing point and the area above (marked by a dashed double-sided arrow) increasing.

[0109] Figure 3C is a diagram of sampling instants and a threshold provided by a mid-level slicer according to an embodiment of the present disclosure. Figure 3C, shows a third eye diagram 300C of an NRZ electrical signal, which indicates two levels (or states) such that a single bit of value 0 or 1 is represented within a given clock cycle of the signal. Therefore, within a given clock cycle of the input optical signal of the high bandwidth optical front end, a two-level signal obtained according to a threshold value (e.g., "Th0" provided by the intermediate level slicer) is observed. It should be noted that, as Figure 3C As shown, the sampling instant corresponds to 2 samples per bit, however, a single sampling instant of two-level detection corresponding to 1 sample per bit may also be employed without departing from the scope of the present disclosure.

[0110] Figure 3D is a diagram of sampling instants and two thresholds provided by a high-level slicer and a low-level slicer according to an embodiment of the present disclosure. Figure 3D , a fourth eye diagram 300D of an NRZ electrical signal is shown, which indicates three levels (or states) such that a single bit of values ​​0, 1, and 2 is represented within a given clock cycle of the signal. Therefore, within a given clock cycle of the input optical signal of the low-bandwidth optical front end, a three-level signal obtained according to two thresholds (e.g., "Th1" and "Th2" provided by the high-level slicer and the low-level slicer) is observed. It should be noted that, as Figure 3D As shown, the sampling instant corresponds to 2 samples per bit, however, a single sampling instant of three-level detection corresponding to 1 sample per bit may also be employed without departing from the scope of the present disclosure.

[0111] Figure 4A is a network environment of a first exemplary system for detecting an intensity modulated optical signal according to an embodiment of the present disclosure. Figure 4B is a detailed diagram of various components in the processor 224 according to an embodiment of the present disclosure. Figure 1 , Figure 2C and Figure 4B Component Description Figure 4A . refer to Figure 4A , shows a processor 224 in a receiving device 204, which includes an intermediate level slicer 402, a first bit delay unit 404, a first calculation block 406, a second bit delay unit 408, a high level slicer 410, a low level slicer 412, a second calculation block 414, a third bit delay unit 416, a third calculation block 418, a comparator block 420, an error detection block 422, an error correction block 424 and a decoder 426.

[0112] In operation, as described above, at the transmitting device 202, the PRBS generator 210 generates a serial sequence of binary test patterns corresponding to the NRZ electrical signal. In an exemplary embodiment, the PRBS generator 210 may generate two 15-1 bit, the bit rate is 50Gbps. However, this exemplary embodiment should not be construed as limiting, and other configurations are possible without departing from the scope of the present disclosure. The precoder 212 encodes the NRZ electrical signal and transmits the encoded NRZ electrical signal to the modulation circuit 214. According to one embodiment, the modulation circuit 214 modulates the optical intensity of the carrier output from the light source 208 according to the input received from the precoder 212. According to another embodiment, the modulation circuit 214 modulates the optical intensity of the carrier output from the light source 208 according to the input received from the PRBS generator 210 in the absence of the precoder 212 in the transmitting device 202. The control circuit 216 sends an intensity modulated optical signal (e.g., x[n]) to the receiving device 204 via the optical link 206. In one implementation, the control circuit 216 may be a general-purpose processor.

[0113] At the receiving device 204, the intensity modulated optical signal (e.g., x[n]) is received and processed by the optical front end (i.e., PD 218 and TIA 220) of the receiving device 204. According to an embodiment of the present disclosure, the optical front end of the receiving device 204 may have a low bandwidth (e.g., 0.25*bit rate), so the received intensity modulated optical signal (e.g., x[n]) displays a multi-level signal, such as Figure 3B As shown. PD 218 (e.g., APD) utilizes the photoelectric effect of the intensity modulated optical signal (e.g., x[n]) and converts it into a corresponding electrical signal. The carrier is amplified based on the avalanche breakdown mechanism. Thereafter, TIA 220 amplifies the current output of PD 218 into an amplified voltage signal, which is further transmitted to the intermediate level slicer 402 for two-level detection and the other two slicers (i.e., high level slicer 410, low level slicer 412) for three-level detection.

[0114] The intermediate level slicer 402 provides a threshold value, such as "Th0", based on which two levels (or states) of the intensity modulated optical signal, hereinafter referred to as the input optical signal (eg, x[n]), are detected. Figure 3C As shown, according to the detection of the eye and the cross point in the eye diagram of the voltage signal corresponding to the input optical signal, the intermediate level slicer 402 detects two levels (or states) of the input optical signal. More specifically, in the eye opening in the eye diagram of the voltage signal, the intermediate level slicer 402 detects a binary signal to detect two levels (or states) of the input optical signal, hereinafter referred to as a two-level signal (e.g. ).

[0115] According to one embodiment, when the two-level signal has a single error to be corrected, the first bit delay unit 404 provides a delay to the two-level signal (eg ) provides a delay of one symbol (or one bit delay). Thereafter, the first calculation block 406 converts the detected two-level signal (eg ) into the expected three-level signal (e.g. ). By delaying the two-level signal (delayed by one symbol) generated by the first bit delay unit 404 (eg ) and the two-level signal detected by the intermediate level slicer 402 (eg ) are added to generate the expected three-level signal (eg In one embodiment, the XOR gate can be implemented as an adder to implement the first calculation block 406, such as Figure 4B As shown in the first modification block 406A of the first calculation block 406 in FIG.

[0116] According to another embodiment, when the two-level signal has two consecutive errors to be corrected, the first delay unit 404 provides a delay to the two-level signal (eg ) provides a double symbol delay (or two bit delay). Thereafter, the first calculation block 406 converts the detected two-level signal (eg ) into the expected three-level signal (e.g. ). According to the following relationship, the delayed two-level signal (delayed by two symbols) generated by the first bit delay unit 404 (eg ) and the two-level signal detected by the intermediate level slicer 402 (eg ) is subtracted to generate an expected three-level signal (eg ):

[0117]

[0118] In one embodiment, the XOR gate can be implemented as a subtractor to implement the first calculation block 406, such as Figure 4B As shown in the second modification block 406B of the first calculation block 406 in FIG.

[0119] Meanwhile, the other two slicers, such as the high level slicer 410 and the low level slicer 412, respectively provide two thresholds, such as "Th1" and "Th2", based on which three levels (or states) of the input optical signal (such as x[n]) are detected. Figure 3DAs shown, based on the detection of the eye and the crossing point in the eye diagram of the voltage signal corresponding to the input optical signal, the high level slicer 410 and the low level slicer 412 jointly detect the three levels (or states) of the input optical signal. More specifically, in the eye crossing in the eye diagram of the voltage signal, the high level slicer 410 detects the high-order binary signal, and the low level slicer 412 detects the low-order binary signal. The detected high-order binary signal and the low-order binary signal are added by the XOR gate implemented in the second calculation block 414 to detect the three levels (or states) of the input optical signal, which are hereinafter referred to as the three-level signal (e.g. According to one embodiment, a three-level signal (eg ) can be obtained from a two-level signal The decision time is shifted by about half a bit.

[0120] It should be noted that, generally, since the detected three-level signal is the sum of continuous two-level signals, the detected two-level signal and the three-level signal are related to each other according to the following relationship:

[0121]

[0122] It should be understood that detection of more than three levels may also be performed according to the following relationship:

[0123]

[0124] because So the above relationship can be simplified to:

[0125]

[0126] According to one embodiment, when the two-level signal has two errors to be corrected, an optional set of calculation units may be implemented, e.g. Figure 4A The third bit delay unit 416 and the third calculation block 418 are enclosed in the dashed box. In this embodiment, the third bit delay unit 416 provides a three-level signal (eg ) provides a delay of one symbol (or one bit delay). Thereafter, the third calculation block 418 converts the detected three-level signal (eg ) into a converted three-level signal (e.g. ):

[0127]

[0128] By transforming the delayed three-level signal (delayed by one symbol) (i.e. ) and the detected three-level signal (i.e. ) is subtracted to generate a converted three-level signal (eg In one embodiment, the XOR gate may be implemented as a subtractor to implement the third computation block 418.

[0129] According to one embodiment, when the two-level signal has a single error to be corrected, the comparator block 420 can be used to convert the expected three-level signal (eg ) (generated by the first modification block 406A of the first calculation block 406) and the detected three-level signal (eg ) (generated by the second calculation block 414) is compared. At the comparator block 420, the following relationship must be satisfied to determine the two-level signal (e.g. ) in a single error:

[0130]

[0131] According to another embodiment, when the two-level signal has multiple errors (eg, two errors) to be corrected, the comparator block 420 may be used to convert the expected three-level signal (eg, ) (generated by the second modification block 406B of the first calculation block 406) and the detected three-level signal (eg ) (generated by the third calculation block 418) is compared. At the comparator block 420, the following relationship must be satisfied to determine the two-level signal (e.g. ) in a single error:

[0132]

[0133] According to one embodiment, the XOR gate may be implemented as a comparator to implement the comparator block 420, such as Figure 4B As shown. Therefore, the output of the comparator block 420 may correspond to a series of "0" and "1". It should be noted that two consecutive "1" bits correspond to the expected three-level signal (i.e. or ), which in turn corresponds to the detected two-level signal (i.e. ) in a single error.

[0134] Thereafter, the output of the comparator block 420 is transmitted to the error detection block 422. The error detection block 422 may be implemented based on an AND gate and a bit delay unit, such as Figure 4B As shown. More specifically, the output of the comparator block 420 is directly transmitted to the first terminal of the AND gate. In addition, the output of the comparator block 420 is transmitted to the bit delay unit, which is further connected to the second terminal of the AND gate. Therefore, the error detection block 422 searches for and locates two consecutive errors in the output of the comparator block 420.

[0135] Based on the continuous errors searched and located by the error detection block 422, the error correction block 424 can be used to correct such continuous errors. Generally, the logic gate of the error correction block 424 is an XOR gate that takes the detected two-level signal with an appropriate delay (considering the processing time of the decoder 426) as an input. The output of the error detection block 422 indicates whether the detected bit needs to be corrected, that is, if it is "1", the detected bit is changed, and if it is "0", the detected bit is left. More specifically, according to one embodiment, the output of the error detection block 422 indicates the y[n-1] signal (that is, a two-level signal, such as ) in the error bit. The error correction block 424 can be used to apply a technique to compensate for low bandwidth to detect M levels. According to this technique, based on the delayed input signal received from the second bit delay unit 408 (which represents y[n-1]), a two-level signal with an error bit, such as ) and an input signal received from the error detection block 422 (which represents an error bit in the three-level signal, such as ), the error correction block 424 determines the corrected y[n-1] signal, i.e., a two-level signal, such as The error correction block 424 determines a corrected y[n-1] signal, e.g., by using an XOR gate that substantially negates the error bit in the delayed input signal received from the second bit delay unit 408. Once the corrected y[n-1] signal (e.g. ) is determined by the error correction block 424, the decoder 426 in the receiving device 204 can be used to decode the various signals at the detection level (ie, y[n], for example and y[n-1], for example ) and correct the current two-level signal (e.g. ) due to the limited bandwidth of the receiver or the eye closure caused by the n-bit delay channel.

[0136] According to one embodiment, when a given input optical signal (i.e., x[n]) is not precoded, the error detection block 422 may be used to determine consecutive errors in the signal received from the comparator block 420. Based on the determined consecutive errors, the error correction block 424 may be used to correct the three-level signal, i.e. Once the corrected three-level signal (i.e. ) is determined by the error correction block 424, the decoder 426 in the receiving device 204 can be used to decode the various signals at the detection level (i.e. and ) and correct the current two-level signal (i.e. ) due to the limited bandwidth of the receiver or the eye closure caused by the n-bit delay channel.

[0137] Figure 4C is a network environment of a second exemplary system for detecting an intensity modulated optical signal according to another embodiment of the present disclosure. Figure 1 , Figure 2C , Figure 4A and Figure 4B Component Description Figure 4C . refer to Figure 4C , shows the processor 224 in the receiving device 204, which includes the following Figure 4A In addition to the intermediate level slicer 402, the first bit delay unit 404, the first calculation block 406, the second bit delay unit 408, the high level slicer 410, the low level slicer 412, the second calculation block 414, the third bit delay unit 416, the third calculation block 418, the comparator block 420, the error detection block 422, the error correction block 424 and the decoder 426 described in detail, it also includes electrical filters, such as a first electrical filter 428 and a second electrical filter 430.

[0138] In the case of using an ADC, a first electrical filter 428 is connected between the optical front end of the receiving device 204 and the intermediate level slicer 402. Examples of the first electrical filter 428 may include, but are not limited to, a feedforward equalizer (FFE) and a continuous time linear equalizer (CTLE). The first electrical filter 428 may be an analog filter or a digital filter (or equalizer). The first electrical filter 428 receives an input optical signal (e.g., x[n]) from the optical front end as an amplified voltage signal, passes optical signals with frequencies lower than a selected cutoff frequency, and attenuates signals with frequencies higher than the cutoff frequency. The first electrical filter 428 transmits the filtered optical signal to the intermediate level slicer 402 for further processing.

[0139] Similarly, the second electrical filter 430 is connected between the optical front end of the receiving device 204 and the other two slicers (i.e., the high level slicer 410 and the low level slicer 412). The second electrical filter 430 receives the input optical signal (e.g., x[n]) from the optical front end as an amplified voltage signal and makes the N levels more distinct. Examples of the second electrical filter 430 may include, but are not limited to, an FFE and a low pass filter. The second electrical filter 430 transmits the filtered optical signal to the other two slicers for further processing. Then, the operation of the second exemplary system for detecting and correcting intensity modulated optical signals is similar to that of Figure 4A A first exemplary system is described in .

[0140] Figure 5A and Figure 5Bis a graphical representation of comparison results of measurements of different target BERs in an exemplary system for detecting intensity modulated optical signals according to an embodiment of the present disclosure. Figures 1 to 4C Component Description Figure 5A and Figure 5B . refer to Figure 5A , showing the target BER 10 -3 The graph shows 500A. Similarly, refer to Figure 5B , showing the target BER10 -2 Another graphical representation of 500B. Figure 5A and Figure 5B In each of the FIG. 5B , the X-axis 502A represents the percentage value of bandwidth (BW) / bit rate, and the Y-axis 502B represents the power penalty in dB.

[0141] Figure 5A The graphical representation in Figure 1 shows the percentage of bandwidth / bit rate that is increased to achieve the same SNR or BER performance as the ideal system to compensate for the system degradation, i.e., the power penalty. The penalty is considered for three cases (i.e., two-level, three-level, two-level, and three-level) and for a target BER of 10 -3 Although the best receiver sensitivity is for a full bandwidth receiver, with a combination of two-level and three-level detection (represented by the third line 508), the penalty can be <1 dB in the range of 0.28*Rb to 0.75*Rb. For example, the lower boundary of 50 Gb / s corresponds to 14 GHz BW. Figure 5A As shown, in all considered bandwidths, the three-level detection represented by the first line 504 (for two-level detection) and the second line 506 (for three-level detection) is at most equal to the combination of the two-level detection and the three-level detection represented by the third line 508. However, Figure 5A It is further shown that the performance of detection with more than three levels (e.g., five-level detection represented by fourth line 510 and a combination of three-level detection and five-level detection represented by fifth line 512) is lower due to the smaller eye diagram. However, there can be an improvement when BW<0.2*Rb, limiting the penalty to about 5dB. For example, in the case of a combination of two-level detection and three-level detection and a combination of three-level detection and five-level detection, the penalty is between a three-level receiver and a five-level receiver. At a target BER of 10 -2 of Figure 5B A similar trend can be observed in another graphical representation 500B.

[0142] Figure 5C and Figure 5Dis a graphical representation of the comparison results of the measurements of BER for B2B and 20km transmission versus received optical power (RoP) for different detection techniques according to an embodiment of the present disclosure. The detection technique may correspond to a combination of BER with finite impulse response (FIR) and two-level detection and three-level detection. Reference Figure 5C , a graphical representation 500C of a B2B transmission is shown. Similarly, reference Figure 5D , shows another graphical representation 500D of a 20 km transmission. Figure 5C and 5D In each of the examples, the X-axis 520A represents RoP in dBm and the Y-axis 520B represents BER. Figure 5C As shown, for B2B transmission, the BER of the combination of two-level detection and three-level detection represented by the sixth line 522 is lower than the BERwFIR detection technique represented by the seventh line 524. Figure 5D As shown, for a 20 km transmission, the BER of the combination of two-level detection and three-level detection represented by the sixth line 522 is lower than the BERwFIR detection technique represented by the seventh line 524.

[0143] The embodiments of the present disclosure described above may be modified without departing from the scope of the present disclosure as defined by the appended claims. Expressions such as "including", "combined with", "having", "is", etc. used to describe and claim the present disclosure are intended to be interpreted in a non-exclusive manner, that is, items, components or elements that are not explicitly described are allowed to exist. References to the singular should also be interpreted as being related to the plural. The word "exemplary" used herein means "as an example, instance or illustration". Any embodiment described as "exemplary" is not necessarily interpreted as being more preferred or more advantageous than other embodiments, and / or excluding the combination of features of other embodiments. The word "optionally" used herein means "provided in some embodiments and not provided in other embodiments". It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in combination in a single embodiment. On the contrary, the various features of the present disclosure described in the context of a single embodiment for the sake of brevity may also be provided separately, in any appropriate combination, or suitable for any other described embodiment of the present disclosure.

Claims

1. A method (100) for detecting an intensity modulated optical signal, characterized in that: include: The processor (224) receives an input optical signal via the photodiode (218); The processor (224) performs a first multi-level detection of M levels on the input signal after the input light signal is converted by the photodiode (218), wherein M>1; The processor (224) performs a second multi-level detection of N levels on the input signal, wherein N>M; The processor (224) converts the detected M-level signal into an expected N-level signal; The processor (224) detects an error in the detected M-level signal based on a comparison of the expected N-level signal and the detected N-level signal; The processor (224) corrects the detected M-level signal according to the detected error.

2. The method (100) according to claim 1, characterized in that: The input optical signal includes a string of symbols.

3. The method (100) according to claim 2, characterized in that: The symbol string is a binary string or an amplitude modulated string having a plurality of levels.

4. The method (100) according to claim 2 or 3, characterized in that: Converting the detected M-level signal to the expected N-level signal includes generating a sum of a current symbol and an immediately previous symbol.

5. The method (100) according to claim 2 or 3, characterized in that: The detecting an error in the detected M-level signal includes detecting a discrepancy between the expected N-level signal and the detected N-level signal of two consecutive symbols.

6. The method (100) according to claim 4, characterized in that: The comparing of the expected N-level signal with the detected N-level signal includes further converting the expected N-level signal and the detected N-level signal according to a double symbol delay.

7. The method (100) according to any one of claims 1 to 3, characterized in that N=2M-1.

8. The method (100) according to any one of claims 1 to 3, characterized in that M＝2。 9. The method (100) according to any one of claims 1 to 3, characterized in that: The photodiode (218) is limited in bandwidth.

10. The method (100) according to claim 9, characterized in that: The receiving also includes applying an electrical filter (222) to the input optical signal.

11. The method (100) according to any one of claims 1 to 3, characterized in that: Performing the second multi-level detection includes applying a low pass filter (430) for separating the N levels.

12. The method (100) according to any one of claims 1 to 3, characterized in that Also included is applying a technique to compensate for low bandwidth to detect the M levels.

13. A receiving device (204), characterized in that: Comprising a processor (224) for implementing the method (100) of any one of claims 1 to 12.

14. A computer readable medium, characterized in that For storing instructions, when the instructions are executed by a processor (224), the instructions cause the processor (224) to perform the method (100) of any one of claims 1 to 12.

Images