A test structure, chip stacking structure and test method

Abstract

The embodiments of the present disclosure provide a test structure, a chip stacking structure, and a test method. The test structure is applied to a chip stacking structure. The chip stacking structure includes multiple chips, at least two chips constitute a test group, and the test structure includes a test circuit. Each test group has a test circuit, and each chip in the test group includes a portion of the test circuit, wherein: the test circuit is used to test the test group. If the portion of the test circuit included in each chip in the test group is effectively enabled and started, the test circuit starts and outputs a flag signal, and the flag signal indicates that the test group does not include a top-layer chip. In this way, the embodiments of the present disclosure can quickly and accurately determine the top-layer chip from multiple chips, thereby providing a basis for TSV testing and repair.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test structure, a chip stacking structure, and a test method. Background Art

[0002] For memories, such as Dynamic Random Access Memory (DRAM), three-dimensional design has better performance than planar design. In three-dimensional integrated structures, through silicon via (TSV) technology is usually used to achieve vertical interconnection of different chips. Among them, through silicon via technology refers to: etching a through hole in the silicon substrate and filling the through hole with metal conductor materials such as copper and tungsten to form a vertical interconnection of chips. For memories with three-dimensional integrated structures, through silicon vias are important devices to ensure the normal operation of the chip, and testing through silicon vias is an important task. When testing through silicon vias, it is necessary to first connect the test points between the logic chip and the top layer. Therefore, how to accurately determine the top chip from multiple chips is a problem that needs to be solved. Summary of the Invention

[0003] Embodiments of the present disclosure provide a test structure, a chip stacking structure, and a test method.

[0004] In a first aspect, embodiments of the present disclosure provide a test structure applied to a chip stack structure, the chip stack structure including a plurality of chips, at least two of the chips forming a test group, the test structure including a test circuit, each test group having one test circuit, and each chip in the test group including a portion of the test circuit, wherein:

[0005] The test circuit is used to test the test group. If part of the test circuit contained in each chip in the test group is effectively enabled and started, the test circuit is started and outputs a flag signal, and the flag signal indicates that the test group does not contain the top chip.

[0006] In some embodiments, each of the chips is provided with a first test module or a second test module, and each of the chips is connected to a through-silicon via module. When the test group includes two chips, the two chips are connected through the through-silicon via module. The test circuit corresponding to the test group includes the first test module and the second test module. The first test module and the second test module are respectively provided in the two chips, and the two ends of the through-silicon via module are respectively connected to the first test module and the second test module.

[0007] In some embodiments, the first test module is used to determine a first test result based on a voltage change at one end of the through silicon via module connected to the first test module, wherein the first test result is used to indicate whether the first test module is effectively enabled and started;

[0008] The second test module is configured to determine a second test result based on a voltage change at the other end of the through silicon via module connected to the second test module, wherein the second test result is used to indicate whether the second test module is effectively enabled and started;

[0009] The voltage change across the through silicon via module is provided by the first test module and the second test module.

[0010] In some embodiments, the test circuit is further configured to determine that an abnormality exists in the through silicon via module if at most one of the first test result and the second test result is a first value.

[0011] In some embodiments, the test circuit is further configured to determine that bidirectional transmission of the through silicon via module connected to the test circuit is abnormal if both the first test result and the second test result are second values;

[0012] The test circuit is further configured to determine that a unidirectional transmission anomaly exists in the through silicon via module connected to the test circuit if one of the first test result and the second test result is a first value and the other is a second value.

[0013] In some embodiments, the first test module includes a charging module and a first trigger module, and the second test module includes a discharging module and a second trigger module; wherein:

[0014] The charging module is configured to charge the connected through silicon via module to a first level after the first trigger module and the second trigger module receive a power-on signal;

[0015] The discharging module is configured to discharge the TSV module to a second level after the charging module charges the TSV module;

[0016] The first trigger module is configured to perform trigger processing according to the first level and the second level to obtain a first test result;

[0017] The second trigger module is configured to perform trigger processing according to the first level and the second level to obtain a second test result.

[0018] In some embodiments, the first trigger module includes a first trigger and a first inverter, a clock input terminal of the first trigger is connected to an output terminal of the first inverter, an input terminal of the first inverter is connected to the through silicon via module and the charging module, an input terminal of the first trigger is connected to a first power supply module, and an output terminal of the first trigger is used to output the first test result;

[0019] The second trigger module includes a second trigger and a second inverter, the clock input end of the second trigger is connected to the output end of the second inverter, the input end of the second inverter is connected to the through silicon via module and the discharge module, the input end of the second trigger is connected to the second power supply module, and the output end of the second trigger is used to output the second test result.

[0020] In some embodiments, the test circuit further includes an AND logic module, a first input terminal of the AND logic module is connected to the output terminal of the first trigger, and a second input terminal of the AND logic module is connected to the output terminal of the second trigger, wherein:

[0021] The AND logic module is used to perform an AND logic operation on the first test result and the second test result, and output the flag signal.

[0022] In some embodiments, the first trigger module further includes a first transistor, the input end of the first inverter is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first ground module, and the gate of the first transistor is connected to the inverted signal of the power signal;

[0023] The second trigger module further includes a second transistor, the input end of the second inverter is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second grounding module, and the gate of the second transistor is connected to the inverted signal of the electrical signal.

[0024] In some embodiments, the first trigger module further includes a third inverter, and the second trigger module further includes a fourth inverter, wherein:

[0025] The input end of the third inverter is connected to the output end of the first inverter, and the output end of the third inverter is connected to the input end of the first inverter;

[0026] The input end of the fourth inverter is connected to the output end of the second inverter, and the output end of the fourth inverter is connected to the input end of the second inverter.

[0027] In some embodiments, the control terminal of the charging module is connected to a first driving signal, and the control terminal of the discharging module is connected to a second driving signal.

[0028] In some embodiments, each of the chips includes the charging module and the discharging module; and one of the charging module and the discharging module are connected at one end of the through silicon via module, and / or, one of the discharging module and the charging module are connected at the other end of the through silicon via module.

[0029] In some embodiments, the test circuit is also used to perform a first test by connecting the charging module and the discharging module on both sides of the through silicon via module to obtain a first test result, and to perform a second test by connecting another charging module and another discharging module on both sides of the through silicon via module to obtain a second test result.

[0030] In some embodiments, the charging module includes a third transistor, and the discharging module includes a fourth transistor, wherein:

[0031] The gate of the third transistor is connected to the first driving signal, the first electrode of the third transistor is connected to the through silicon via module, and the second electrode of the third transistor is connected to the power supply module;

[0032] The gate of the fourth transistor is connected to the second driving signal, the first electrode of the fourth transistor is connected to the through silicon via module, and the second electrode of the fourth transistor is connected to the ground module.

[0033] In some embodiments, the test circuit further includes a level monitoring module, wherein:

[0034] The level monitoring module is configured to monitor the level value of the through silicon via module during the first test, and output the first test result according to the level value of the through silicon via module;

[0035] The level monitoring module is further configured to monitor the level value of the TSV module during the second test, and output the second test result according to the level value of the TSV module.

[0036] In some embodiments, the test circuit is further configured to determine that the test group corresponding to the test circuit does not include a top chip if both the first test result and the second test result are first values.

[0037] In some embodiments, the stacking mode of the plurality of chips is face-to-face stacking, and the connection mode between two adjacent chips that do not belong to the same test group is hybrid bonding.

[0038] In a second aspect, an embodiment of the present disclosure provides a chip stacking structure, comprising a plurality of chips, wherein at least one test structure as described in the first aspect is disposed in the chip stacking structure.

[0039] In a third aspect, an embodiment of the present disclosure provides a testing method, applied to the test circuit as described in the first aspect, the method comprising:

[0040] The test group is tested by the test circuit. If part of the test circuit included in each chip in the test group is effectively enabled and started, the test circuit is started and outputs a flag signal, which indicates that the test group does not include the top chip.

[0041] The present disclosure provides a test structure, a chip stacking structure, and a test method. The test structure is applied to a chip stacking structure, wherein the chip stacking structure includes a plurality of chips, wherein at least two chips form a test group. The test structure includes a test circuit, wherein each test group has a test circuit, and each chip in the test group includes a portion of the test circuit. The test circuit is used to test the test group. If the portion of the test circuit included in each chip in the test group is effectively enabled and started, the test circuit is started and outputs a flag signal, wherein the flag signal indicates that the test group does not include a top chip. In this way, the chip stacking structure is divided into test groups. If the test group includes at least two chips, then the portion of the test circuit included in the at least two chips can form a complete test circuit. Therefore, when testing, the portion of the test circuit included in each chip in the test group can be effectively enabled and started. At this time, it can be confirmed that the test group does not include a top chip. For the top chip, since it does not form a test group with the other chips, correspondingly, when testing, the portion of the test circuit in the top chip cannot be effectively enabled and started. Therefore, whether the chip is a top chip can be determined based on whether the portion of the test circuit in the chip is effectively enabled and started. Based on this approach, the top chip can be accurately and quickly identified, providing a basis for TSV testing and repair. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of a TSV test circuit;

[0043] Figure 2 A schematic diagram of a chip stack including four memory chips;

[0044] Figure 3 A schematic diagram of a chip stack containing 8 memory chips;

[0045] Figure 4 A schematic diagram of the composition structure of a chip stacking structure provided in an embodiment of the present disclosure;

[0046] Figure 5 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0047] Figure 6 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0048] Figure 7 A schematic diagram of a circuit structure of a test circuit provided in an embodiment of the present disclosure;

[0049] Figure 8 A signal timing diagram provided in an embodiment of the present disclosure;

[0050] Figure 9 A schematic diagram of the structure of another TSV test circuit;

[0051] Figure 10 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0052] Figure 11 A schematic diagram of the circuit structure of another test circuit provided in an embodiment of the present disclosure;

[0053] Figure 12 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0054] Figure 13 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0055] Figure 14 A schematic top view of a chip provided in an embodiment of the present disclosure;

[0056] Figure 15 A schematic diagram of the composition structure of another chip stacking structure provided by an embodiment of the present disclosure;

[0057] Figure 16 A schematic top view of another chip provided in an embodiment of the present disclosure;

[0058] Figure 17 A flowchart of a testing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0061] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0062] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0063] Figure 1 FIG. 1 shows a schematic diagram of the structure of a TSV test circuit. Figure 1 As shown, DRAM includes a logic chip (also called a bottom chip, substrate chip, or Base Die) and eight memory chips (respectively denoted as Die0, Die1, Die2, Die3, Die4, Die5, Die6, and Die7). These multiple chips form a chip stack structure and are connected together through TSVs. In actual production, there is usually a need for TSV testing. At this time, it is necessary to determine the top chip (TopDie) from multiple memory chips, and connect TSV test points to the TSVs in the top chip and the TSVs in the logic chip to test the TSVs. In other words, the significance of finding the top chip is that most TSV testing technologies require a test loop to be formed between the top chip and the logic chip. Since there is a test loop in the memory chip and the logic chip, after finding the top chip, the test loop between the top chip and the logic chip can be used to perform a comprehensive test on the logic chip and all memory chips. Otherwise, if a non-top chip is tested, only part of the memory chips will actually be tested, resulting in low coverage, or extra time will be spent on testing the remaining memory chips, resulting in low efficiency. At this time, the top chip can be identified by the chip identity document (ID).

[0064] In DRAM, the stacking of chips can include different configurations such as 4 / 8 / 12 / 16, that is, DRAM can be formed by stacking a logic chip plus 4 / 8 / 12 / 16 memory chips (also called core dies). For example, Figure 2 Figure 2 shows a schematic diagram of a chip stack containing four memory chips. Figure 2 In the DRAM, there is a logic chip (Base Die) and four memory chips (Die0, Die1, Die2, and Die3). Each memory chip is numbered as the ID of each memory chip, abbreviated as chip ID (or Stack ID, SID). Starting from Die 0 adjacent to the logic chip, they are numbered as: 0000, 0001, 0010, 0011. It can be seen that at this time, two bits are actually needed to represent the ID of each memory chip.

[0065] Figure 3 A schematic diagram of a chip stack containing 8 memory chips is shown. Figure 3 In the DRAM, there is a logic chip (Base Die) and eight memory chips (Die0, Die1, Die2, Die3, Die4, Die5, Die6, and Die7). Starting from Die0, which is adjacent to the logic chip, the chips are numbered as follows: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111. It can be seen that three bits are actually needed to represent the ID of each memory chip.

[0066] like Figure 2 and Figure 3 The chip ID of the top die will also be different in different configurations. When 16 memory chips are stacked, 4 bits are required to represent the chip ID. As the number of memory chips continues to increase, more bits are required to represent the chip ID. For this method of determining the top die by SID, on the one hand, the SID may be subject to transmission errors. On the other hand, the number of memory chips is not a specific number, making it impossible to find the top die based on a specific SID. For example, when 4 memory chips are stacked, the chip with SID 0011 is the top die. However, when the number of chips stacked is not 4, the chip with SID 0011 is not the top die. On the other hand, when the number of stacked memory chips is large, even if a random selection method is used, the probability of selecting the top die is relatively low. It can be seen that the error probability of using SID to determine the top die is relatively high. Therefore, relying on the chip ID to determine the top die requires that the TSV that transmits the chip ID is very robust; otherwise, it is easy to make mistakes.

[0067] Based on this, an embodiment of the present disclosure provides a test structure for use in a chip stack structure, the chip stack structure including a plurality of chips, at least two of which constitute a test group, the test structure including a test circuit, each test group having a test circuit, each chip in the test group including a portion of the test circuit, wherein the test circuit is used to test the test group, and if the portion of the test circuit included in each chip in the test group is effectively enabled and activated, the test circuit is activated and outputs a flag signal, the flag signal indicating that the test group does not include a top chip. In this way, the chip stack structure is divided into test groups. If the test group includes at least two chips, the portion of the test circuit included in the at least two chips can form a complete test circuit. Therefore, when testing, the portion of the test circuit included in each chip in the test group can be effectively enabled and activated. At this time, it can be confirmed that the test group does not include a top chip. For the top chip, since it does not form a test group with the other chips, the portion of the test circuit in the top chip cannot be effectively enabled and activated during testing. Therefore, whether the chip is a top chip can be determined based on whether the portion of the test circuit in the chip is effectively enabled and activated. Based on this approach, the top chip can be accurately and quickly identified, providing a basis for TSV testing and repair.

[0068] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0069] In one embodiment of the present disclosure, see Figure 4 , which shows a schematic diagram of the composition structure of a chip stacking structure 10 provided by an embodiment of the present disclosure, and the test structure provided by an embodiment of the present disclosure is applied to the chip stacking structure 10. Figure 4 As shown, the chip stack structure 10 includes multiple chips, at least two chips form a test group 11, the test structure includes a test circuit 12, each test group 11 has a test circuit 12, and each chip in the test group 11 includes a portion of the test circuit, wherein:

[0070] The test circuit 12 is used to test the test group 11. If part of the test circuits included in each chip in the test group 11 are effectively enabled, the test circuit 12 is started and outputs a flag signal, which indicates that the test group does not include the top chip.

[0071] It should be noted that if Figure 4 As shown, the chip stacking structure 10 includes a logic chip (Base Die) and four memory chips (Die0, Die1, Die2 and Die3), and each test group 11 includes two chips. It can be understood that Figure 4 This is just an example, and the types and quantities of the multiple chips are not specifically limited. A test group may also include three or more chips. Figure 4 The specific implementation of the embodiment of the present disclosure is described by taking FIG.

[0072] like Figure 4 As shown, the chip stack structure 10 includes five chips, of which Base Die and Die0 form a test group, Die1 and Die2 form a test group, and each test group 11 has a test circuit 12. For each test group 11, the two chips respectively contain parts of the test circuit 11, so that the test circuit 12 can test the corresponding test group 11.

[0073] It should also be noted that for each test circuit 12, if there is no fault in the test circuit 12, then when the test group 11 is tested, part of the test circuit contained in each chip in the test group 11 can be effectively enabled and started. At this time, the test circuit 12 will output a flag signal, indicating that the test group 11 does not contain the top chip. Based on this, Figure 4 In the example, Base Die, Die0, Die1, and Die3 are not top chips.

[0074] It should also be noted that if Figure 4 As shown in the figure, since Die3 is not part of a test group with other chips, only part of the test circuit is included in Die3. Since the test circuit is not complete, some of the test circuits in Die3 cannot be effectively enabled, and the flag signal indicating that the top chip is not included cannot be obtained. Therefore, Die3 can be determined to be the top chip.

[0075] It should also be noted that although Figure 3 In the figure, it can be observed that Die3 is located at the top layer of the chip stacking structure 10. However, in an actual memory, due to various reasons such as the complexity of the circuit and the packaging, it is impossible to intuitively determine the top layer chip.

[0076] In this way, the embodiment of the present disclosure divides the chip stacking structure into test groups and performs tests using test circuits corresponding to the test groups. For non-top chips, since they can form a test group with adjacent chips, the test circuit can output a flag signal indicating that the test group does not include the top chip. For the top chip, since it does not form a test group with other chips, some test circuits in the chip cannot output the flag signal. In this way, the top chip can be determined from multiple chips, and then the TSV test of the chip stacking structure can be performed based on the test points determined according to the top chip.

[0077] Furthermore, Figure 5 and Figure 6Schematic diagrams of two different chip stacking structures provided by the embodiments of the present disclosure are shown. Figure 5 As shown, in some embodiments, a first test module 14 or a second test module 15 is provided in each chip, and each chip is connected to a through silicon via module 13. When the test group 11 includes two chips, the two chips are connected through the through silicon via module 13. The test circuit corresponding to the test group 11 includes a first test module 14 and a second test module 15. The first test module 14 and the second test module 15 are respectively provided in the two chips, and the two ends of the through silicon via module 13 are respectively connected to the first test module 14 and the second test module 15.

[0078] It should be noted that, in the embodiment of the present disclosure, the stacking method between the multiple chips in the chip stacking structure 10 is face-to-face stacking, and the connection method between two adjacent chips that do not belong to the same test group is hybrid bonding. Figure 5 As shown, in each test group 11, two chips are connected together through a through silicon via module 13. At this time, the through silicon via module 13 is formed in the substrates of the two chips. That is, the substrates of the two chips in the same test group 11 are opposite to each other and are connected through the through silicon via module 13; two adjacent chips that do not belong to the same test group are not connected through the through silicon via module, but are connected by hybrid bonding (such as Figure 5 16 in FIG), the two chips have their sides facing away from the substrate facing each other.

[0079] It should also be noted that when a chipset contains two chips, the chip that does not form a chipset is the top chip. In this case, the total number of chip stacking structures is usually an odd number, or the chip stacking structure contains a logic chip (bottom chip) and an even number of memory chips. For example, Figure 5 There are a total of 5 chips, including a BaseDie and 4 memory chips.

[0080] It should also be noted that each chip in the chip stacking structure 10 is connected to a through silicon via module 13. For the through silicon via module 13 in the test group 11, both ends are connected to a chip. For the top chip (for example, Die3), since it does not form a test group, the through silicon via module 13 connected to Die3 has only one end connected to the chip, and the other end is not connected to the chip.

[0081] It should also be noted that the test circuit corresponding to test group 11 includes a first test module 14 and a second test module 15, and that first test module 14 and second test module 15 are respectively located in two chips of test group 11. As for the top chip, since it only corresponds to part of the test circuit, the top chip only contains the first test module 14 or the second test module 15.

[0082] exist Figure 5 In a test group 11, the chip at the bottom includes a first test module 14, and the chip at the top includes a second test module 15. Die3 does not form a test group with other chips and includes the first test module 14. Figure 6 In a test group 11, the chip at the bottom includes the second test module 15, and the chip at the top includes the first test module 14. Die 3 does not form a test group with other chips, but includes the second test module 15. Furthermore, the terms "up" and "down" are used only for ease of description with reference to the accompanying drawings. In actual production, the positional relationship between chips is not necessarily up and down. In the embodiments of the present disclosure, the terms "up" and "down" or "left" and "right" used in other descriptions are also used for ease of description with reference to the accompanying drawings and do not constitute a limitation to the embodiments.

[0083] by Figure 5 For example, in a test group 11, if the first test module 14, the TSV module 13 and the second test module 15 are all normal and have no faults, then during the test, the TSV module 13 can transmit signals normally, and the first test module 14 and the second test module 15 can also be effectively enabled and started, indicating that the chips to which the first test module 14 and the second test module 15 belong belong to the same test group, that is, neither of the two chips is a top-level chip. As for Die3, although the first test module 14 and the TSV module 13 are normal, since they do not form a complete test circuit with the second test module 15, the first test module 14 cannot be effectively enabled and started, indicating that the chip to which the first test module 14 belongs does not form a test group with other chips, then the Die3 to which the first test module 14 belongs is a top-level chip. Figure 6 The principle of the structure shown is Figure 5 Similar, no further description here.

[0084] In this way, although each chip contains the first test module or the second test module, only the first test module and the second test module in the two chips in the test group can be effectively enabled and started, and the first test module or the second test module in the top chip cannot be effectively enabled and started. Therefore, it can be judged that the chip to which the first test module or the second test module that cannot be effectively enabled and started belongs is the top chip.

[0085] In some embodiments, the first test module 14 is configured to determine a first test result based on a voltage change at one end of the through silicon via module 13 connected to the first test module 14 , wherein the first test result is configured to indicate whether the first test module 14 is effectively enabled and started;

[0086] A second test module 15 is configured to determine a second test result based on a voltage change at the other end of the through silicon via module 13 connected to the second test module 15 , wherein the second test result is used to indicate whether the second test module 15 is effectively enabled and started;

[0087] The voltage change across the TSV module 13 is provided by the first test module 14 and the second test module 15 .

[0088] It should be noted that after testing the first test module 14 or the second test module 15, i.e., the aforementioned partial test circuit, the first test module 14 will output a first test result, and the second test module 15 will output a second test result. The first test module 14 and the second test module 15 can respectively charge or discharge the TSV module 13, thereby causing a voltage change at both ends of the TSV module 13 during the charging and discharging process. The end of the TSV module 13 connected to the first test module 14 is referred to as the first end, and the end of the TSV module 13 connected to the second test module 15 is referred to as the second end. Based on the voltage change at the first end of the TSV module 13, the first test module 14 can output a first test result; and based on the voltage change at the second end of the TSV module 13, the second test module 15 can output a second test result. The voltage change is generated by providing different voltage levels to the TSV 13 provided by the first test module 14 and the second test module 15.

[0089] It should also be noted that for the first test module 14 and the second test module 15 within the test group 11, since the corresponding test circuits are complete, the first test module 14 and the second test module 15 can both be effectively enabled and started, thereby outputting the first test result and the second test result representing the non-top chip. However, in the top chip that does not form a test group, the first test module 14 or the second test module 15 does not form a complete test circuit, so the first test module 14 or the second test module 15 in the top chip cannot be effectively enabled and started, thereby outputting the first test result or the second test result representing the top chip.

[0090] Further, see Figure 7 , which shows a circuit structure diagram of a test circuit 12 provided by an embodiment of the present disclosure. Figure 7As shown, in some embodiments, the first test module 14 includes a charging module 141 and a first trigger module 142, and the second test module 15 includes a discharging module 151 and a second trigger module 152; wherein:

[0091] The charging module 141 is configured to charge the connected through silicon via module 13 to a first level after the first trigger module 142 and the second trigger module 152 receive a power-on signal;

[0092] The discharge module 151 is configured to discharge the TSV module 13 to a second level after the charging module 141 charges the TSV module 13;

[0093] A first trigger module 142 is configured to perform trigger processing according to the first level and the second level to obtain a first test result;

[0094] The second trigger module 152 is configured to perform trigger processing according to the first level and the second level to obtain a second test result.

[0095] It should be noted that if Figure 7 As shown, the charging module 141 is connected to the first end of the through silicon via module 13, and the charging module 141 is also connected to the first trigger module 142; the discharging module 151 is connected to the second end of the through silicon via module 13, and the discharging module 151 is also connected to the second trigger module 152. P_on represents the power-on signal (Power_on). When testing, the power-on signal is in a valid state, otherwise, the power-on signal is in an invalid state. In the embodiment of the present disclosure, the valid state is a high level logic 1, and the invalid state is a low level logic 0 as an example for description. However, in other structural embodiments of the first trigger module and the second trigger module, the valid state can also be a low level logic 0, and the invalid state can also be a high level logic 1, which is not specifically limited here.

[0096] It should also be noted that when the first trigger module 142 and the second trigger module 152 both receive the power-on signal, the first trigger module 142 and the second trigger module 152 both enter the test state; after entering the test state, the charging module 141 first charges the through silicon via module 13. If there is no abnormality in the through silicon via module 13, the first end and the second end of the through silicon via module 13 are both charged to the first level, where the first level can indicate a high level of logic 1; after the through silicon via module 13 is charged to the first level, the discharge module 151 discharges the through silicon via module 13. If there is no abnormality in the through silicon via module 13, the first end and the second end of the through silicon via module 13 are both discharged to the second level, where the second level can indicate a low level of logic 0.

[0097] In this way, since the through silicon via module 13 is first charged to the first level and then discharged to the second level, a voltage change will occur at both ends of the through silicon via module 13 during this process. According to this voltage change, the first trigger module 142 and the second trigger module 152 are triggered, thereby outputting the first test result and the second test result representing the non-top layer chip, respectively.

[0098] However, for the top chip, since it only includes one of the first test module 14 or the second test module 15, the corresponding first trigger module 142 or the second trigger module 152 cannot be triggered, and the test results representing the non-top chip cannot be output.

[0099] Specifically, when the top chip only includes the first test module 14, after the test starts, the through silicon via module 13 can be charged to the first level by the charging module 141, but since the other end of the through silicon via module 13 is not connected to the second test module 15, there is no discharge module 151 to discharge the through silicon via module 13, resulting in no voltage change in the through silicon via module 13 and the first trigger module 142 cannot be triggered. At this time, the first trigger module 142 outputs the first test result representing the top chip.

[0100] When the top chip includes only the second test module 15, after the test starts, since one end of the TSV module 13 is not connected to the first test module 14, there is no charging module 141 for charging the TSV module 13, and the TSV module 13 cannot be charged to the first level. Although the discharge module 151 can discharge the TSV module 13 to the second level, since it is not charged to the first level, the voltage of the TSV module 13 does not change, and the second trigger module 152 cannot be triggered. At this time, the second trigger module 152 outputs a second test result representing the top chip.

[0101] Thus, whether the chip to which the first test module 14 belongs is the top chip can be determined based on the first test result output by the first test module 14. Similarly, whether the chip to which the second test module 15 belongs is the top chip can be determined based on the second test result output by the second test module 15.

[0102] Furthermore, based on the test circuit 12, it is also possible to determine whether the TSV module 13 within the corresponding test group 11 has an abnormality. Specifically, if the TSV module 13 does not have an abnormality, voltage changes will occur at both ends of the TSV module 13. The first test result and the second test result indicate that the chip is not a top-layer chip, meaning that the TSV module 13 does not have an abnormality. If both bidirectional transmission of the TSV module 13 has an abnormality, then when the TSV module 13 is charged, the second end cannot be charged to the first voltage level, and when the TSV module 13 is discharged, the first end cannot be discharged to the second voltage level. There will be no voltage change at both ends of the TSV module 13, or the voltage change is not large enough to trigger the first trigger module 142 or the second trigger module 152. In this case, the chip is a top-layer chip, and the first and second test results actually indicate that the TSV module 13 has a transmission abnormality. In other words, the first and second test results can be used to indicate whether the chip is a top-layer chip, and can also be used to determine whether there is a transmission abnormality in the TSV module if the chip is determined to be a non-top-layer chip.

[0103] If the through silicon via module 13 has an abnormality in transmitting from the first end to the second end, or if the through silicon via module 13 has an abnormality in transmitting a high level, then during charging, only the first end can be charged to the first level, and the second end cannot be charged to the first level. During discharging, the first end can be discharged to the second level. At this time, a normal voltage change will occur at the first end, triggering the first trigger module 142, so that the first trigger module 142 can output a first test result representing a non-top chip, but the second end is not charged to the first level, no voltage change will occur, and the second trigger module 152 cannot be triggered. Therefore, the second test result represents the top chip, which means that there is an abnormality in the through silicon via module 13.

[0104] If the through silicon via module 13 has an abnormality in transmitting power from the second end to the first end, or if the through silicon via module 13 has an abnormality in transmitting a low level, then during charging, although both the first end and the second end can be charged to the first level, during discharging, only the second end can be discharged to the second level. At this time, a normal voltage change will occur at the second end, triggering the second trigger module 152, so that the second trigger module 152 can output a second test result representing a non-top chip. However, since the first end is not discharged to the second level, no voltage change will occur, and the first trigger module 142 cannot be triggered. Therefore, the first test result represents the top chip, which means that there is an abnormality in the through silicon via module 13.

[0105] In this way, the embodiment of the present disclosure charges and discharges the TSV module 13 through the charging module 141 and the discharging module 151, respectively. During the charging and discharging process, the voltage at both ends of the TSV module 13 changes, thereby triggering the first trigger module 142 and the second trigger module 152. Only when there is no abnormality in the TSV module 13, the first trigger module 142 and the second trigger module 152 will be triggered to output the first test result and the second test result representing the non-top chip, indicating that there is no abnormality in the TSV module 13. Otherwise, the test result representing the top chip will be output to the non-top chip, indicating that there is an abnormality in the TSV module 13. This also allows the TSV module 13 to be tested and whether there is an abnormality in the TSV module 13.

[0106] Furthermore, regarding the specific composition of the test circuit 12, as shown in FIG. Figure 7 As shown, in some embodiments, the first trigger module 142 includes a first trigger 1421 and a first inverter 1422. The clock input terminal CLK of the first trigger 1421 is connected to the output terminal of the first inverter 1422. The input terminal of the first inverter 1422 is connected to the through silicon via module 13 and the charging module 141. The input terminal D of the first trigger 1421 is connected to the first power supply module VDD1. The output terminal Q of the first trigger 1421 is used to output the first test result.

[0107] The second trigger module 152 includes a second trigger 1521 and a second inverter 1522. The clock input terminal CLK of the second trigger 1521 is connected to the output terminal of the second inverter 1522. The input terminal of the second inverter 1522 is connected to the silicon through via module 13 and the discharge module 151. The input terminal D of the second trigger 1521 is connected to the second power supply module VDD2. The output terminal Q of the second trigger 1521 is used to output the second test result.

[0108] The first test module 142 further includes a first transistor T1, an input end of a first inverter 1422 is connected to a first electrode of the first transistor T1, a second electrode of the first transistor T1 is connected to a first grounding module VSS1, and a gate of the first transistor T1 is connected to an inverted signal of the power signal;

[0109] The second test module 15 further includes a second transistor T2. The input end of the second inverter 1522 is connected to the first electrode of the second transistor T2. The second electrode of the second transistor T2 is connected to the second ground module VSS2. The gate of the second transistor T2 is connected to the inverted signal of the upper electrical signal.

[0110] The charging module 141 may include a third transistor T3, wherein a gate of the third transistor T3 receives a first driving signal, a first electrode of the third transistor T3 is connected to an input end of the first inverter 1422 and a first end of the through silicon via module 13, and a second electrode of the third transistor T3 is connected to a third power supply module VDD3;

[0111] The discharge module 151 may include a fourth transistor T4, a gate of the fourth transistor T4 receives the second driving signal, a first electrode of the fourth transistor T4 is connected to the input end of the second inverter 1522 and the second end of the through silicon via module 13, and a second electrode of the fourth transistor T4 is connected to the third ground module VSS3.

[0112] It should be noted that in Figure 7 In the embodiment, the first power module VDD1, the second power module VDD2, and the third power module VDD3 can be different modules or the same power supply, and this is not specifically limited here. Similarly, the first ground module VSS1, the second ground module VSS2, and the third ground module VSS3 can be different modules or the same ground terminal, and this is not specifically limited here. The voltage level provided by VDD1 / VDD2 / VDD3 is a first value, and the voltage level provided by VSS1 / VSS2 / VSS3 is a second value. The first value represents a high level logic 1, and the second value represents a low level logic 0.

[0113] like Figure 7 As shown, the first transistor T1, the second transistor T2 and the fourth transistor T4 are all N-type metal oxide semiconductor field effect transistors (NMOS transistors), and the third transistor T3 is a P-type metal oxide semiconductor field effect transistor (PMOS transistor).

[0114] The gates of the first transistor T1 and the second transistor T2 both receive the inverted signal of the power-on signal (in the figure, Thus, when not being tested, the power-on signal is in an invalid state (i.e., logic 0 at a low level), and the inverted signal of the power-on signal is in a valid state (logic 1 at a high level). Under the control of , the first transistor T1 and the second transistor T2 are in the on state. Figure 7As shown, since the first electrode of the first transistor T1 is connected to the input terminal of the first inverter 1422 and the first terminal of the through-silicon via module 13, and the first electrode of the second transistor T2 is connected to the input terminal of the second inverter 1522 and the second terminal of the through-silicon via module 13, the input terminal of the first inverter 1422 receives the second value, inverts it, and outputs the first value to the clock input terminal CLK of the first flip-flop 1421. The input terminal of the second inverter 1522 also receives the second value, inverts it, and outputs the first value to the clock input terminal CLK of the second flip-flop 1521. During this period, the control terminals RN of the first flip-flop 1421 and the second flip-flop 1422 do not receive the power-on signal, or in other words, receive an invalid power-on signal.

[0115] After the test starts, the power-on signal is in a valid state. The first trigger 1421 and the second trigger 1521 receive the power-on signal and turn on, entering the test state. Since the inverted signal of the power-on signal is in an invalid state, the first transistor T1 and the second transistor T2 are not conducting. After entering the test state, the first drive signal (represented by PDRV in the figure) is first provided to the third transistor T3, so that the third transistor T3 is turned on. Since the third transistor T3 is a PMOS tube, the level value of the first drive signal is the second value (low level logic 0). After the third transistor T3 is turned on, the high level provided by VDD3 is transmitted, so that the two ends of the silicon via module 13 are charged to the first level, wherein the level value of the first level is the first value (high level logic 1). At the same time, the input ends of the first inverter 1422 and the second inverter 1522 also receive the first value, and after inversion processing, output the second value to the clock receiving end CLK of the first trigger 1421 and the second trigger 1521.

[0116] Next, the first drive signal is no longer provided to the third transistor T3. Instead, a second drive signal (denoted by NDRV in the figure) is provided to the fourth transistor T4, turning on the fourth transistor T4. Since the fourth transistor T4 is an NMOS transistor, the level of the second drive signal is the first value. After the fourth transistor T4 is turned on, the low level provided by VSS3 is transmitted, thereby discharging the two ends of the through-silicon via module 13 to the second level, where the level of the second level is the second value. At the same time, the input terminals of the first inverter 1422 and the second inverter 1522 also receive the second value, and after inversion, output the first value to the clock receiving terminal CLK of the first flip-flop 1421 and the second flip-flop 1521. Thus, for first flip-flop 1421 and second flip-flop 1521, the signal received at clock receiving terminal CLK changes from the second value to the first value, forming a rising edge, thereby triggering first flip-flop 1421 and second flip-flop 1521. First flip-flop 1421 and second flip-flop 1521 sample the signal received at their input terminal D based on the signal received at clock input terminal CLK and output a test result at output terminal Q. Since input terminal D of first flip-flop 1421 is connected to VDD1 and input terminal D of second flip-flop 1521 is connected to VDD2, and VDD1 / VDD2 provide a high-level first value, then, when TSV module 13 functions properly, the first test result outputted at output terminal Q of first flip-flop 1421 and the second test result outputted at output terminal Q of second flip-flop 1521 are both the first value. Thus, here, when the first test result / second test result is the first value, it indicates a non-top chip, and when the first test result / second test result is the second value, it indicates a top chip.

[0117] As previously mentioned, for non-top chips, since the test circuit is complete, the first test result output by first flip-flop 1421 and the second test result output by second flip-flop 1521 are both the first value. However, for top chips, since the test circuit is not complete, the first test result output by first flip-flop 1421 or the second test result output by second flip-flop 1521 is the second value.

[0118] That is to say, for the first test module 141, when the first test result is the first value, the chip to which the corresponding first test module 141 belongs is a non-top-level chip; when the first test result is the second value, the chip to which the corresponding first test module 141 belongs is a top-level chip; for the second test module 151, when the second test result is the first value, the chip to which the corresponding second test module 151 belongs is a non-top-level chip; when the second test result is the second value, the chip to which the corresponding second test module 151 belongs is a top-level chip.

[0119] Furthermore, when the through silicon via module 13 in the test group 11 is tested in this manner, if there are abnormalities in the bidirectional transmission of the through silicon via module 13, then a rising edge cannot be formed at the clock input terminal CLK of the first trigger 1421 and the second trigger 1521, and the first trigger 1421 and the second trigger 1521 will not be triggered, so that the first test result and the second test result are both the second value.

[0120] If the TSV module 13 transmits abnormally from the first end to the second end, or transmits abnormally high level, only the first trigger 1421 will be triggered and output the first value, but the second trigger 1521 will not be triggered and output the second value.

[0121] If the TSV module 13 transmits abnormally from the second end to the first end, or transmits abnormally at a low level, only the second trigger 1521 will be triggered and output the first value, but the first trigger 1421 will not be triggered and output the second value.

[0122] That is, the test circuit 12 is further configured to determine that an abnormality exists in the TSV 13 module if at most one of the first test result and the second test result is a first value.

[0123] Specifically, the test circuit 12 is also used to determine that there is an abnormality in the bidirectional transmission of the through silicon via module 13 connected to the test circuit 12 if the first test result and the second test result are both the second value; the test circuit 12 is also used to determine that there is an abnormality in the unidirectional transmission of the through silicon via module 13 connected to the test circuit 12 if one of the first test result and the second test result is the first value and the other is the second value.

[0124] In addition, the embodiment of the present disclosure is illustrated by taking the first trigger 1421 and the second trigger 1521 as triggers triggered by rising edges as an example. For other types of triggers, it is only necessary to adaptively adjust the circuit to still detect whether the chip is a top-level chip and test the silicon through-via module 13. The design ideas are consistent and will not be repeated here.

[0125] It should also be noted that, with respect to first flip-flop 1421 and second flip-flop 1521, first flip-flop 1421 is further configured to reset the output of first flip-flop 1421 when it does not receive a power-on signal, and second flip-flop 1521 is further configured to reset the output of second flip-flop 1521 when it does not receive a power-on signal. Thus, resetting the outputs of the flip-flops when not testing can also prevent signal interference and inaccurate test results.

[0126] Further, if Figure 7As shown, in some embodiments, the first trigger module 142 further includes a third inverter 1423, and the second trigger module 152 further includes a fourth inverter 1523, wherein:

[0127] The input end of the third inverter 1423 is connected to the output end of the first inverter 1422 , and the output end of the third inverter 1423 is connected to the input end of the first inverter 1422 ;

[0128] An input terminal of the fourth inverter 1523 is connected to an output terminal of the second inverter 1522 , and an output terminal of the fourth inverter 1523 is connected to an input terminal of the second inverter 1522 .

[0129] It should be noted that if Figure 7 As shown, the first trigger module 142 further includes a third inverter 1423. The third inverter 1423 and the first inverter 1422 are connected end to end to form a latch structure, thereby ensuring the reliability of the signal input to the clock input terminal CLK of the first trigger 1421. The second trigger module 152 further includes a fourth inverter 1523. The fourth inverter 1523 and the second inverter 1522 are connected end to end to form a latch structure, thereby ensuring the reliability of the signal input to the clock input terminal CLK of the second trigger 1521.

[0130] Furthermore, Figure 8 A signal timing diagram provided by the disclosed embodiment is shown below. Figure 8 Briefly describe the test results output by the test circuit. It represents the inverted signal of the power-on signal, P_on represents the power-on signal, PDRV represents the first drive signal, NDRV represents the second drive signal, TSV(abnormal) represents the voltage change of the through silicon via module (first end) with bidirectional transmission abnormality, or represents the voltage change of the through silicon via module connected to the top chip, P(abnormal) represents the first test result when the through silicon via module has a bidirectional transmission abnormality, or represents the first test result output by the first test module in the top chip, TSV(normal) represents the voltage change of the normal through silicon via module (first end), and P(normal) represents the first test result when the through silicon via module is normal.

[0131] Combine Figure 7 and Figure 8 As shown, before point A, that is, before power is applied, the power-on signal is at a low level, and the inverted signal of the power-on signal is at a high level. At this time, the control terminal RN of the first trigger 1421 is at a low level, the gate of the first transistor T1 is at a high level, and the first transistor T1 is turned on, so that the input terminal of the first inverter 1422 is grounded, and the output terminal of the first inverter 1422 outputs a high level, that is, the clock input terminal CLK of the first trigger 1421 is set to "1".

[0132] At point B, the first drive signal PDRV is at a low level, causing the third transistor T3 to be turned on and charging the through-silicon via module 13. As shown in TSV (normal), the input end of the first inverter 1422 is at a high level, and the output end of the first inverter 1422 outputs a low level to the clock input end CLK of the first trigger 1421, that is, the clock input end CLK of the first trigger 1421 is set to "0".

[0133] At point C, the first driving signal PDRV changes from a low level to a high level, so that the third transistor T3 is turned off.

[0134] At point D, the second drive signal NDRV is at a high level, causing the fourth transistor T4 to be turned on, causing the through silicon via module 13 to discharge, as shown in TSV (normal). The input terminal of the first inverter 1422 becomes a low level, and the output terminal of the first inverter 1422 outputs a high level to the clock input terminal CLK of the first trigger 1421, thereby generating a rising edge at the clock input terminal CLK of the first trigger 1421, and the output terminal Q of the first trigger 1421 outputs a high level, as shown in P (normal).

[0135] For a TSV module with a bidirectional transmission anomaly, as indicated by TSV (abnormal), the voltage of the TSV module does not change during charging and discharging. Accordingly, the clock input CLK of the first trigger 1421 cannot detect a rising edge, the first trigger 1421 is not triggered, and its output Q outputs a low level, as indicated by P (abnormal). For the TSV module connected to the top chip, as indicated by TSV (abnormal), since the TSV module can only be charged but not discharged, the voltage change required for triggering does not occur. Consequently, the clock input CLK of the first trigger 1421 cannot detect a rising edge, the first trigger 1421 is not triggered, and its output Q outputs a low level, as indicated by P (abnormal).

[0136] The same is true for the unidirectional transmission anomaly and the second detection circuit 15 , which will not be described in detail here.

[0137] It should be noted that, during the test, in the first test module 14, the charging module 141 needs to receive the first driving signal PDRV, and in the second test module 15, the discharging module 151 needs to receive the second driving signal NDRV. Figure 7 As shown, the control terminal of the charging module 141 is connected to the first driving signal PDRV, and the control terminal of the discharging module 151 is connected to the second driving signal NDRV. The control terminal of the charging module 141 is the gate of the third transistor T3, and the control terminal of the discharging module 151 is the gate of the fourth transistor T4.

[0138] Further, if Figure 7 As shown, in some implementations, the test circuit 12 further includes an AND logic module 18, wherein a first input terminal of the AND logic module 18 is connected to an output terminal of the first flip-flop 1421, and a second input terminal of the AND logic module 18 is connected to an output terminal of the second flip-flop 1521, wherein:

[0139] The AND logic module 18 is configured to perform an AND logic operation on the first test result and the second test result, and output a flag signal.

[0140] It should be noted that the first input end of the AND logic module 18 receives the first test result, and the second input end of the AND logic module 18 receives the second test result. The first test result and the second test result are subjected to an AND logic operation, and a flag signal is obtained and outputted at the output end of the AND logic module 18.

[0141] Only when both the first test result and the second test result are the first value (logical 1) will the AND logic module output a flag signal of the first value, indicating that the test group corresponding to the test circuit 12 does not include the top chip. However, in the top chip, since a complete test circuit is not formed, only one input terminal of the AND logic module 18 has an input, and the input signal is the second value, so the first value flag signal cannot be obtained. In addition, when testing the TSV module 13, if the TSV module 13 has an abnormality, one or both of the first test result and the second test result will be the second value (logical 0), so that the AND logic module 18 outputs the second value, indicating that the corresponding TSV module has an abnormality. The AND logic module 18 can be an AND gate.

[0142] In addition, in the embodiment of the present disclosure, the first test result and the second test result may also directly constitute a flag signal, that is, when the first test result and the second test result are both the first value, it indicates that the corresponding chipset does not include the top chip.

[0143] Furthermore, Figure 9 FIG. 1 shows another schematic diagram of the structure of a TSV test circuit. Figure 9 As shown, the test group includes chip 1 and chip 2, and chip 1 and chip 2 are connected through TSV. Chip 1 can represent a logic chip (Base Die), chip 2 can represent a memory chip (Core Die), or chip 1 and chip 2 can also represent any two chips connected through TSV. Figure 9 FIG3 shows three identical test circuits: test circuit 1, test circuit 2, and test circuit 3. Test circuit 1 serves as the main test circuit, and test circuit 2 and test circuit 3 serve as redundant backups. Test circuit 1 is used as an example for description.

[0144] like Figure 9As shown, in the test circuit 1, only VDD, VSS, P1, N1, P2, N2, TSV and the repair flag latch (also called Repair Flag Latch) need to be paid attention to. As the other parts of the circuit are not involved in the embodiments of this disclosure, they will not be described in detail. Among them, VDD represents the power supply, which is used to provide a high level (logic 1), VSS represents the ground, which is used to provide a low level (logic 0), P1 and P2 represent PMOS transistors, and N1 and N2 represent NMOS transistors.

[0145] The test principle of this circuit is as follows: P1 and N2 are connected to form a test loop for the first test (as shown by the solid line curve with an arrow). If the TSV connection is normal, the repair flag latch will receive a high-level signal; otherwise, it will receive a low-level signal. P2 and N1 are connected to form a test loop for the second test (as shown by the dashed line curve with an arrow). If the TSV connection is normal, the repair flag latch will receive a high-level signal; otherwise, it will receive a low-level signal. In other words, if the TSV connection is normal, a high-level signal will be received in both tests.

[0146] The PMOS transistor has a low on-resistance, while the NMOS transistor has a relatively high on-resistance. This is because if the TSV is functioning properly, a high level must be output at the node connecting the TSV and the repair flag latch. This requires a relatively large voltage divider on the NMOS transistor. The voltage at this node is the voltage divided by the voltage of N2 and the TSV series resistor. When P1 and N2 are on, the voltage divider at this node can only be detected when the resistance of N2 is relatively high. If the resistance of N2 is relatively low, the voltage at this node approaches a low level. The same principle applies to P2 and N1. Therefore, P1 and P2 can also be called strong PMOS transistors (Strong PMOS), and N1 and N2 can be called weak NMOS transistors (Weak NMOS). In other words, the principle of forming a test loop with strong PMOS and weak NMOS is that if the results of both the P1+N2 and P2+N1 tests are "1", it indicates that the TSV connection is normal. "1" represents a high level, and "0" represents a low level.

[0147] Based on this principle, for a chip not included in a test group with other chips, if it includes P1 and N1, then only during the first test will P1 be able to transmit the high voltage level provided by VDD, resulting in a "1" result. In the second test, since there is no high voltage level provided by VDD, the TSV is grounded through N1, resulting in a "0" result. If it includes P2 and N2, then similarly, in the first test, the TSV is grounded through N2, resulting in a "0" result. In the second test, the TSV is connected to the power supply through P2, resulting in a "1" result. Therefore, in this test method, for the top chip, the two test results are "1" and "0", respectively, which can be used to determine that the chip does not belong to the test group and is the top chip.

[0148] for Figure 9 The circuit shown can be implemented using the aforementioned charging and discharging modules. Therefore, in some embodiments, each chip includes both a charging and discharging module; a charging module and a discharging module are connected to one end of a TSV module, and / or a discharging module and a charging module are connected to the other end of the TSV module.

[0149] The test circuit is also used to perform a first test by connecting a charging module and a discharging module on both sides of the through-silicon via module 13 to obtain a first test result, and to perform a second test by connecting another charging module and another discharging module on both sides of the through-silicon via module 13 to obtain a second test result.

[0150] It should be noted that in order to achieve Figure 9 The function of the circuit shown in the embodiment of the present disclosure can also be connected to both the charging module and the discharging module at one end of the through silicon via module. In other words, both the discharging module and the charging module are set in each chip.

[0151] Specific as Figure 10 As shown, since the charging module can be implemented by a PMOS transistor, the charging module is represented by P, and since the discharging module can be implemented by an NMOS transistor, the discharging module is represented by N. For each TSV module 13 in the test group 11, both ends are connected to an N and a P. For the top chip (Die3), one end of its corresponding TSV module 13 is connected to both an N and a P. The function of the charging module here is similar to that of the aforementioned Strong P, and the function of the discharging module here is similar to that of the aforementioned Weak N.

[0152] In this way, a first test can be performed through the P at the first end and the N at the second end of the through silicon via module 13 (as shown by the dotted arrow), and a second test can be performed through the N at the first end and the P at the second end of the through silicon via module 13 (as shown by the solid arrow), and the first test results and the second test results can be obtained respectively. When used for judging the top-layer chip, if both test results are "1", it means that the corresponding chip is a non-top-layer chip. If the two test results are "1" and "0" respectively, it means that the corresponding chip is a top-layer chip. When testing the through silicon via module 13, if both test results are "1", it means that there is no abnormality in the through silicon via module 13. If the two test results are "1" and "0" respectively, it means that there is an abnormality in the through silicon via module 13.

[0153] Figure 11 The circuit structure diagram of another test circuit provided by the embodiment of the present disclosure is as follows. Figure 11 As shown, in some embodiments, the test circuit further includes a level monitoring module 19, wherein:

[0154] During the first test, the level monitoring module 19 is used to monitor the level value of the through silicon via module 13 and output the first test result according to the level value of the through silicon via module;

[0155] During the second test, the level monitoring module 19 is used to monitor the level value of the TSV module and output the second test result according to the level value of the TSV module.

[0156] It should be noted that, for the sake of distinction, the discharge module connected to the first end of the through silicon via module 13 is referred to as the discharge module 1411, the discharge module connected to the second end of the through silicon via module 13 is referred to as the discharge module 1412, the charging module connected to the first end of the through silicon via module 13 is referred to as the charging module 1512, and the charging module connected to the second end of the through silicon via module 13 is referred to as the charging module 1511. Figure 11 Connected to the first end of the through silicon via module 13, it can also be connected to the second end of the through silicon via module 13, which is not specifically limited here. Figure 11 The test circuit can also include Figure 7 The components of the circuit shown are not involved here and are therefore not shown.

[0157] like Figure 11 As shown, the charging module includes a third transistor T3, and the discharging module includes a fourth transistor T4, wherein:

[0158] The gate of the third transistor T3 is connected to the first driving signal PDRV, the first electrode of the third transistor T3 is connected to the through silicon via module 13, and the second electrode of the third transistor T3 is connected to the power supply module;

[0159] A gate of the fourth transistor T4 is connected to the second driving signal NDRV, a first electrode of the fourth transistor T4 is connected to the through silicon via module 13 , and a second electrode of the fourth transistor T4 is connected to the ground module.

[0160] The third transistor T3 is a PMOS transistor, the fourth transistor T4 is an NMOS transistor, and the on-resistance of the fourth transistor T4 is greater than the on-resistance of the third transistor T3.

[0161] It should be noted that in Figure 11 In the embodiment, the power supply module may include a third power supply module VDD3 and a fourth power supply module VDD4, and the grounding module may include a third grounding module VSS3 and a fourth grounding module VSS4. VDD3 and VDD4 (as well as the aforementioned VDD1 and VDD2) may be different modules or the same power supply, which is not specifically limited here. Similarly, VSS3 and VSS4 (as well as the aforementioned VSS1 and VSS2) may be different modules or the same ground terminal, which is not specifically limited here. The voltage level provided by VDD3 / VDD4 is a first value, and the voltage level provided by VSS3 / VSS4 is a second value, wherein the first value represents a high level of logic 1 and the second value represents a low level of logic 0.

[0162] by Figure 11 For example, during the first test, a first drive signal PDRV is provided to the control terminal of the charging module 1411 and a second drive signal NDRV is provided to the control terminal of the discharging module 1511, so that the level monitoring module 19 can detect the first value (high-level logic 1) and output the first test result as "1". During the second test, a first drive signal PDRV is provided to the control terminal of the charging module 1412 and a second drive signal NDRV is provided to the control terminal of the discharging module 1512, so that the level monitoring module 19 can detect the first value (high-level logic 1) and output the second test result as "1". In this way, both test results are "1", indicating that the corresponding test group does not contain the top chip. In other words, the test circuit is also used to determine that the test group corresponding to the test circuit does not contain the top chip if both the first test result and the second test result are the first value.

[0163] In addition, the embodiment of the present disclosure may further include a delay module and an AND logic module to delay the first test result until it is consistent with the timing of the second test result, and then perform an AND logic operation on the two test results, so that a flag signal can be output. Only when the first test result and the second test result are both "1" can a flag signal of "1" be output. Alternatively, the embodiment of the present disclosure may further include two level monitoring modules, which are used to output the first test result and the second test result respectively, and are not specifically limited here. In addition, in the embodiment of the present disclosure, the first test result and the second test result may also directly constitute a flag signal, that is, when the first test result and the second test result are both the first value, it indicates that the corresponding chipset does not contain a top-level chip.

[0164] Further, in Figure 11 In the embodiment, if only the first end of the through silicon via module 13 is connected to the charging module 1411 and the discharging module 1512, then during the first test, the third transistor T3 in the charging module 1411 is turned on, and the level monitoring module 19 can monitor the high level provided by VDD3 transmitted by the charging module 1411, thereby outputting the first test result as "1"; during the second test, the fourth transistor T4 in the discharging module 1512 is turned on, and the level monitoring module 19 can monitor the low level provided by VSS4 transmitted by the discharging module 1512, thereby outputting the second test result as "0".

[0165] Similarly, in Figure 11 In the embodiment, if only the second end of the through silicon via module 13 is connected to the charging module 1412 and the discharging module 1511, then during the first test, the fourth transistor T4 in the discharging module 1511 is turned on, and the level monitoring module 19 can monitor the low level provided by VSS3 transmitted by the discharging module 1511, thereby outputting the first test result as "0"; during the second test, the third transistor T3 in the charging module 1412 is turned on, and the level monitoring module 19 can monitor the high level provided by VDD4 transmitted by the charging module 1412, thereby outputting the second test result as "1".

[0166] In this way, it is possible to determine whether the chip is a top chip or whether the TSV module 13 has an abnormality based on the first test result and the second test result.

[0167] The present disclosure provides a test structure for use in a chip stack structure, wherein the chip stack structure includes a plurality of chips, wherein at least two chips form a test group, and the test structure includes a test circuit, wherein each test group has a test circuit, and each chip in the test group includes a portion of the test circuit, wherein the test circuit is used to test the test group, and if the portion of the test circuit included in each chip in the test group is effectively enabled and activated, the test circuit is activated and outputs a flag signal, wherein the flag signal indicates that the test group does not include a top chip. In this way, the chip stack structure is divided into test groups. If the test group includes at least two chips, then the portion of the test circuit included in the at least two chips can form a complete test circuit. Therefore, when testing, the portion of the test circuit included in each chip in the test group can be effectively enabled and activated. At this time, it can be confirmed that the test group does not include a top chip. For the top chip, since it does not form a test group with the other chips, correspondingly, the portion of the test circuit in the top chip cannot be effectively enabled and activated during testing. Therefore, whether the chip is a top chip can be determined based on whether the portion of the test circuit in the chip is effectively enabled and activated. Based on this approach, the top chip can be accurately and quickly identified, providing a basis for TSV testing and repair.

[0168] In another embodiment of the present disclosure, see Figure 12 , which shows a schematic diagram of the composition structure of another chip stacking structure 10 provided by an embodiment of the present disclosure. Figure 12 As shown, at least one test structure as described in any of the above embodiments is disposed in the chip stack structure 10 .

[0169] It should be noted that Figure 12 is Figure 4 Based on , at least one test structure is added. Figure 12 As shown, the dotted line in the figure divides the chip stacking structure into two parts, the test circuit and part of the test circuit on the left side of the dotted line constitute one test structure, and the test circuit and part of the test circuit on the right side of the dotted line constitute another test structure.

[0170] Furthermore, Figure 13 A schematic diagram of the composition structure of another chip stacking structure 10 provided in an embodiment of the present disclosure is provided. Figure 5 Based on this, at least one test structure is added. Figure 14 for Figure 13 A top view of any chip in the . Figure 13 and Figure 14As shown, in mass production, each chip includes a first test module 14 and a second test module 15, as well as multiple redundant first and second test modules. Thus, the chips are stacked face-to-face to form a chip stack structure 10. At least two test circuits can be formed between two chips in a test group 11. It will be appreciated that in the test circuit composed of the redundant first and second test modules, the first and second test modules are connected via redundant through-silicon via modules.

[0171] For example, Figure 13 Taking Base Die and Die0 in the example, the first test module 14 in Base Die and the second test module 15 in Die0 form one test circuit, and the first test module 14 in Die0 and the second test module 15 in Base Die form another test circuit. At the same time, the redundant first and second test modules in Base Die and Die0 also form multiple test loops. Die3, as the top chip, has first and second test modules 14 and 15 that cannot form a complete test circuit with other test modules.

[0172] In this way, after powering on all first test modules 14 and second test modules 15, if any test module in a chip outputs the first value, it indicates that the chip is not a top-layer chip. Since the top-layer chip does not form a test group, all test modules in it output the second value. Therefore, even if there is an abnormal TSV module 13, as long as there is one TSV module 13 in a test group that does not have an abnormality, a test result of the first value can be obtained, confirming that the corresponding chip is not a top-layer chip.

[0173] Furthermore, Figure 15 A schematic diagram of the composition structure of another chip stacking structure 10 provided in an embodiment of the present disclosure is provided. Figure 10 Based on this, at least one test structure is added. Figure 16 for Figure 15 A top view of any chip in the . Figure 15 and Figure 16 As shown, in mass production, each chip includes a P (charging module) and an N (discharging module), as well as several redundant P and N modules. Thus, the chips are stacked face-to-face to form a chip stack structure 10. At least two test circuits can be formed between two chips in a test group. It will be appreciated that in the test circuit consisting of two redundant N modules and two redundant P modules, the test circuits are connected via redundant through-silicon via modules.

[0174] For example, Figure 15 For example, in the example of the Base Die and Die0 in Figure 1, on the left side of the dotted line, the P and N pins in the Base Die and the P and N pins in Die0 form a single test circuit. On the right side of the dotted line, the P and N pins in Die0 and the P and N pins in the Base Die form another test circuit. Furthermore, the redundant P and N pins in the Base Die and Die0 form multiple test circuits, each containing two N pins and two P pins. Die3, as the top chip, has its P and N pins unable to form a complete test circuit on the left side of the dotted line, and its P and N pins also fail to form a complete test loop on the right side of the dotted line.

[0175] correspond Figure 15 , performing the first test (dashed arrow) and the second test (solid arrow) respectively. Table 1 shows the test results output by the partial test circuit corresponding to Die3 on the left side of the dashed line during the two tests. Table 2 shows the test results output by the partial test circuit corresponding to Die3 on the right side of the dashed line during the two tests. Table 3 shows the test results output by the test circuit corresponding to the test group consisting of Die1 and Die2 on the left side of the dashed line during the two tests. Table 4 shows the test results output by the test circuit corresponding to the test group consisting of Die1 and Die2 on the right side of the dashed line during the two tests.

[0176] Table 1

[0177]

[0178] Table 2

[0179]

[0180] Table 3

[0181]

[0182] Table 4

[0183]

[0184] As shown in Tables 3 and 4, during the first test, on the left side of the dashed line, the P in Die 1 and the N in Die 2 complete a circuit, resulting in a test result of "1." On the right side of the dashed line, the N in Die 1 and the P in Die 2 complete a circuit, resulting in a test result of "1." During the second test, on the left side of the dashed line, the N in Die 1 and the P in Die 2 complete a circuit, resulting in a test result of "1." On the right side of the dashed line, the P in Die 1 and the N in Die 2 complete a circuit, resulting in a test result of "1." Clearly, within the test group, since both P and N participate in the test and complete the circuit in each test, the test results outputted for both the first and second tests are "1."

[0185] As shown in Tables 1 and 2, during the first test, on the left side of the dashed line, although only the P pin in Die 3 is conducting and not the N pin, the P pin is able to provide a high level, resulting in a test result of "1." On the right side of the dashed line, only the N pin is conducting and not the P pin, and the N pin cannot provide a high level, resulting in a test result of "0." During the second test, on the left side of the dashed line, only the N pin is conducting and not the P pin, and the N pin cannot provide a high level, resulting in a test result of "0." On the right side of the dashed line, although only the P pin is conducting and not the N pin, the P pin can provide a high level, resulting in a test result of "1." This shows that for the top chip, which is not part of a test group with other tests, the two test results are "1" and "0," respectively, allowing the top chip to be identified.

[0186] That is, as listed in Tables 1 to 4, the chips whose test results are both 1 are non-top-level chips, and the chips whose test results are 1 / 0 and 0 / 1 are top-level chips.

[0187] In addition, it should be noted that within a chip, only one of the N and P terminals connected to the same end of the same TSV module 13 will be turned on during a test. For example, on the left side of Die1, only the P terminal will be turned on in the first test, and only the N terminal will be turned on in the second test.

[0188] Thus, after performing the first and second tests, if both test results for any test circuit are "1," the corresponding chip is not a top-layer chip, while the test results for the top-layer chip include both "1" and "0." Thus, even if an abnormal TSV module 13 exists, as long as at least one TSV module 13 within a test group is normal, both test results will be "1," confirming that the corresponding chip is not a top-layer chip.

[0189] It should also be noted that in the embodiment of the present disclosure, the TSV module for determining whether the chip is a top chip is the same as the Figure 1 The TSVs shown in the figure are different. After the top chip is determined through this solution, the TSV test points are connected according to the top chip and the bottom chip (logic chip) to Figure 1 The TSV shown is tested.

[0190] In short, the embodiment of the present disclosure relates to the problem of determining the top chip of face-to-face stacked DRAM. The purpose of this embodiment is to find a solution that is independent of the chip ID and has a high fault tolerance rate. Figure 14 As shown, the first test module and the second test module are placed at both ends of the symmetry line. Figure 13As shown, a test circuit is formed between Base Die and Die0, and a test circuit is formed between Die1 and Die2. In the case of DRAM stacking 4 layers of memory chips, only the top chip Die3 does not form a test circuit with other chips. In the case of sufficient redundancy (Dummy), as long as it is detected that one set of test circuits can obtain a flag signal (Pass Flag), it can be considered that the chip in this layer is not the top chip. Correspondingly, Die3 does not form a loop with any chip, so all the first test modules and the second test modules obtain abnormal test results (Fail Flag). Therefore, Die3 is the top chip. For Figure 15 and Figure 16 The same is true for the structure shown.

[0191] This approach is not only simple but also highly redundant, enabling immediate detection as soon as the chip is powered on. The top-level information quickly determined based on the test results can then be used to test and repair other TSVs, including those used to transmit chip IDs.

[0192] In another embodiment of the present disclosure, see Figure 17 , which shows a flow chart of a testing method provided by an embodiment of the present disclosure. Figure 17 As shown, the method may include:

[0193] S1001: Testing the test group through the test circuit. If part of the test circuit included in each chip in the test group is effectively enabled, the test circuit is started and outputs a flag signal. The flag signal indicates that the test group does not include the top chip.

[0194] In some embodiments, testing the test group may include:

[0195] Determine a first test result according to a voltage change at one end of the through silicon via module, the first test result being used to indicate whether the first test module is effectively enabled and started;

[0196] Determine a second test result according to a voltage change at the other end of the through silicon via module, where the second test result is used to indicate whether the second test module is effectively enabled and started;

[0197] The voltage change at both ends of the through silicon via module is provided by the first test module and the second test module.

[0198] In some embodiments, the method may further include: determining that an abnormality exists in the through silicon via module if at most one of the first test result and the second test result is a first value.

[0199] In some embodiments, determining whether a TSV module is abnormal may include:

[0200] If the first test result and the second test result are both the second value, it is determined that there is an abnormality in the bidirectional transmission of the through silicon via module;

[0201] If one of the first test result and the second test result is the first value and the other is the second value, it is determined that a unidirectional transmission anomaly exists in the through silicon via module.

[0202] In some embodiments, the method may further include: performing an AND logic operation on the first test result and the second test result, and outputting a flag signal.

[0203] In some embodiments, testing the test group may include:

[0204] A first test is performed by connecting a charging module and a discharging module on both sides of the through silicon via module to obtain a first test result, and a second test is performed by connecting another charging module and another discharging module on both sides of the through silicon via module to obtain a second test result.

[0205] In some embodiments, the method may further include: if the first test result and the second test result are both the first value, determining that the test group corresponding to the test circuit does not include the top chip.

[0206] It should be noted that the test method provided in the embodiment of the present disclosure can be applied to the test structure provided in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please understand them according to the description of the aforementioned embodiment.

[0207] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0208] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0209] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0210] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0211] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0212] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0213] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A test structure, characterized in that: Applied to a chip stacking structure, the chip stacking structure includes multiple chips, at least two of the chips constitute a test group, the test structure includes a test circuit, each test group has one test circuit, and each chip in the test group includes part of the test circuit, wherein: The test circuit is used to test the test group. If part of the test circuit contained in each chip in the test group is effectively enabled and started, the test circuit is started and outputs a flag signal, and the flag signal indicates that the test group does not contain the top chip.

2. The test structure according to claim 1, characterized in that A first test module or a second test module is provided in each of the chips, and each of the chips is connected to a through-silicon via module. When the test group includes two chips, the two chips are connected through the through-silicon via module. The test circuit corresponding to the test group includes the first test module and the second test module. The first test module and the second test module are respectively provided in the two chips, and the two ends of the through-silicon via module are respectively connected to the first test module and the second test module.

3. The test structure according to claim 2, wherein: The first test module is configured to determine a first test result based on a voltage change at one end of the through silicon via module connected to the first test module, wherein the first test result is used to indicate whether the first test module is effectively enabled and started; The second test module is configured to determine a second test result based on a voltage change at the other end of the through silicon via module connected to the second test module, wherein the second test result is used to indicate whether the second test module is effectively enabled and started; The voltage change across the through silicon via module is provided by the first test module and the second test module.

4. The test structure according to claim 3, characterized in that The test circuit is further configured to determine that an abnormality exists in the through silicon via module if at most one of the first test result and the second test result is a first value.

5. The test structure according to claim 4, wherein: The test circuit is further configured to determine that abnormalities exist in both bidirectional transmissions of the through silicon via module connected to the test circuit if both the first test result and the second test result are second values; The test circuit is further configured to determine that a unidirectional transmission anomaly exists in the through silicon via module connected to the test circuit if one of the first test result and the second test result is a first value and the other is a second value.

6. The test structure according to claim 2, characterized in that The first test module includes a charging module and a first trigger module, and the second test module includes a discharging module and a second trigger module; wherein: The charging module is configured to charge the connected through silicon via module to a first level after the first trigger module and the second trigger module receive a power-on signal; The discharging module is configured to discharge the TSV module to a second level after the charging module charges the TSV module; The first trigger module is configured to perform trigger processing according to the first level and the second level to obtain a first test result; The second trigger module is configured to perform trigger processing according to the first level and the second level to obtain a second test result.

7. The test structure according to claim 6, wherein: The first trigger module includes a first trigger and a first inverter, wherein a clock input terminal of the first trigger is connected to an output terminal of the first inverter, an input terminal of the first inverter is connected to the through silicon via module and the charging module, an input terminal of the first trigger is connected to a first power supply module, and an output terminal of the first trigger is used to output the first test result; The second trigger module includes a second trigger and a second inverter, the clock input end of the second trigger is connected to the output end of the second inverter, the input end of the second inverter is connected to the through silicon via module and the discharge module, the input end of the second trigger is connected to the second power supply module, and the output end of the second trigger is used to output the second test result.

8. The test structure according to claim 7, characterized in that The test circuit further includes an AND logic module, wherein a first input terminal of the AND logic module is connected to the output terminal of the first trigger, and a second input terminal of the AND logic module is connected to the output terminal of the second trigger, wherein: The AND logic module is used to perform an AND logic operation on the first test result and the second test result, and output the flag signal.

9. The test structure according to claim 7, wherein: The first trigger module further includes a first transistor, the input end of the first inverter is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the first grounding module, and the gate of the first transistor is connected to the inverted signal of the power signal; The second trigger module further includes a second transistor, the input end of the second inverter is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to the second grounding module, and the gate of the second transistor is connected to the inverted signal of the electrical signal.

10. The test structure according to claim 7, characterized in that: The first trigger module further includes a third inverter, and the second trigger module further includes a fourth inverter, wherein: The input end of the third inverter is connected to the output end of the first inverter, and the output end of the third inverter is connected to the input end of the first inverter; The input end of the fourth inverter is connected to the output end of the second inverter, and the output end of the fourth inverter is connected to the input end of the second inverter.

11. The test structure according to claim 10, characterized in that: The control end of the charging module is connected to a first driving signal, and the control end of the discharging module is connected to a second driving signal.

12. The test structure according to claim 11, characterized in that Each of the chips includes the charging module and the discharging module; and one of the charging module and the discharging module are connected to one end of the through silicon via module, and / or one of the discharging module and the charging module are connected to the other end of the through silicon via module.

13. The test structure according to claim 12, characterized in that The test circuit is also used to perform a first test by connecting the charging module and the discharging module on both sides of the through-silicon via module to obtain a first test result, and to perform a second test by connecting another charging module and another discharging module on both sides of the through-silicon via module to obtain a second test result.

14. The test structure according to claim 13, characterized in that The charging module includes a third transistor, and the discharging module includes a fourth transistor, wherein: The gate of the third transistor is connected to the first driving signal, the first electrode of the third transistor is connected to the through silicon via module, and the second electrode of the third transistor is connected to the power supply module; The gate of the fourth transistor is connected to the second driving signal, the first electrode of the fourth transistor is connected to the through silicon via module, and the second electrode of the fourth transistor is connected to the ground module.

15. The test structure according to claim 13, characterized in that The test circuit further includes a level monitoring module, wherein: The level monitoring module is configured to monitor the level value of the through silicon via module during the first test, and output the first test result according to the level value of the through silicon via module; The level monitoring module is further configured to monitor the level value of the TSV module during the second test, and output the second test result according to the level value of the TSV module.

16. The test structure according to claim 15, characterized in that The test circuit is further configured to determine that the test group corresponding to the test circuit does not include a top chip if both the first test result and the second test result are first values.

17. The test structure according to any one of claims 1 to 16, characterized in that: The stacking mode between the multiple chips is face-to-face stacking, and the connection mode between two adjacent chips that do not belong to the same test group is hybrid bonding.

18. A chip stacking structure, characterized in that: The chip stacking structure includes a plurality of chips, and at least one test structure according to any one of claims 1 to 17 is disposed in the chip stacking structure.

19. A testing method, characterized in that: Applied to the test circuit according to any one of claims 1 to 17, the method comprises: The test group is tested by the test circuit. If part of the test circuit included in each chip in the test group is effectively enabled and started, the test circuit is started and outputs a flag signal, which indicates that the test group does not include the top chip.

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