Manufacturing Method and Structure of a Low Dark Current Photoelectric Triode

Abstract

The present invention discloses a manufacturing method and structure of a low dark current phototransistor, belonging to the semiconductor field. The present invention adopts a design of a high-concentration boron region and a manufacturing process of low-resistivity epitaxy. The process includes the following steps: preparation of a low-resistivity epitaxial wafer, wafer cleaning, field oxidation, high-concentration boron region implantation, high-concentration boron region diffusion, light-boron base region implantation, light-boron base region diffusion, emitter region implantation, emitter region diffusion, antireflection film layer deposition, photolithography and etching of the contact hole region, metal deposition, photolithography and etching of the metal pad region, and metallization alloying. The structure of the obtained chip is of the N+-N--P--N+ type. The present invention appropriately reduces the resistivity of the top-layer epitaxy, increases the doping concentration on the collector region side, effectively reduces the collector junction leakage current; at the same time, a high-concentration boron region structure is added in the chip design, which increases the doping concentration on the base region side of the collector junction, effectively reduces the collector junction leakage current, improves the dark current performance of the chip, and meets the application requirements in the high-temperature field.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a manufacturing method and structure of a low dark current phototransistor. Background Art

[0002] A phototransistor chip can receive an optical signal to generate a photocurrent, which is then amplified and output as an electrical signal, thereby realizing the conversion and transmission of optical-electrical signals; it has the advantages of high sensitivity, long life, strong anti-interference ability, etc.; it is mainly applied to market fields such as optocouplers, security, whiteboards, and optical axes. Among them, the market demand for optocoupler products is the largest. Because it can be used in combination with IR to achieve electro-optical-electrical conversion and electrical isolation, it is currently widely used in products such as household appliances, system instruments, power management, and MCU port isolation.

[0003] The dark current of existing phototransistor chips is usually relatively large, reaching the level of several 10 nA or even larger. The leakage performance will deteriorate further at high temperatures, resulting in a decrease in the current transmission efficiency at high temperatures and unable to meet the application requirements of high-temperature scenarios. Summary of the Invention

[0004] The purpose of the present invention is to provide a manufacturing method and structure of a low dark current phototransistor to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a manufacturing method and structure of a low dark current phototransistor, including:

[0006] Clean and spin-dry the N<111> single-layer or multi-layer epitaxial wafer, and load it into an oxidation process furnace tube for high-temperature thermal oxidation to form a dielectric oxide layer;

[0007] Spin-coat photoresist on the wafer after field oxidation, expose and develop the high-concentration boron region, perform high-dose boron implantation after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form a high-concentration boron region;

[0008] Spin-coat photoresist on the wafer after field oxidation, expose and develop the high-concentration boron region, perform medium-dose boron implantation in the low-concentration boron region after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form a low-concentration boron base region;

[0009] Spin-coat photoresist on the wafer after field oxidation, expose and develop the emitter region, perform high-dose phosphorus implantation in the emitter region after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form an emitter region and a peripheral cut-off ring region;

[0010] Deposit a SiN thin film with a preset thickness as a surface protection layer to prevent passivation, and at the same time, it is also used as an optical absorption and antireflection film;

[0011] Spin coat photoresist on the wafer after field oxidation, expose and develop the contact hole area, then remove the intermediate dielectric layer to open the contact hole area;

[0012] Deposit metal on the wafer, then spin coat photoresist, expose and develop the metal area, etch the metal with the photoresist on, and remove the surface photoresist after etching to form the metal pad area;

[0013] Perform high-temperature alloying on the wafer to reduce the Au-Si resistance.

[0014] In one embodiment, the concentrated boron region is disposed in an area at least 2 μm away from the emitter region, and the concentrated boron region completely surrounds the emitter region; the lateral spacing between the concentrated boron region and the cutoff ring region is not less than 2 μm.

[0015] In one embodiment, the concentrated boron region covers the light boron base region except the emitter region.

[0016] In one embodiment, after opening the contact hole area, detect the preset gain value of the wafer. If it does not reach the preset value, continue high-temperature diffusion above 950 °C until the preset value is reached.

[0017] In one embodiment, the thickness of the dielectric oxide layer is not less than 500 nm; the resistivity of the epitaxial layer is controlled not to exceed 12 ohm·cm; the implantation dose of the high-dose boron implantation is not less than 1E15; the implantation dose of the medium-dose boron implantation is 1E14 - 1E15; the implantation dose of the high-dose phosphorus implantation is not less than 1E15.

[0018] In one embodiment, in the process of forming the metal pad area, the deposited metal thickness is at least 2000 nm.

[0019] In one embodiment, the temperature range of the alloying is 380 - 530 °C.

[0020] The present invention also provides a low dark current phototransistor structure, including a substrate, an epitaxial layer, a field oxide layer, an emitter region, a light boron base region, a concentrated boron region, a cutoff ring region, a dielectric oxide layer, an emitter oxide layer, a contact hole area, a surface protection layer, and a metal pad area;

[0021] The epitaxial layer is disposed on the top outer surface of the substrate, the field oxide layer is disposed on the top outer surface of the epitaxial layer, and the emitter region is disposed on the top inner surface of the epitaxial layer; the light boron base region is disposed on the top inner surface of the epitaxial layer and completely surrounds the emitter region; the heavy boron region is disposed on the top inner surface of the epitaxial layer and covers the light boron base region except the emitter region, and a sufficient lateral spacing is left between the heavy boron region and the emitter region; the cutoff ring region is disposed along the entire circumference of the epitaxial layer on the top inner surface of the epitaxial layer, and a sufficient lateral distance is left between the cutoff ring region and the heavy boron region; the dielectric oxide layer is disposed on the upper surface of the epitaxial layer where the light boron base region is located; the emitter region oxide layer is disposed on the top outer surface of the emitter region; the contact hole region is disposed on the emitter region and the light boron base region; the surface protection layer is disposed on the entire chip surface except the contact hole region; the metal pad region is disposed on the contact hole region.

[0022] In the manufacturing method and structure of the low dark current phototransistor provided by the present invention, through design optimization and process improvement, a low dark current phototransistor chip with a dark current less than 1 nA and a temperature drift of the current transfer efficiency less than 30% can be obtained, improving the photoelectric transmission performance of the chip and meeting the application requirements in the high temperature field. Compared with the prior art, the present invention appropriately reduces the resistivity of the epitaxial layer, increases the doping concentration on the collector side, effectively reduces the collector junction leakage current; at the same time, a heavy boron region structure is added in the chip design, increasing the doping concentration on the base side of the collector junction, effectively reducing the collector junction leakage current, and improving the dark current performance of the chip. Brief Description of the Drawings

[0023] Figure 1 is a schematic flow chart of a manufacturing method of a low dark current phototransistor provided by the present invention;

[0024] Figure 2 is a schematic plan view of a low dark current phototransistor provided by the present invention;

[0025] Figure 3 is a schematic cross-sectional view of a low dark current phototransistor provided by the present invention. Detailed Description of the Embodiments

[0026] The following further describes in detail a manufacturing method and structure of a low dark current phototransistor provided by the present invention with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0027] The present invention provides a preparation method for a low dark current phototransistor structure, and its process is as Figure 1As shown in the figure, it includes the following steps:

[0028] Clean and spin-dry a single-layer or multi-layer epitaxial wafer of N<111> (including substrate 12 and epitaxial layer 11), and perform high-temperature thermal oxidation to form a field oxide layer 9 with a thickness exceeding 500 nm;

[0029] Spin-coat photoresist on the wafer after field oxidation, expose and develop the high-concentration boron region, perform high-dose boron implantation after removing the thick oxide layer and growing thin oxide, where the implantation dose ≥ 1E15; after implantation, perform high-temperature diffusion at a temperature above 950 °C to form a high-concentration boron region 6;

[0030] Spin-coat photoresist on the wafer, expose and develop the high-concentration boron region, perform medium-dose boron implantation in the light-boron region after removing the thick oxide layer and growing thin oxide, where the implantation dose is 1E14 - 1E15; after implantation, perform high-temperature diffusion at a temperature above 950 °C to form a light-boron base region 5;

[0031] Spin-coat photoresist on the wafer, expose and develop the emitter region, perform high-dose phosphorus implantation in the emitter region after removing the thick oxide layer and growing thin oxide, where the implantation dose ≥ 1E15; after implantation, perform high-temperature diffusion at a temperature above 950 °C to form an emitter region 2 and a peripheral cutoff ring region 1;

[0032] Deposit a SiN thin film with a preset thickness as a surface protection layer 8 for anti-passivation, and it can also be used as an optical absorption and antireflection film;

[0033] Spin-coat photoresist on the wafer, expose and develop the contact hole region, then remove the intermediate dielectric layer to open the contact hole region 3. At this time, the preset gain value of the wafer can be detected. If it does not reach the preset value, high-temperature diffusion above 950 °C can be continued until the preset value is reached;

[0034] Select sputtering or evaporation process to deposit metal on the wafer. Generally, the metal thickness is not less than 2000 nm. Then spin-coat photoresist, expose and develop the metal region, perform metal etching with the photoresist on, and remove the surface photoresist after etching to form a metal pad region 4;

[0035] Perform high-temperature alloying on the wafer to reduce the metal-semiconductor resistance. The alloying temperature is generally not higher than 530 °C and not lower than 380 °C.

[0036] The present invention further provides a low-dark-current phototransistor structure. Refer to Figure 2 and Figure 3, the low dark current phototransistor structure includes a substrate 12, an epitaxial layer 11, a field oxide layer 9, an emitter region 2, a light boron base region 5, a heavy boron region 6, a cutoff ring region 1, a dielectric oxide layer 7, an emitter region oxide layer 10, a contact hole region 3, a surface protection layer 8, and a metal pad region 4. The epitaxial layer 11 is disposed on the top outer surface of the substrate 12, the field oxide layer 9 is disposed on the top outer surface of the epitaxial layer 11, and the emitter region 2 is disposed on the top inner surface of the epitaxial layer 11; the light boron base region 5 is disposed on the top inner surface of the epitaxial layer 11 and completely surrounds the emitter region 2; the heavy boron region 6 is disposed on the top inner surface of the epitaxial layer 11 and completely surrounds the light boron base region 5, and a sufficient lateral spacing is left between the heavy boron region 6 and the emitter region 2; the cutoff ring region 1 is disposed in a circle along the epitaxial layer 11 on the top inner surface of the epitaxial layer 11, and a sufficient lateral distance is left between the cutoff ring region 1 and the heavy boron region 6; the dielectric oxide layer 7 is disposed on the upper surface of the epitaxial layer 11 at the position where the light boron base region 5 is located; the emitter region oxide layer 10 is disposed on the top outer surface of the emitter region 2; the contact hole region 3 is disposed on the emitter region 2 and the light boron base region 5; the surface protection layer 8 is disposed on the entire chip surface except the contact hole region 3; the metal pad region 4 is disposed on the contact hole region 3.

[0037] Currently, the dark current of phototransistor chips is usually relatively large, and the leakage performance will further deteriorate at high temperatures, resulting in a decrease in the current transmission efficiency at high temperatures and unable to meet the application requirements of high-temperature scenarios. By designing the heavy boron region structure and appropriately reducing the resistivity of the epitaxial material during the manufacturing process, the present invention can obtain a low dark current phototransistor chip with a dark current less than 1 nA and a high-temperature temperature drift of the current transmission efficiency less than 30%, effectively solving the problem of relatively large dark current.

[0038] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A manufacturing method of a low dark current phototransistor, characterized in that, It includes the following steps: Clean and spin-dry the N<111> single-layer or multi-layer epitaxial wafers, load them into the oxidation process furnace tube for high-temperature thermal oxidation to form a dielectric oxide layer; Spin-coat photoresist on the wafer after field oxidation, expose and develop the high-concentration boron region, perform high-dose boron implantation after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form a high-concentration boron region; Spin-coat photoresist on the wafer after field oxidation, expose and develop the high-concentration boron region, perform medium-dose boron implantation in the light-boron base region after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form a light-boron base region; Spin-coat photoresist on the wafer after field oxidation, expose and develop the emitter region, perform high-dose phosphorus implantation in the emitter region after removing the thick oxide layer and growing thin oxide, and then perform high-temperature diffusion above 950 °C after implantation to form the emitter region and the cutoff ring region on the periphery; Deposit a SiN thin film with a preset thickness as a surface protection layer to prevent passivation and also as an anti-reflection film for light absorption; Spin-coat photoresist on the wafer after field oxidation, expose and develop the contact hole region, and then remove the intermediate dielectric layer to open the contact hole region; Deposit metal on the wafer, then spin-coat photoresist, expose and develop the metal region, etch the metal with the photoresist on, and remove the surface photoresist after etching to form a metal pad region; Perform high-temperature alloying on the wafer to reduce the metal-semiconductor resistance.

2. The manufacturing method of the low dark current phototransistor according to claim 1, characterized in that The high-concentration boron region is set in an area at least 2 um away from the emitter region, and the high-concentration boron region completely surrounds the emitter region; the lateral spacing between the high-concentration boron region and the cutoff ring region is not less than 2 um.

3. The manufacturing method of the low dark current phototransistor according to claim 2, characterized in that, The high-concentration boron region covers the light-boron base region except the emitter region.

4. The manufacturing method of the low dark current phototransistor according to claim 1, characterized in that, After opening the contact hole region, detect the preset gain value of the wafer. If it does not reach the preset value, continue high-temperature diffusion above 950 °C until the preset value is reached.

5. The manufacturing method of the low dark current phototransistor according to claim 1, characterized in that, The thickness of the dielectric oxide layer is not less than 500 nm; the implantation dose of the high-dose boron implantation is not less than 1E15; the implantation dose of the medium-dose boron implantation is 1E14 - 1E15; the implantation dose of the high-dose phosphorus implantation is not less than 1E15.

6. The manufacturing method of the low dark current phototransistor according to claim 1, characterized in that, In the process of forming the metal pad region, the deposited metal thickness is at least 2000 nm.

7. The manufacturing method of the low dark current phototransistor according to claim 1, characterized in that, The temperature range of the alloy is 380 - 530 °C.

8. A low dark current phototransistor structure, characterized in that, It includes a substrate (12), an epitaxial layer (11), a field oxide layer (9), an emitter region (2), a light-boron base region (5), a high-concentration boron region (6), a cutoff ring region (1), a dielectric oxide layer (7), an emitter oxide layer (10), a contact hole region (3), a surface protection layer (8), and a metal pad region (4); The epitaxial layer (11) is disposed on the top outer surface of the substrate (12), the field oxide layer (9) is disposed on the top outer surface of the epitaxial layer (11), and the emitter region (2) is disposed on the top inner surface of the epitaxial layer (11); the light boron base region (5) is disposed on the top inner surface of the epitaxial layer (11) and completely surrounds the emitter region (2); the heavy boron region (6) is disposed on the top inner surface of the epitaxial layer (11) and covers the light boron base region (5) except the emitter region (2), and a sufficient lateral spacing is left between the heavy boron region (6) and the emitter region (2); the cutoff ring region (1) is disposed along the epitaxial layer (11) in a circle on the top inner surface of the epitaxial layer (11), and a sufficient lateral distance is left between the cutoff ring region (1) and the heavy boron region (6); the dielectric oxide layer (7) is disposed on the upper surface of the epitaxial layer (11) where the light boron base region (5) is located; the emitter region oxide layer (10) is disposed on the top outer surface of the emitter region (2); the contact hole region (3) is disposed on the emitter region (2) and the light boron base region (5); the surface protection layer (8) is disposed on the entire chip surface except the contact hole region (3); the metal pad region (4) is disposed on the contact hole region (3).

Images