Switching power supply current detection circuitry

Abstract

The application discloses a switching power supply current detection circuit system and relates to the technical field of switching power supplies. A basic topology circuit unit comprises a first metal-oxide semiconductor field effect transistor and a controller; the drain electrode of the first metal-oxide semiconductor field effect transistor is connected to an input voltage, and the third pin of the controller is connected to a starting voltage; the first end of a current mirror unit is connected to the input voltage, and the second end is connected to the third pin; the voltage transmission unit is further connected to the first pin and the second pin of the controller; a first enable signal controls the entering of a current detection effective stage or an invalid stage, and a second enable signal controls the turn-on or turn-off of the first metal-oxide semiconductor field effect transistor; the current mirror unit mirrors the current flowing through the first metal-oxide semiconductor field effect transistor. The application reduces the power loss of the switching power supply and realizes the lossless detection of the switching power supply.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and in particular to a switching power supply current detection circuit system. Background Technology

[0002] Switching power supplies utilize the switching on and off of switches to control the storage and release of electrical energy in inductive devices, and are widely used in electronic equipment.

[0003] With the rapid development of semiconductor technology, especially the widespread application of large-scale integrated circuits, electronic devices are trending towards miniaturization. Simultaneously, higher demands are being placed on the efficiency of switching power supplies. High frequency and high efficiency are the two major directions in the development of switching power supplies. The advantage of high frequency lies in the fact that, with a fixed total energy storage, more energy storage cycles are possible, resulting in smaller single-cycle energy storage capacity for the inductors in the switching power supply, requiring less inductance. Smaller inductors lead to a smaller overall size of the switching power supply, greatly expanding its application scenarios. The advantage of high efficiency lies in the superior performance of the switching power supply in terms of energy consumption and heat dissipation, resulting in lower energy consumption, less heat generation, and higher overall efficiency.

[0004] Switching power supplies have three basic topologies: BUCK topology, BOOST topology, or BUCK-BOOST topology. For an example of BUCK topology, please refer to [link to relevant documentation]. Figure 1 HS stands for high-side metal-oxide-semiconductor field-effect transistor (MOSFET), and low-side MOSFET (in... Figure 1 (represented by LS in Chinese), controller and inductor (in Figure 1 The topology of the BUCK is represented by L.

[0005] Traditional switching power supplies use series resistors ( Figure 1 The current signal is converted into a voltage signal in the manner represented by Rsns, and then amplified ( Figure 1 (represented by EA) The amplified output detection result is then transmitted to the controller to participate in circuit control. Figure 1 In this diagram, Vin represents the input voltage, Vout represents the output voltage, Cout represents the output capacitance, and SW represents the node voltage at the connection point between the high-side MOSFET and the low-side MOSFET.

[0006] While traditional solutions have simple internal circuit designs, they involve destructive testing. Although the power loss through the series resistor is small when the current is small, the power loss through the series resistor increases quadratically when the current is large, which has a significant impact on the efficiency of the switching power supply. Summary of the Invention

[0007] The purpose of this invention is to provide a switching power supply current detection circuit system to reduce the power loss of the switching power supply, achieve non-destructive detection of the switching power supply current, and improve the efficiency of the switching power supply.

[0008] To achieve the above objectives, embodiments of the present invention provide the following solutions:

[0009] A switching power supply current detection circuit system includes a basic topology circuit unit and a current detection circuit system; the current detection circuit system includes a voltage transmission unit and a current mirror unit, wherein:

[0010] The basic topology circuit unit is used to adjust the voltage; the basic topology circuit unit includes at least a first metal-oxide-semiconductor field-effect transistor and a controller connected in series; the drain of the first metal-oxide-semiconductor field-effect transistor is connected to the input voltage, and the third pin of the controller is connected to the start-up voltage;

[0011] The first terminal of the current mirror unit is connected to the input voltage, and the second terminal of the current mirror unit is connected to the third pin through the voltage transmission unit;

[0012] The voltage transmission unit is also connected to the first pin and the second pin of the controller respectively; the second pin is also connected to the gate of the first metal-oxide-semiconductor field-effect transistor; wherein, the first enable signal output by the first pin is used to control the current detection circuit system to enter the current detection active stage or the current detection inactive stage, and the second enable signal output by the second pin is used to control the first metal-oxide-semiconductor field-effect transistor to be turned on or off.

[0013] The voltage transmission unit is configured to: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned on, control the current mirror unit to enter the working state; and during the current detection activation phase, while the first metal-oxide-semiconductor field-effect transistor is turned on, transmit the start-up voltage at the third pin to the second terminal of the current mirror unit.

[0014] The current mirroring unit is used to mirror the current flowing through the first metal-oxide-semiconductor field-effect transistor in the operating state.

[0015] Optionally, the voltage transmission unit is specifically configured to: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned on, control the current mirror unit to enter the working state, wherein the start time of the current mirror unit entering the working state is later than the start time of the first metal-oxide-semiconductor field-effect transistor being turned on; and during the current detection activation phase, while the first metal-oxide-semiconductor field-effect transistor is turned on, transmit the start-up voltage at the third pin to the second terminal of the current mirror unit.

[0016] Optionally, the rising edge of the second enable signal is used to trigger the first metal-oxide-semiconductor field-effect transistor to turn on, and the falling edge of the second enable signal is used to trigger the first metal-oxide-semiconductor field-effect transistor to turn off.

[0017] Optionally, the voltage transmission unit is further configured to: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned off, control the current mirror unit to enter a non-operating state.

[0018] Optionally, the voltage transmission unit includes a timing controller and a transmission unit, wherein:

[0019] The timing controller has two input terminals connected to the second pin and the first pin, respectively;

[0020] The first end of the transmission unit is connected to the output end of the timing controller, the second end of the transmission unit is connected to the third pin, and the third end of the transmission unit is connected to the second end of the current mirror unit.

[0021] The timing controller is configured to: during the current detection activation phase, output a third enable signal based on the second enable signal; the third enable signal is used to control the current mirror unit to enter the working state;

[0022] The transmission unit is used to transmit the startup voltage at the third pin to the second terminal of the current mirror unit during the conduction of the first metal-oxide-semiconductor field-effect transistor.

[0023] Optionally, the transmission unit includes:

[0024] A third metal-oxide-semiconductor field-effect transistor (MOSFET) has its gate connected to the output of the timing controller, and its source connected to the source of the second MOSFET. The gate voltage of the third MOSFET is determined by the third enable signal.

[0025] The second diode has its anode connected to the input voltage and its cathode connected to the drain of the third metal-oxide-semiconductor field-effect transistor.

[0026] A first resistor, with its first terminal connected to the input voltage;

[0027] The third diode, wherein the positive terminal of the third diode is connected to the second terminal of the first resistor;

[0028] A fourth metal-oxide-semiconductor field-effect transistor, wherein the gate of the fourth metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the first resistor; and the source of the fourth metal-oxide-semiconductor field-effect transistor is connected to the negative terminal of the third diode.

[0029] The second resistor is connected to the drain of the fourth metal-oxide-semiconductor field-effect transistor and the third pin, respectively.

[0030] Optionally, the rising edge of the third enable signal is used to trigger the current mirror unit to enter the working state, and the falling edge of the third enable signal is used to trigger the current mirror unit to enter the non-working state; furthermore, the rising edge of the third enable signal lags behind the rising edge of the second enable signal, and the falling edge of the third enable signal coincides with the falling edge of the second enable signal; the rising edge of the third enable signal corresponds to the start time; and the rising edge of the second enable signal corresponds to the conduction start time.

[0031] Optionally, the current mirror unit includes:

[0032] A fifth metal-oxide-semiconductor field-effect transistor, wherein the drain of the fifth metal-oxide-semiconductor field-effect transistor is connected to the input voltage, and the gate of the fifth metal-oxide-semiconductor field-effect transistor is connected to the negative terminal of the third diode;

[0033] An amplifier, wherein the positive input terminal of the amplifier is connected to the source of the fifth metal-oxide-semiconductor field-effect transistor, and the negative input terminal of the amplifier is connected to the drain of the third metal-oxide-semiconductor field-effect transistor;

[0034] A sixth metal-oxide-semiconductor field-effect transistor (MOSFET) is provided, wherein the drain of the sixth MOSFET is connected to the source of the fifth MOSFET, the gate of the sixth MOSFET is connected to the output of the amplifier, and the source of the sixth MOSFET is connected to the subsequent circuit of the basic topology circuit unit.

[0035] Optionally, the third metal-oxide-semiconductor field-effect transistor includes a first parasitic diode; the positive terminal of the first parasitic diode is connected to the source of the third metal-oxide-semiconductor field-effect transistor, and the negative terminal of the first parasitic diode is connected to the drain of the third metal-oxide-semiconductor field-effect transistor.

[0036] The fourth metal-oxide-semiconductor field-effect transistor includes a second parasitic diode; the positive terminal of the second parasitic diode is connected to the drain of the fourth metal-oxide-semiconductor field-effect transistor, and the negative terminal of the second parasitic diode is connected to the source of the fourth metal-oxide-semiconductor field-effect transistor.

[0037] Optionally, the basic topology circuit unit, the voltage transmission unit, and the current mirror unit are integrated in the controller.

[0038] According to specific embodiments provided by the present invention, the following technical effects are disclosed:

[0039] This invention provides a switching power supply current detection circuit system, including a basic topology circuit unit, a current mirror unit, and a voltage transmission unit. The components work together as follows:

[0040] In the basic topology circuit unit, the drain of the first metal-oxide-semiconductor field-effect transistor is connected to the input voltage, while the third pin of the controller is connected to the startup voltage. Simultaneously, the first terminal of the current mirror unit is connected to the aforementioned input voltage, and the second terminal is connected to the aforementioned third pin via a voltage transmission unit. The current mirror unit is not located on the path of the basic topology circuit unit.

[0041] During the current detection activation phase, the current mirror unit is used to mirror the current passing through the first metal-oxide-semiconductor field-effect transistor. Therefore, the current in the current mirror unit can be used for current detection. At the same time, as mentioned earlier, the current mirror unit is not located on the path of the basic topology circuit unit. In this way, no matter how large or small the current flowing through the current mirror unit is, it will not affect the current in the above path, thereby realizing non-destructive testing and improving the efficiency of the switching power supply. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1This is a schematic diagram of an existing switching power supply.

[0044] Figure 2 This is an exemplary structural diagram of a switching power supply current detection circuit system provided in an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the BUCK topology structure of the basic topology circuit unit provided in the embodiments of the present invention;

[0046] Figure 4 A schematic diagram of the BOOST topology structure of the basic topology circuit unit provided in the embodiments of the present invention;

[0047] Figure 5 A schematic diagram of the BUCK-BOOST topology of the basic topology circuit unit provided in the embodiments of the present invention;

[0048] Figure 6 A schematic diagram of the CCM current mode provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of the DCM current mode provided in an embodiment of the present invention;

[0050] Figure 8 A schematic diagram of the BCM current mode provided in an embodiment of the present invention;

[0051] Figure 9 The timing control logic diagram of the switching power supply current detection circuit system provided in the embodiment of the present invention is shown. Detailed Implementation

[0052] The structures and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0053] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0054] The purpose of this invention is to provide a switching power supply current detection circuit system to solve the problem of destructive testing of existing switching power supplies, realize non-destructive testing of switching power supply current, and improve the efficiency of switching power supplies.

[0055] Figure 2An exemplary structure of the aforementioned switching power supply current detection circuit system is shown, including a basic topology circuit unit (in... Figure 2 (represented by reference numeral 1) and a current detection circuit system; wherein, the current detection circuit system includes a voltage transmission unit (in Figure 2 (represented by reference numeral 2) and current mirror unit (in Figure 2 (represented by the number 3 in Chinese).

[0056] The connection relationship and function of the basic topology circuit unit 1, voltage transmission unit 2 and current mirror unit 3 are described below.

[0057] Basic topology circuit unit 1 is used to adjust the voltage. Specifically, basic topology circuit unit 1 can be a BUCK topology, a BOOST topology, or a BUCK-BOOST topology.

[0058] Figures 3 to 5 The diagrams sequentially illustrate the BUCK topology, BOOST topology, and BUCK-BOOST topology. Here, L represents an inductor, K1 represents switch 1, and K2 represents switch 2 (corresponding to...). Figure 1 (LS in the middle).

[0059] The BUCK topology described above can achieve a step-down transformation from input voltage (VIN) to output voltage (VOUT); the BOOST topology can achieve a step-up transformation from input voltage (VIN) to output voltage (VOUT); the BUCK-BOOST topology can achieve both a step-down transformation from input voltage (VIN) to output voltage (VOUT) and a step-up transformation from input voltage (VIN) to output voltage (VOUT).

[0060] Regardless of the topology, it must include at least: a first MOSFET and a controller (in Figure 2 (represented by 12 in Chinese). It should be noted that the first MOSFET is... Figure 1 HS indicates that, in Figure 2 The number 11 indicates that in Figures 3 to 5 The middle corresponds to switch 1 and is represented by K1.

[0061] Using the BUCK topology as an example, please refer to [link / reference]. Figure 2 The drain of the first MOSFET11 is connected to the input voltage (in Figure 2 The current flowing through the drain (i.e., the input current) is represented by Vin, and the third pin of controller 12 (in...) Figure 2 (represented by 123) is used to connect the start-up voltage (in Figure 2(This is represented by V_Boot). For other topologies, the first MOSFET 11 also has its drain connected to Vin, and the third pin of the controller 12 is also connected to V_Boot. The other components of the basic topology circuit unit 1 will be introduced later.

[0062] The following details the other parts of the basic topology circuit unit 1, specifically including: the second MOSFET (in Figure 2 The number 13 is used to represent the number, and its corresponding number is 13. Figure 3-5 K2 in the middle), the first diode (in Figure 2 (represented by 14 in the middle), the first capacitor (in Figure 2 (represented by 15), inductance (in) Figure 2 (represented by 16) and the second capacitor (in Figure 2 (represented by 17 in Chinese).

[0063] Please see again Figure 2 The gate of the second MOSFET 13 is connected to the fourth pin of the controller 12 (at... Figure 2 (represented by 124) is connected, and the fourth enable signal output from the fourth pin 124 (in) Figure 2 (represented by LS_EN) is used to control the turn-on or turn-off of the second MOSFET13; the drain of the second MOSFET13 is connected to the source of the first MOSFET11; the source of the second MOSFET13 is grounded.

[0064] The cathode of the first diode 14 is connected to the third pin 123, and the anode of the first diode 14 is used to input the voltage at the third node (in...). Figure 2 (represented by V_LDO in Chinese).

[0065] The input terminal of the first capacitor 15 is connected to the negative terminal of the first diode 14, and the first capacitor 15 is used to store electrical energy.

[0066] The input terminal of inductor 16 is connected to the source of the first MOSFET 11, the drain of the second MOSFET 13, and the output terminal of the first capacitor 15, respectively. The output terminal of inductor 16 is connected to the output terminal of the switching power supply. Inductor 16 is used to block AC current through DC current.

[0067] The input terminal of the second capacitor 17 is connected to the output terminal of the inductor 16. The second capacitor 17 is used for filtering and storing electrical energy.

[0068] The voltage transmission unit 2 is described below. In addition to the connection relationships described above, the voltage transmission unit 2 is also connected to the first pin of the controller 12 (in...). Figure 2 (represented by 121) and the second pin (in Figure 2 (represented by 122) are connected respectively.

[0069] The second pin 122 is also connected to the gate of the first MOSFET 11. The first enable signal output from the first pin 121 (in...) Figure 2 The second enable signal (represented by SNS_EN) is used to control the current detection circuit system to enter the current detection active stage or the current detection inactive stage. The second enable signal output from the second pin 122 (in...) Figure 2 (represented by HS_EN) is used to control the on or off state of the first MOSFET11.

[0070] The voltage transmission unit 2 is used to control the current mirror unit 3 to enter the working state after the first MOSFET 11 is turned on during the current detection activation phase; and to transmit the start-up voltage at the third pin 123 to the second end of the current mirror unit 3 during the current detection activation phase when the first MOSFET 11 is turned on.

[0071] The current mirror unit 3 is described below. The current mirror unit 3 is used to mirror the current flowing through the first MOSFET 11 under the above operating conditions.

[0072] The first terminal of the current mirror unit 3 is connected to the input voltage (Vin), and the second terminal of the current mirror unit 3 is connected to the third pin 123 through the voltage transmission unit 2.

[0073] By comparison, it can be seen that the drain of the first MOSFET 11 in the basic topology circuit unit 1 is connected to the input voltage, while the third pin 123 of the controller 12 is connected to the startup voltage. Simultaneously, the first terminal of the current mirror unit 3 is connected to the input voltage, just like the drain of the first MOSFET 11, and the second terminal is connected to the third pin 123 via the voltage transmission unit 2. Therefore, the current mirror unit 3 and the basic topology circuit unit 1 are connected in parallel between the input voltage and the third pin 123, and the current mirror unit 3 is not located on the path of the basic topology circuit unit 1.

[0074] As can be seen, in this embodiment, during the current detection activation phase, the current mirror unit 3 is used to mirror the current passing through the first MOSFET 11. Therefore, the current in the current mirror unit 3 can be used for current detection. At the same time, the current mirror unit 3 is not located on the path of the basic topology circuit unit. In this way, no matter how large or small the current flowing through the current mirror unit is, it will not affect the current in the above path, thereby realizing non-destructive detection and improving the efficiency of the switching power supply.

[0075] In other embodiments of the present invention, regarding the control of the current mirror unit 3 to enter the working state, the voltage transmission unit 2 is specifically configured to: control the start time of the current mirror unit 3 entering the working state to lag behind the turn-on start time of the first MOSFET 11. That is, to delay the control of the current mirror unit 3 to enter the working state. This avoids current and voltage glitches that may be generated during the switching of the power supply, reduces interference from current and voltage glitches, and improves the detection accuracy and stability of the switching power supply.

[0076] In other embodiments of the present invention, the voltage transmission unit 2 in all the above embodiments can also be used to: control the current mirror unit 3 to enter a non-operating state when the first MOSFET 11 is turned off during the current detection active phase. Of course, the current mirror unit 3 is also in a non-operating state during the current detection inactive phase.

[0077] The following will combine Figure 9 The timing control example shown illustrates the collaboration process between different parts of the system in this embodiment.

[0078] Please see Figure 9 The aforementioned current detection activation phase includes, for example, phases A, B, and C, while the current detection failure phase is exemplarily phase D. The duration of phase A is T_dly.

[0079] During the current detection activation phase, after the first MOSFET11 is turned on, the voltage transmission unit 2 delays the current mirror unit 3 to enter the working state (corresponding to...). Figure 9 In stage B of the current mirror unit 3, the start time of its operation is delayed until the turn-on start time of the first MOSFET 11. Figure 9 For example, the turn-on start time of the first MOSFET11 is the start time of stage A, and the start time of the current mirror unit 3 entering the working state is the start time of stage B. The difference between the two start times is T_dly.

[0080] Meanwhile, during the current detection activation phase, during the first MOSFET11 conduction period (including...) Figure 9 In stages A and B of the process, voltage transmission unit 2 also transmits the startup voltage at the aforementioned third pin 123 to the second terminal of current mirror unit 3. In the operating state, current mirror unit 3 is used to mirror the current flowing through the first MOSFET 11.

[0081] It should be noted that, in the non-operating state, the current mirror unit 3 cannot mirror the current flowing through the first MOSFET 11.

[0082] When the first MOSFET11 is turned off (i.e., entering phase C), the control current mirror unit 3 enters a non-operating state. Of course, during the current detection failure phase, the current mirror unit 3 is also in a non-operating state.

[0083] In summary, this embodiment of the invention uses a current mirror unit 3 to mirror the current in the first MOSFET 11 to achieve current detection. Furthermore, as mentioned earlier, the current mirror unit 3 is not located on the path of the basic topology circuit unit 1. Therefore, regardless of the magnitude of the current flowing through the current mirror unit 3, it will not affect the current in the path of the basic topology circuit unit 1, thus achieving non-destructive current detection. It also avoids power loss caused by series resistors, thereby improving the efficiency of the switching power supply.

[0084] Meanwhile, during the current detection activation phase, after the first MOSFET11 is turned on, the voltage transmission unit2 delays the current mirror unit3 to enter the working state, so that the start time of the current mirror unit3 entering the working state is later than the start time of the first MOSFET11 being turned on. This avoids the current and voltage glitches that may be generated during the switching of the power supply, reduces the interference of current and voltage glitches, and improves the detection accuracy and stability of the power supply.

[0085] In other embodiments of the present invention, the basic topology circuit unit 1, the voltage transmission unit 2, and the current mirror unit 3 may be integrated into the controller 12.

[0086] exist Figure 1 In the prior art shown, the series resistor is placed outside the controller 12, requiring the controller 12 to have one or two additional pins to connect to the series resistor, thus increasing the packaging cost of the controller 12. In this embodiment, the basic topology circuit unit 1, voltage transmission unit 2, and current mirror unit 3 are integrated into the controller 12, eliminating the need for one or two additional pins to connect to the series resistor. This reduces the packaging cost of the controller 12, thereby reducing the production cost of the switching power supply.

[0087] The enable signal is described below.

[0088] Please see Figure 9 The first enable signal (in) Figure 9 The rising edge of the SNS_EN signal (represented in the diagram) is used to trigger the current sensing circuit system to enter the current sensing active phase, and the falling edge of the first enable signal is used to trigger the current sensing circuit system to enter the current sensing inactive phase. Of course, in other examples, it is also possible to design the current sensing circuit system to enter the current sensing active phase with the falling edge of SNS_EN and to enter the current sensing inactive phase with the rising edge of SNS_EN.

[0089] In other embodiments of the present invention, please refer to Figure 9 When SNS_EN is high, the second enable signal (in) Figure 9 The rising edge of HS_EN (represented by HS_EN) is used to trigger the first MOSFET11 to turn on, and the rising edge of HS_EN corresponds to the start time of the first MOSFET11's turn-on. The falling edge of HS_EN is used to trigger the first MOSFET11 to turn off. Of course, in other examples, it is also possible to design the first MOSFET11 to turn on with the falling edge of HS_EN and to turn off with the rising edge of HS_EN.

[0090] In other embodiments of the present invention, HS_EN can be a periodic signal, with each period lasting t. The high-level holding time of SNS_EN is greater than or equal to n*t (when the falling edge of SNS_EN triggers the current detection circuit system to enter the current detection activation stage, the low-level holding time of SNS_EN is greater than or equal to n*t), where n can be a positive number greater than or equal to 1, and the specific value can be determined according to actual needs. SNS_EN can be a periodic signal or a non-periodic signal.

[0091] The voltage transmission unit 2 will now be described in more detail.

[0092] In other embodiments of the present invention, please refer to Figure 2 The voltage transmission unit 2 described above exemplarily includes a timing controller (in... Figure 2 (represented by 21) and transmission unit.

[0093] Let's first introduce the timing controller 21.

[0094] Please see again Figure 2 The two input terminals of the timing controller 21 are connected to the second pin 122 and the first pin 121, respectively.

[0095] The timing controller 21 is used to: during the current detection activation phase, output a third enable signal based on the second enable signal (in... Figure 2 and Figure 9 (represented by TG_EN in the text), the third enable signal is used to control the current mirror unit 3 to enter the working state.

[0096] In one example, the timing controller 21 can specifically be a timing control chip.

[0097] In another example, the timing controller 21 can specifically be a resistor-capacitor delay circuit (RC delay circuit).

[0098] In other embodiments of the present invention, under delay control, the start time of the third enable signal controlling the current mirror unit 3 entering the working state is later than the start time of the first MOSFET 11 turning on.

[0099] In one example, the rising edge of TG_EN is used to trigger the current mirror unit 3 to enter the working state, and the falling edge of TG_EN is used to trigger it to enter the non-working state, and vice versa.

[0100] Furthermore, with Figure 9 As shown in the example, under delay control, the rising edge of TG_EN lags behind the rising edge of the second enable signal (HS_EN) by a difference of T_dly. The falling edge of TG_EN coincides with the falling edge of the second enable signal. This ensures that the start time of the third enable signal controlling the current mirror unit 3 to enter the working state lags behind the start time of the first MOSFET 11's conduction, with a lag time of T_dly.

[0101] The transmission unit is described below.

[0102] The first end of the transmission unit is connected to the output end of the timing controller 21, the second end of the transmission unit is connected to the third pin 123, and the third end of the transmission unit is connected to the second end of the current mirror unit 3.

[0103] The transmission unit is used to transmit the startup voltage at the third pin 123 to the second terminal of the current mirror unit 3 during the conduction of the first MOSFET11.

[0104] In one example, see Figure 2 The transmission unit specifically includes: a third MOSFET (in Figure 2 (represented by 22 in the middle), the second diode (in Figure 2 (represented by 23), first resistor (in) Figure 2 (represented by 24), the third diode (in) Figure 2 (represented by 25), the fourth MOSFET (in) Figure 2 (represented by 26) and the second resistor (in Figure 2 (represented by 27 in Chinese).

[0105] Please see again Figure 2 The gate of the third MOSFET 22 is connected to the output of the timing controller 21, and the source of the third MOSFET 22 is connected to the source of the second MOSFET 13. The gate voltage of the third MOSFET 22 is determined by the third enable signal. The gate of the third MOSFET 22 serves as the first terminal of the transmission unit.

[0106] The positive terminal of the second diode 23 is connected to the input voltage Vin, and the negative terminal of the second diode 23 is connected to the drain of the third MOSFET 22.

[0107] The first terminal of the first resistor 24 is connected to the input voltage Vin.

[0108] The positive terminal of the third diode 25 is connected to the second terminal of the first resistor 24.

[0109] The gate of the fourth MOSFET 26 is connected to the second terminal of the first resistor 24. The source of the fourth MOSFET 26 is connected to the negative terminal of the third diode 25.

[0110] The two ends of the second resistor 27 are connected to the drain of the fourth MOSFET 26 and the third pin 123, respectively. The end of the second resistor 27 connected to the third pin 123 serves as the second end of the transmission unit.

[0111] Specifically, the third MOSFET 22 includes a first parasitic diode 221. The anode of the first parasitic diode 221 is connected to the source of the third MOSFET 22, and the cathode of the first parasitic diode 221 is connected to the drain of the third MOSFET 22; the fourth MOSFET 26 includes a second parasitic diode 261. The anode of the second parasitic diode 261 is connected to the drain of the fourth MOSFET 26, and the cathode of the second parasitic diode 261 is connected to the source of the fourth MOSFET 26.

[0112] The current mirror unit 3 is described in detail below.

[0113] In one example, current mirror unit 3 specifically includes: a fifth MOSFET (in Figure 2 (represented by 31 in Chinese), amplifier (in) Figure 2 (represented by 32) and the sixth MOSFET (in Figure 2 (represented by 33). Among them:

[0114] The drain of the fifth MOSFET 31 is connected to the input voltage Vin, and the gate of the fifth MOSFET 31 is connected to the negative terminal of the third diode 25. In this example, the drain of the fifth MOSFET 31 serves as the first terminal of the current mirror unit 3, and the gate of the fifth MOSFET 31 serves as the second terminal of the current mirror unit 3, which is connected to the third terminal of the transmission unit (i.e., the gate of the fourth MOSFET 26).

[0115] The positive input terminal of amplifier 32 is connected to the source of the fifth MOSFET 31, and the negative input terminal of amplifier 32 is connected to the drain of the third MOSFET 31.

[0116] The drain of the sixth MOSFET 33 is connected to the source of the fifth MOSFET 31, the gate of the sixth MOSFET 33 is connected to the output of the amplifier 32, and the source of the sixth MOSFET 33 is connected to the subsequent circuit of the basic topology circuit unit 1. The subsequent circuit is connected to the controller 12, so the detection current Isns flowing through the source of the sixth MOSFET 33 can be processed by the subsequent circuit and then enter the controller 12.

[0117] Below, based on Figure 2 The detailed structure of the switching power supply is shown, and its overall working process is introduced.

[0118] It should be noted that, in Figure 2 In the circuit, the voltage drop across the ordinary diodes (diode 14, diode 23, and diode 25) is 0.7V, and the voltage drop across the parasitic diodes (first and second parasitic diodes) is 0.3V. The on-state voltage drop of the first MOSFET 11 is V. 11 =Iin×Ron, where Iin represents the input current and Ron represents the source-drain equivalent resistance of the first MOSFET11.

[0119] Of course, different processes and application conditions may cause slight differences in the voltage drop of ordinary diodes and parasitic diodes, resulting in slight differences in the voltage of different nodes in the switching power supply.

[0120] Combination Figure 9 visible:

[0121] Within region D, when the first enable signal (SNS_EN) issued by controller 12 is low, the third MOSFET 22 is turned off. At this time, regardless of how the fourth enable signal (LS_EN) and the second enable signal (HS_EN) change, the current detection circuit system is in the current detection failure stage.

[0122] When the first enable signal from controller 12 is high, it indicates that the current detection is activated. The third enable signal (TG_EN) changes in accordance with the second enable signal. Specifically, the rising edge of the third enable signal is delayed by a time T_dly compared to the rising edge of the second enable signal, and the falling edge of the third enable signal coincides with the falling edge of the second enable signal.

[0123] Within region A, the voltage of the second enable signal is Vin - Iin × Ron + V_LDO - 0.7, and the first MOSFET 11 is turned on. The second node voltage (in...) Figure 2 In this stage, the voltage of the third enable signal (represented by V_SW) is Vin-Iin×Ron. The third MOSFET 22 is turned off, and the voltage at the inverting input of amplifier 32 (in...) Figure 2 The voltage at pin 123 (represented by VN) is Vin-Iin×Ron-0.3. The startup voltage at pin 123 is Vin-Iin×Ron+V_LDO-0.7. At this time, the gate voltage of the fourth MOSFET 26 is Vin, and the drain voltage is the startup voltage = Vin-Iin×Ron+V_LDO-0.7. The fourth MOSFET 26 is essentially in a reverse conduction state. The fourth MOSFET 26 transfers its drain voltage, i.e., the startup voltage (Vin-Iin×Ron+V_LDO-0.7), to the gate of the fifth MOSFET 31. Since the voltage at the inverting input of amplifier 32 is Vin-Iin×Ron-0.3, the feedback "virtual short" at the inverting input results in the voltage at the non-inverting input of amplifier 32 (the source of the fifth MOSFET 31) being Vin-Iin×Ron-0.3. In summary, the voltage characteristics of the gate, source, and drain of the first MOSFET 11 and the fifth MOSFET 31 are shown in Table 1.

[0124] Table 1

[0125] gate Source Drain 11 Vin-Iin×Ron+V_LDO-0.7 Vin-Iin×Ron Vin 31 Vin-Iin×Ron+V_LDO-0.7 Vin-Iin×Ron-0.3 Vin

[0126] As shown in Table 1, within region A, since the third MOSFET 22 is off, the source voltages of the fifth MOSFET 31 and the first MOSFET 11 are different, and the detection result is invalid at this time.

[0127] Within region B, the second enable signal (HS_EN) voltage is Vin - Iin × Ron + V_LDO - 0.7. The first MOSFET 11 is turned on, V_SW is Vin - Iin × Ron, and the TG_EN voltage is Vin - Iin × Ron + V_LDO - 0.7. The third MOSFET 22 is turned on, and the voltage at the inverting input of amplifier 32 is Vin - Iin × Ron. At this time, the gate voltage of the fourth MOSFET 26 is Vin, and the drain voltage of the fourth MOSFET 26 is the startup voltage (Vin - Iin × Ron + V_LDO - 0.7). The fourth MOSFET 26 is essentially in a reverse-biased conduction state. The fourth MOSFET 26 transmits its drain voltage, i.e., the startup voltage (Vin - Iin × Ron + V_LDO - 0.7), to the gate of the fifth MOSFET 31. Since the voltage at the inverting input terminal of amplifier 32 is Vin - Iin × Ron, the "virtual short" feedback at the inverting input terminal causes the voltage at the non-inverting input terminal (source of the fifth MOSFET 31) of amplifier 32 to be Vin - Iin × Ron. In summary, the gate, source, and drain voltages of the first MOSFET 11 and the fifth MOSFET 31 are shown in Table 2.

[0128] Table 2

[0129] gate Source Drain 11 Vin-Iin×Ron+V_LDO-0.7 Vin-Iin×Ron Vin 31 Vin-Iin×Ron+V_LDO-0.7 Vin-Iin×Ron Vin

[0130] As can be seen from the analysis of Table 2, within the B stage range, the gate, source, and drain voltages of the first MOSFET11 and the fifth MOSFET31 are the same, and the detection result is valid.

[0131] At this point, the fifth MOSFET 31 and the first MOSFET 11 form a mirror pair. The relationship between Iin and Isns satisfies: Isns = k * Iin, where k is the size ratio coefficient between the fifth MOSFET 31 and the first MOSFET 11. Special attention needs to be paid to the matching between the first MOSFET 11 and the fifth MOSFET 31 during circuit design and layout to improve detection accuracy. Those skilled in the art can flexibly design the value of k, such as 1, 2, 4, 6, etc. Isns flows through the sixth MOSFET 33 and can be further processed for use by subsequent circuits. The subsequent circuits are connected to the controller 12, and Isns enters the controller 12 after being processed by the subsequent circuits. Isns represents the mirror current, i.e., the detection current.

[0132] Within region C, the second enable signal voltage is 0, the first MOSFET 11 is off, the second node voltage is 0, the third enable signal voltage is 0, the third MOSFET 22 is off, and the voltage at the inverting input of amplifier 32 is Vin-0.7. The startup voltage is V_LDO-0.7. At this time, the gate voltage of the fourth MOSFET 26 is Vin, the source voltage of the fourth MOSFET 26 is Vin-0.7, the drain voltage of the fourth MOSFET 26 is the startup voltage (V_LDO-0.7), and the fourth MOSFET 26 is off. The gate voltage of the fifth MOSFET 31 is Vin-0.7. Since the voltage at the inverting input of amplifier 32 is Vin-0.7, the feedback "virtual short" at the inverting input causes the voltage at the non-inverting input of amplifier 32 (the source of the fifth MOSFET 31) to be Vin-0.7. In summary, the voltage conditions of the gate, source, and drain of the first MOSFET 11 and the fifth MOSFET 31 are shown in Table 3.

[0133] Table 3

[0134] gate Source Drain 11 0 0 Vin 31 Vin-0.7 Vin-0.7 Vin

[0135] As can be seen from the analysis in Table 3, the gate and source voltages of the first MOSFET11 and the fifth MOSFET31 are different. At this time, the fifth MOSFET31 is turned off, there is no mirror current, and no detection result output.

[0136] It can be assumed that the mirror current unit 3 is in the working state when the gate, source, and drain voltages of the first MOSFET 11 and the fifth MOSFET 31 are the same. When any one or more of the gate, source, and drain voltages of the two MOSFETs are not the same, the mirror current unit 3 is in the non-working state.

[0137] As can be seen from the analysis of Tables 1, 2 and 3 above, the voltages at both the positive and negative input terminals of amplifier 32 change around Vin during the current detection activation phase, exhibiting a stable common-mode level.

[0138] As can be seen from the analysis of Tables 1, 2 and 3 above, the difference between the gate and source voltages of the third MOSFET22, the fourth MOSFET26, the fifth MOSFET31 and the sixth MOSFET33 in each region ABCD is less than the breakdown voltage. The basic topology circuit unit 1, voltage transmission unit 2 and current mirror unit 3 can realize MOSFET self-protection and enhance the stability of the switching power supply.

[0139] It should be noted that the switching power supply current detection circuit system (hereinafter referred to as the system) in all the above embodiments is illustrated by using the basic topology circuit unit 1 as a BUCK topology. The voltage transmission unit and current mirror unit described in all the above embodiments are also applicable to systems containing other topologies (BOOST topology or BUCK-BOOST topology).

[0140] Furthermore, as previously mentioned, other topologies also include a first MOSFET and a controller. The connection relationships between the voltage transmission unit and the first MOSFET, the current mirror unit and the first MOSFET, the voltage transmission unit and the controller, and the current mirror unit and the controller described in all the above embodiments are also applicable to systems containing other topologies.

[0141] The above-described switching power supply current detection circuit system can also be referred to as a switching power supply; please refer to [link / reference]. Figures 6 to 8Based on whether the inductor current crosses zero, the control modes of switching power supplies can be divided into three types: CCM (Continuous Conduction Mode) and DCM (Discontinuous Conduction Mode). CCM refers to a continuous inductor current mode, where the inductor current is always greater than zero. DCM refers to a discontinuous inductor current mode, where the inductor current is zero for a certain period of time. BCM (Boundary Conduction Mode) refers to a critical inductor current mode, where the inductor current starts charging again the instant it discharges to zero. In this diagram, the horizontal axis t represents time, and the vertical axis IL represents the inductor current.

[0142] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0143] This document uses specific examples to illustrate the principles and implementation methods of the embodiments of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of the embodiments of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the embodiments of the present invention. In summary, the content of this specification should not be construed as a limitation on the embodiments of the present invention.

Claims

1. A switching power supply current detection circuit system, characterized in that, It includes a basic topology circuit unit and a current detection circuit system; the current detection circuit system includes a voltage transmission unit and a current mirror unit, wherein: The basic topology circuit unit is used to adjust the voltage; the basic topology circuit unit includes at least a first metal-oxide-semiconductor field-effect transistor and a controller connected in series; the drain of the first metal-oxide-semiconductor field-effect transistor is connected to the input voltage, and the third pin of the controller is used to connect to the start-up voltage; The first terminal of the current mirror unit is connected to the input voltage, and the second terminal of the current mirror unit is connected to the third pin through the voltage transmission unit; The voltage transmission unit is also connected to the first pin and the second pin of the controller respectively; the second pin is also connected to the gate of the first metal-oxide-semiconductor field-effect transistor; wherein, the first enable signal output by the first pin is used to control the current detection circuit system to enter the current detection active stage or the current detection inactive stage, and the second enable signal output by the second pin is used to control the first metal-oxide-semiconductor field-effect transistor to be turned on or off. The voltage transmission unit is configured to: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned on, control the current mirror unit to enter the working state; and during the current detection activation phase, while the first metal-oxide-semiconductor field-effect transistor is turned on, transmit the start-up voltage at the third pin to the second terminal of the current mirror unit. The current mirroring unit is used to: mirror the current flowing through the first metal-oxide-semiconductor field-effect transistor in the operating state; The voltage transmission unit includes a timing controller and a transmission unit, wherein: The timing controller has two input terminals connected to the second pin and the first pin, respectively; The first end of the transmission unit is connected to the output end of the timing controller, the second end of the transmission unit is connected to the third pin, and the third end of the transmission unit is connected to the second end of the current mirror unit. The timing controller is configured to: during the current detection activation phase, output a third enable signal based on the second enable signal; the third enable signal is used to control the current mirror unit to enter the working state; The transmission unit is used to transmit the startup voltage at the third pin to the second terminal of the current mirror unit during the conduction of the first metal-oxide-semiconductor field-effect transistor.

2. The switching power supply current detection circuit system according to claim 1, characterized in that, The voltage transmission unit is specifically used for: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned on, controlling the current mirror unit to enter the working state, wherein the start time of the current mirror unit entering the working state is later than the start time of the first metal-oxide-semiconductor field-effect transistor being turned on; and during the current detection activation phase, during the period when the first metal-oxide-semiconductor field-effect transistor is turned on, transmitting the start-up voltage at the third pin to the second end of the current mirror unit.

3. The switching power supply current detection circuit system according to claim 1, characterized in that, The rising edge of the second enable signal is used to trigger the first metal-oxide-semiconductor field-effect transistor to turn on, and the falling edge of the second enable signal is used to trigger the first metal-oxide-semiconductor field-effect transistor to turn off.

4. The switching power supply current detection circuit system according to claim 1, characterized in that, The voltage transmission unit is further configured to: during the current detection activation phase, when the first metal-oxide-semiconductor field-effect transistor is turned off, control the current mirror unit to enter a non-operating state.

5. The switching power supply current detection circuit system according to any one of claims 1-4, characterized in that, The transmission unit includes: A third metal-oxide-semiconductor field-effect transistor (MOSFET) has its gate connected to the output of the timing controller, and its source connected to the source of a second MOSFET. The gate voltage of the third MOSFET is determined by the third enable signal. The second diode has its anode connected to the input voltage and its cathode connected to the drain of the third metal-oxide-semiconductor field-effect transistor. A first resistor, with its first terminal connected to the input voltage; The third diode, wherein the positive terminal of the third diode is connected to the second terminal of the first resistor; A fourth metal-oxide-semiconductor field-effect transistor, wherein the gate of the fourth metal-oxide-semiconductor field-effect transistor is connected to the second terminal of the first resistor; and the source of the fourth metal-oxide-semiconductor field-effect transistor is connected to the negative terminal of the third diode. The second resistor is connected to the drain of the fourth metal-oxide-semiconductor field-effect transistor and the third pin, respectively.

6. The switching power supply current detection circuit system according to any one of claims 1-4, characterized in that, The rising edge of the third enable signal is used to trigger the current mirror unit to enter the working state, and the falling edge of the third enable signal is used to trigger the current mirror unit to enter the non-working state; furthermore, the rising edge of the third enable signal lags behind the rising edge of the second enable signal, and the falling edge of the third enable signal coincides with the falling edge of the second enable signal. The rising edge of the third enable signal corresponds to the start time; the rising edge of the second enable signal corresponds to the conduction start time.

7. The switching power supply current detection circuit system according to claim 5, characterized in that, The current mirror unit includes: A fifth metal-oxide-semiconductor field-effect transistor, wherein the drain of the fifth metal-oxide-semiconductor field-effect transistor is connected to the input voltage, and the gate of the fifth metal-oxide-semiconductor field-effect transistor is connected to the negative terminal of the third diode; An amplifier, wherein the positive input terminal of the amplifier is connected to the source of the fifth metal-oxide-semiconductor field-effect transistor, and the negative input terminal of the amplifier is connected to the drain of the third metal-oxide-semiconductor field-effect transistor; A sixth metal-oxide-semiconductor field-effect transistor (MOSFET) is provided, wherein the drain of the sixth MOSFET is connected to the source of the fifth MOSFET, the gate of the sixth MOSFET is connected to the output of the amplifier, and the source of the sixth MOSFET is connected to the subsequent circuit of the basic topology circuit unit.

8. The switching power supply current detection circuit system according to claim 5, characterized in that, The third metal-oxide-semiconductor field-effect transistor includes a first parasitic diode; the positive terminal of the first parasitic diode is connected to the source of the third metal-oxide-semiconductor field-effect transistor, and the negative terminal of the first parasitic diode is connected to the drain of the third metal-oxide-semiconductor field-effect transistor. The fourth metal-oxide-semiconductor field-effect transistor includes a second parasitic diode; the positive terminal of the second parasitic diode is connected to the drain of the fourth metal-oxide-semiconductor field-effect transistor, and the negative terminal of the second parasitic diode is connected to the source of the fourth metal-oxide-semiconductor field-effect transistor.

9. The switching power supply current detection circuit system according to claim 1, characterized in that, The basic topology circuit unit, the voltage transmission unit, and the current mirror unit are integrated in the controller.

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