A test circuit and latch up rule verification method

Abstract

The present invention provides a test circuit and a latch-up rule verification method, wherein an inverter includes first to N-th inverters connected in sequence; a tie-high circuit; each inverter in the first to N-th inverters includes an NMOS and a PMOS connected to each other; an input end of the first inverter is connected to an output end of the tie-high circuit; and the output end of the N-th inverter is suspended; the tie-high circuit includes: first and second NMOSs and first and second PMOSs; the gates of the first and second PMOSs are connected; the bulk ends of the first and second PMOSs and their respective sources are respectively connected to a voltage VDD; the drain of the first PMOS serves as the output end of the tie-high circuit; the drain of the second PMOS is connected to the gate of the second NMOS; the drains of the first and second NMOSs and the gate of the first NMOS are commonly connected to the gates of the first and second PMOSs; the bulk ends of the first and second NMOSs and their respective sources are respectively grounded; the source of the PMOS of each inverter in the first to N-th inverters is connected to the voltage VDD; and the source of the NMOS of each inverter in the first to N-th inverters is grounded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test circuit and a latch-up rule verification method. Background Art

[0002] With the advancement of semiconductor manufacturing technology and the increasing density and integration of packaging, the possibility of latch-up is increasing. The excessive current generated by latch-up can cause permanent damage to the chip, making latch-up prevention one of the most important measures in IC layout.

[0003] Since the latch-up effect is more likely to occur in the IO area, there are a large number of test structures related to IO devices, but few test structures for core devices. Therefore, we designed such a test circuit to fill this gap. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a test circuit and a latch-up rule verification method to solve the problem in the prior art of the lack of a latch-up rule verification method for a core layout test structure.

[0005] To achieve the above and other related objectives, the present invention provides a test circuit, comprising at least:

[0006] Inverter; the inverter includes first to Nth inverters connected in sequence; Tie-high circuit;

[0007] Each of the first to Nth inverters comprises an NMOS and a PMOS connected to each other;

[0008] The input end of the first inverter is connected to the output end of the Tie-high circuit; the output end of the Nth inverter is suspended;

[0009] The tie-high circuit includes: first and second NMOSs and first and second PMOSs; the gates of the first and second PMOSs are connected; the bulk terminals and sources of the first and second PMOSs are connected to a voltage VDD respectively; the drain of the first PMOS serves as the output terminal of the tie-high circuit; the drain of the second PMOS is connected to the gate of the second NMOS;

[0010] The drains of the first and second NMOSs and the gate of the first NMOS are commonly connected to the gates of the first and second PMOSs; the bulk terminals of the first and second NMOSs and their respective sources are grounded respectively;

[0011] A source of the PMOS of each of the first to N-th inverters is connected to a voltage VDD; a source of the NMOS of each of the first to N-th inverters is grounded.

[0012] Preferably, the first to N-th inverters are connected sequentially as follows: the drain of the PMOS in each of the first to N-1-th inverters is connected to the drain of the NMOS in the inverter, and is sequentially connected to the gates of the PMOS and NMOS in the next inverter; the gates of the PMOS and NMOS in the first inverter are connected to the output end of the Tie-high circuit.

[0013] Preferably, the test circuit further comprises a dummy device unit connected to the input end of the tie-high circuit and an END CAP unit connected to the input end of the dummy device unit; the output end of the dummy device unit is connected to the input end of the tie-high circuit.

[0014] Preferably, the test circuit further comprises a dummy device unit connected to the drains of the PMOS and NMOS in the Nth inverter and an END CAP unit connected to the output end of the dummy device unit.

[0015] Preferably, the END CAP unit is used to contact a substrate.

[0016] Preferably, the tie-high circuit is used to generate self-bias for the test circuit.

[0017] Preferably, for the layouts of the PMOS in the first to Nth inverters, in the same N well, when the distance between the PMOS active region and the N+ active region closest to the PMOS active region is greater than 30 μm, the test circuit latches up during operation.

[0018] Preferably, for the layouts of the NMOS in the first to Nth inverters, in the same P well, when the distance between the NMOS active region and the P+ active region closest to the NMOS active region is greater than 30 μm, the test circuit latches up during operation.

[0019] The present invention also provides a latch up rule verification method, which at least includes:

[0020] Step 1: providing the test circuit;

[0021] Step 2: Set the voltage VDD to VCC; and measure the current value Idd1 between the voltage VDD and the ground voltage VSS.

[0022] Step 3: Increase the voltage VDD to 1.5VCC, then reduce it to VCC, and measure the current value Idd2 between the voltage VDD and the ground voltage VSS;

[0023] Step 4: Compare the current value Idd1 with the current value Idd2. If the current value Idd2 is greater than 1.4 times the current value Idd1, the test circuit latches up during the pressurization process in step 3.

[0024] As described above, the test circuit and latch-up rule verification method of the present invention have the following beneficial effects: the present invention provides a test method that is more in line with the use of design rule formulation, adopts a self-biasing method, avoids other negative effects that may be caused by directly connecting the gate to the power supply, saves test pins, and effectively realizes the latch-up test of IO devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic diagram of the Tie-high circuit in the present invention;

[0026] Figure 2 Shown is a schematic diagram of the test circuit of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figures 1 to 2 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0029] The present invention provides a test circuit, comprising at least:

[0030] Inverter; the inverter includes first to Nth inverters connected in sequence; Tie-high circuit;

[0031] Each of the first to Nth inverters comprises an NMOS and a PMOS connected to each other;

[0032] The input end of the first inverter is connected to the output end of the Tie-high circuit; the output end of the Nth inverter is suspended;

[0033] The tie-high circuit includes: first and second NMOSs and first and second PMOSs; the gates of the first and second PMOSs are connected; the bulk terminals and sources of the first and second PMOSs are connected to a voltage VDD respectively; the drain of the first PMOS serves as the output terminal of the tie-high circuit; the drain of the second PMOS is connected to the gate of the second NMOS;

[0034] The drains of the first and second NMOSs and the gate of the first NMOS are commonly connected to the gates of the first and second PMOSs; the bulk terminals of the first and second NMOSs and their respective sources are grounded respectively;

[0035] A source of the PMOS of each of the first to N-th inverters is connected to a voltage VDD; a source of the NMOS of each of the first to N-th inverters is grounded.

[0036] The present invention further provides that the first to N-th inverters of this embodiment are connected sequentially as follows: the drain of the PMOS in each of the first to N-1-th inverters is connected to the drain of the NMOS in the inverter, and sequentially connected to the gates of the PMOS and NMOS in the next inverter; the gates of the PMOS and NMOS in the first inverter are connected to the output end of the Tie-high circuit.

[0037] The present invention further comprises: the test circuit of this embodiment further comprising a dummy device unit connected to the input end of the tie-high circuit and an END CAP unit connected to the input end of the dummy device unit; the output end of the dummy device unit is connected to the input end of the tie-high circuit.

[0038] Furthermore, the test circuit of this embodiment of the present invention further includes a dummy device unit connected to the drains of the PMOS and NMOS in the Nth inverter, and an END CAP unit connected to the output end of the dummy device unit.

[0039] Furthermore, in the present invention, the END CAP unit of this embodiment is used to contact a substrate.

[0040] Furthermore, the tie-high circuit of this embodiment is used to generate self-bias for the test circuit.

[0041] The present invention further provides that, for the layout of the PMOS in the first to Nth inverters of this embodiment, when the distance between the PMOS active region and the N+ active region closest to the PMOS active region in the same N well is greater than 30 μm, the test circuit latches up during operation.

[0042] The present invention further provides that, for the layout of the NMOS in the first to Nth inverters of this embodiment, when the distance from the NMOS active region to the P+ active region closest to the NMOS active region in the same P well is greater than 30 μm, the test circuit latches up during operation.

[0043] like Figure 1 and Figure 2 As shown, Figure 1 Shown is a schematic diagram of the Tie-high circuit in the present invention. Figure 2 Shown is a schematic diagram of the test circuit of the present invention.

[0044] The test circuit of the present invention comprises in this embodiment: an inverter; the inverter comprises first to Nth inverters connected in sequence; the test circuit further comprises: Figure 1 Tie-high circuit shown;

[0045] In the test circuit, each of the first to Nth inverters includes an NMOS and a PMOS connected to each other; wherein the first inverter ( Figure 2 The input end of the inverter at the left end of the middle) is connected to the output end of the Tie-high circuit (Tie high); the Nth inverter ( Figure 2 The output terminal of the inverter at the right end of the middle is left floating; Figure 1 The tie-high circuit comprises: a first NMOS (03), a second NMOS (04) and a first PMOS (01), a second PMOS (02); the gates of the first and second PMOS are connected; the bulk terminals (bases) of the first and second PMOS and their respective sources are connected to a voltage VDD; the drain (01) of the first PMOS serves as the output terminal of the tie-high circuit; the drain of the second PMOS (02) is connected to the gate of the second NMOS (04); the drains of the first and second NMOS and the gate of the first NMOS are commonly connected to the gates of the first and second PMOS; the bulk terminals of the first and second NMOS and their respective sources are grounded (i.e., ground voltage VSS);

[0046] like Figure 2 As shown, the PMOS (i.e. Figure 2 The source of the PMOS in the row located at the upper end from left to right is connected to the voltage VDD; the NMOS of each inverter in the first to Nth inverters (i.e. Figure 2 The sources of the NMOS (a row of NMOSs distributed from left to right at the lower end) are grounded (ie, the ground voltage VSS).

[0047] like Figure 2 As shown, the first inverter in the present invention is composed of Figure 2 The first PMOS (05) at the upper end and the first NMOS (06) at the lower end are formed; the second inverter is composed of the second PMOS (07) at the upper end and the second NMOS (08) at the lower end; and so on, the N-1 inverter is composed of the second-to-last PMOS (09) at the upper end and the second-to-last NMOS (10) at the lower end; the N inverter is composed of the rightmost PMOS (11) at the upper end and the rightmost NMOS (12) at the lower end.

[0048] In this embodiment, the first to N-th inverters are connected sequentially as follows: the drain of the PMOS in each of the first to N-1-th inverters is connected to the drain of the NMOS in the inverter, and sequentially connected to the gates of the PMOS and NMOS in the next inverter; the gates of the PMOS (05) and NMOS (06) in the first inverter are connected to the output end of the tie-high circuit (Tie high).

[0049] The test circuit further includes a dummy device unit (Fill) connected to the input end of the tie-high circuit and an END CAP unit (END CAP) connected to the input end of the dummy device unit (Fill); the output end of the dummy device unit is connected to the input end of the tie-high circuit. The test circuit further includes a dummy device unit connected to the drains of the PMOS (11) and NMOS (12) in the Nth inverter and an END CAP unit (END CAP) connected to the output end of the dummy device unit. The two END CAP units (END CAP) are respectively used to contact the substrate. The tie-high circuit is used to generate self-bias for the test circuit.

[0050] The present invention also provides a latch up rule verification method using the test circuit, which at least includes:

[0051] Step 1: providing the test circuit;

[0052] Step 2: Set the voltage VDD to VCC; and measure the current value Idd1 between the voltage VDD and the ground voltage VSS.

[0053] Step 3: Increase the voltage VDD to 1.5VCC, then reduce it to VCC, and measure the current value Idd2 between the voltage VDD and the ground voltage VSS;

[0054] Step 4: Compare the current value Idd1 with the current value Idd2. If the current value Idd2 is greater than 1.4 times the current value Idd1, the test circuit latches up during the pressurization process in step 3.

[0055] In addition to using the above-mentioned voltage change test method to determine whether latch up occurs in the test circuit. In addition, the occurrence of latch up is determined by conducting experiments through layout design. According to simulation estimation, for the layout of the PMOS in the first to Nth inverters, in the same N well, when the distance from the PMOS active area to the N+ active area closest to the PMOS active area is greater than 30μm, the test circuit latches up during operation. For the layout of the NMOS in the first to Nth inverters, in the same P well, when the distance from the NMOS active area to the P+ active area closest to the NMOS active area is greater than 30μm, the test circuit latches up during operation.

[0056] Conversely, for the PMOS layouts in the first through Nth inverters, if the distance between the PMOS active region and the nearest N+ active region in the same N-well is less than or equal to 30 μm, the test circuit will not latch up during operation. For the NMOS layouts in the first through Nth inverters, if the distance between the NMOS active region and the nearest P+ active region in the same P-well is less than or equal to 30 μm, the test circuit will not latch up during operation.

[0057] Therefore, the distance from the NMOS active region to the P+ active region closest to the NMOS active region and the distance from the PMOS active region to the N+ active region closest to the PMOS active region can be designed to control whether latch up occurs.

[0058] In summary, the present invention provides a testing method that better aligns with design rule formulation and usage. It employs a self-biasing approach, avoids the negative effects that might otherwise arise from directly connecting the gate to the power supply, conserves test pins, and effectively implements latch-up testing of IO devices. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A test circuit, characterized in that: At least includes an inverter and a tie-high circuit; The inverter includes first to Nth inverters connected in sequence; each of the first to Nth inverters includes an NMOS and a PMOS connected to each other; the input end of the first inverter is connected to the output end of the tie-high circuit; The output end of the Nth inverter is left floating; The tie-high circuit includes: a first and a second NMOS and a first and a second PMOS; the gates of the first and the second PMOS are connected; the bulk terminals of the first and the second PMOS and their respective sources are connected to a voltage VDD; the drain of the first PMOS serves as the output terminal of the tie-high circuit; the drain of the second PMOS is connected to the gate of the second NMOS; the drains of the first and the second NMOS and the gate of the first NMOS are commonly connected to the gates of the first and the second PMOS; the bulk terminals of the first and the second NMOS and their respective sources are grounded; the source of the PMOS of each inverter from the first to the Nth inverter is connected to the voltage VDD; the source of the NMOS of each inverter from the first to the Nth inverter is grounded; The test circuit is used to verify the latch up rule in the following way: First, the voltage VDD is set to VCC; a current value Idd1 between the voltage VDD and the ground voltage VSS is measured; then, the voltage VDD is increased to 1.5 VCC and then decreased to VCC, and a current value Idd2 between the voltage VDD and the ground voltage VSS is measured; the current value Idd1 is compared with the current value Idd2. If the current value Idd2 is greater than 1.4 times the current value Idd1, the test circuit latches up during the voltage application process in step 3.

2. The test circuit according to claim 1, wherein: The first to N-th inverters are sequentially connected in the following manner: the drain of the PMOS in each of the first to N-1-th inverters is connected to the drain of the NMOS in the inverter, and is sequentially connected to the gates of the PMOS and NMOS in the next inverter; The gates of the PMOS and NMOS in the first inverter are connected to the output end of the Tie-high circuit.

3. The test circuit according to claim 1, wherein: The test circuit further includes a dummy device unit connected to the input end of the Tie-high circuit and an END CAP unit connected to the input end of the dummy device unit; the output end of the dummy device unit is connected to the input end of the Tie-high circuit.

4. The test circuit according to claim 3, wherein: The test circuit further includes a dummy device unit connected to the drains of the PMOS and NMOS in the Nth inverter and an END CAP unit connected to the output end of the dummy device unit.

5. The test circuit according to claim 4, wherein: The END CAP unit is used to contact the substrate.

6. The test circuit according to claim 1, wherein: The tie-high circuit is used to generate a self-bias for the test circuit.

7. The test circuit according to claim 1, wherein: For the layouts of the PMOS in the first to Nth inverters, in the same N well, when the distance between the PMOS active region and the N+ active region closest to the PMOS active region is greater than 30 μm, the test circuit latches up during operation.

8. The test circuit according to claim 7, wherein: For the layouts of the NMOS in the first to Nth inverters, in the same P well, when the distance between the NMOS active region and the P+ active region closest to the NMOS active region is greater than 30 μm, the test circuit latches up during operation.

9. The latch-up rule verification method for a test circuit according to any one of claims 1 to 8, wherein: At least: Step 1: providing the test circuit; Step 2: Set the voltage VDD to VCC; and measure the current value Idd1 between the voltage VDD and the ground voltage VSS. Step 3: Increase the voltage VDD to 1.5VCC, then reduce it to VCC, and measure the current value Idd2 between the voltage VDD and the ground voltage VSS; Step 4: Compare the current value Idd1 with the current value Idd2. If the current value Idd2 is greater than 1.4 times the current value Idd1, the test circuit latches up during the pressurization process in step 3.

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