Knowledge graph platform

Abstract

The application provides a knowledge graph platform, which comprises a front-end processing platform and a back-end processing platform, wherein the back-end processing platform comprises an integrated storage unit and a field programmable gate array processing unit; the storage unit is configured to store knowledge graph data; the front-end processing platform is configured to receive an access request and parse the access request to obtain a search entity; the field programmable gate array processing unit is connected with the front-end processing platform and the storage unit and is configured to perform information search based on the knowledge graph data stored in the storage unit according to the search entity and return a search result to the front-end processing platform. Based on the knowledge graph search method of the platform, the field programmable gate array processing unit can directly obtain the knowledge graph data from the storage unit for search, and the knowledge graph data does not need to be moved multiple times, so that the knowledge graph search efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a knowledge graph platform. BACKGROUND

[0002] The knowledge graph, known as knowledge domain visualization or knowledge field mapping map in the library information field, is a series of various different graphs showing the development process and structural relationship of knowledge. It is widely applied in the retrieval field, for example, it can be applied to the well-known search engine Google search, chat robots, big data risk control, etc. However, due to the large number of nodes in the knowledge graph and the complex relationship between the nodes, it brings great challenges to the retrieval of the knowledge graph.

[0003] In the prior art, when the knowledge graph is retrieved, part of the knowledge graph data needs to be moved from the storage system to the memory of the general processor, and then the knowledge graph data in the memory is retrieved.

[0004] However, due to the fact that the memory capacity of the general processor is much smaller than the storage capacity of the storage system, it is necessary to move the data multiple times to move all the knowledge graph data to the memory, and then traverse all the data of the knowledge graph to complete the retrieval. Therefore, in the above scheme, due to the multiple movements of the knowledge graph data during retrieval, the efficiency of retrieving the knowledge graph is low. SUMMARY

[0005] The present application provides a knowledge graph platform to solve the technical problem of low efficiency of retrieving the knowledge graph.

[0006] The present application provides a knowledge graph platform, comprising: a front-end processing platform and a back-end processing platform, wherein the back-end processing platform comprises an integrated storage unit and a field programmable gate array processing unit;

[0007] The storage unit is configured to store knowledge graph data.

[0008] The front-end processing platform is configured to receive an access request and parse the access request to obtain a retrieval entity.

[0009] The field programmable gate array processing unit is connected with the front-end processing platform and the storage unit, and is configured to perform information retrieval based on the knowledge graph data stored in the storage unit according to the retrieval entity, and return a retrieval result to the front-end processing platform.

[0010] In a possible implementation manner, the back-end processing platform further includes a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memory unit; the field programmable gate array processing unit includes a knowledge graph retrieval module, a DDR memory control module, a first communication processing module, and a second communication processing module;

[0011] The knowledge graph retrieval module is connected with the DDR memory control module and the second communication processing module, the DDR memory control module is connected with the DDR memory unit, the first communication processing module, and the second communication processing module; the first communication processing module is connected with the front-end processing platform; and the second communication processing module is connected with the storage unit.

[0012] The first communication processing module is configured to acquire the retrieval entity and send the retrieval entity to the knowledge graph retrieval module through the DDR memory control module.

[0013] The knowledge graph retrieval module is configured to send an acquisition request to the storage unit through the second communication processing module.

[0014] The storage unit is configured to send corresponding knowledge graph data to the DDR memory control module through the second communication processing module, so that the DDR memory control module stores the knowledge graph data in the DDR memory unit.

[0015] The knowledge graph retrieval module is configured to acquire the knowledge graph data stored in the DDR memory unit through the DDR memory control module to perform retrieval, and sequentially return a retrieval result to the front-end processing platform through the DDR memory control module and the first communication processing module.

[0016] In a possible implementation manner, the front-end processing platform includes a general processor and a memory unit.

[0017] The general processor is connected with the memory unit and is configured to receive an access request, analyze the access request to obtain a retrieval entity, and store the retrieval entity in the memory unit.

[0018] The field programmable gate array processing unit is connected with the memory unit and is further configured to acquire the retrieval entity stored in the memory unit.

[0019] In a possible implementation manner, the processing unit and the front-end processing platform are connected through a PCIe (Peripheral Component Interconnect Express) interface; and the first communication processing module includes a PCIe control module.

[0020] The PCIe control module is configured to receive the retrieval entity by using an NVMe (Non-Volatile Memory Host Controller Interface Protocol) communication protocol.

[0021] In a possible implementation, the second communication processing module includes a SERDES (Serializer / Deserializer) module and a storage control module.

[0022] The SERDES module is connected with the knowledge graph retrieval module and is configured to convert the acquisition request into a serial signal.

[0023] The storage control module is connected with the SERDES module and the storage unit and is configured to encode the serial signal and send the encoded signal to the storage unit.

[0024] In a possible implementation, the storage unit includes a flash memory.

[0025] In a possible implementation, the storage unit and the field programmable gate array processing unit are integrally arranged on the same PCB (Printed Circuit Board) board card.

[0026] In a possible implementation, a multi-channel communication mode is used between the field programmable gate array processing unit and the storage unit.

[0027] In a possible implementation, the knowledge graph platform further includes an IO (Input / Output) controller.

[0028] The IO controller is configured to control information transmission between modules in the back-end processing platform.

[0029] In a possible implementation, the IO controller includes a command parser and a scheduler.

[0030] The knowledge graph platform provided in the application includes a front-end processing platform and a back-end processing platform, and the back-end processing platform includes a storage unit and a field programmable gate array processing unit which are integrally arranged. The front-end processing platform is configured to receive an access request and parse the access request to obtain a retrieval entity. The field programmable gate array processing unit is configured to retrieve knowledge graph data obtained from the storage unit according to the retrieval entity and return a retrieval result to the front-end processing platform. In the present application, the field programmable gate array processing unit can directly retrieve the knowledge graph data from the storage unit, and the knowledge graph data does not need to be moved multiple times, so that the knowledge graph retrieval efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0032] Figure 1 A structural schematic diagram of a knowledge graph platform provided for Embodiment One of the application;

[0033] Figure 2 A design scheme schematic diagram of an integrated board card based on flash memory and FPGA provided for Embodiment Two of the application;

[0034] Figure 3 A structural schematic diagram of another knowledge graph platform provided for Embodiment Three of the application;

[0035] Figure 4 A processing flow schematic diagram of knowledge graph retrieval provided for Embodiment Four of the application.

[0036] Through the above-mentioned drawings, the explicit embodiments of the application have been shown, and will be described in more detail hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the application by any means, but to illustrate the concept of the application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to various alternative embodiments of the application. It is to be understood that the description of the exemplary embodiments is not intended to limit the application to the embodiments described. Rather, the scope of the application is defined by the appended claims.

[0038] First, the terms involved in the application are explained:

[0039] Flash Memory: Flash Memory is an electronic erasable programmable memory. Compared with traditional magnetic disk media, flash memory has the characteristics of high read-write bandwidth, low access delay, low power consumption and strong stability. At present, it has begun to popularize in data centers, personal computers and mobile devices. Flash memory reads and writes in pages. Before rewriting a page in flash memory, an erase operation needs to be performed first. Flash memory erases in blocks, and a flash memory block contains hundreds of flash memory pages. The SSD (Solid State Drive) built on the basis of flash memory uses FTL (Flash Translation Layer) to manage the read-write-erase of flash memory and provides the same read-write interface to the software system as the traditional magnetic disk. Flash translation layer is mainly responsible for address mapping, garbage collection, wear leveling and ECC (Error Correction Code) verification, etc.

[0040] FPGA: Field Programmable Gate Array, FPGA, is a semiconductor device constructed in an array based on configurable logic blocks (Configurable Logic Block) and programmable interconnects (Programmable Interconnects). With the development of FPGA technology, more and more special computing and storage modules are integrated into the internal of FPGA chip to improve its computing and storage capacity, such as digital signal processing unit (DSP), block storage unit (BRAM), high bandwidth memory (HBM) etc. The characteristics of FPGA chip is that it can customize the special circuit architecture for specific functions, with high performance and good energy efficiency. In addition, FPGA has very good programmability and flexibility, and programmers can repeatedly erase and program it to adapt to different computing occasions and loads;

[0041] Knowledge Graph: Knowledge Graph is essentially a semantic network (Semantic Network) knowledge base, which is a structured representation of knowledge and facts, composed of entities, relationships, and semantic descriptions. Entities can be objects and abstract concepts in the real world, relationships represent the connection between entities, and the semantic description of entities and their relationships contains well-defined types and attribute meanings. Knowledge graph is widely used in search engines, natural language processing, question and answer systems, etc. For example, in a social network graph, "people" are entities, which can also include "school" entities. The relationship between people and people can be "friends" or "colleagues". The relationship between people and school can be "student" or "graduate".

[0042] From the initial Google search, to the present chat robot, big data risk control, securities investment, intelligent medical treatment, and recommendation system, the application of knowledge graph is more and more extensive. Knowledge graph can support accurate retrieval. For example, for a user's need to retrieve a certain problem, the knowledge graph retrieval can return a closest correct answer to the user. Therefore, the knowledge graph needs to include a large amount of data to support such a function.

[0043] Because the number of nodes of the graph in the knowledge graph is large, and the relationship between the nodes is complex, the knowledge graph needs a large amount of (usually TB level) storage system to store it. If a user wants to find the required knowledge in the knowledge graph, it is necessary to search or retrieve the large graph. In the traditional computing platform, when retrieving, part of the knowledge graph data needs to be moved to the memory of the general processor first, and then the knowledge graph data in the memory is retrieved. However, the capacity of the memory (usually GB level) is much smaller than the storage capacity of the storage system, which requires multiple moves of the data in the storage system to realize the traversal of all the data of the knowledge graph to complete the retrieval. Therefore, in the prior art, because the knowledge graph data needs to be moved multiple times during retrieval, the retrieval efficiency of the knowledge graph is low.

[0044] The knowledge graph platform provided by the present application aims to solve the above technical problems of the prior art.

[0045] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0046] Embodiment one

[0047] Figure 1 A structural schematic diagram of a knowledge graph platform provided by the present application embodiment one. As shown in Figure 1 The knowledge graph platform includes a front-end processing platform 11 and a back-end processing platform 12, and the back-end processing platform 12 includes an integrated storage unit and a field programmable gate array processing unit;

[0048] The storage unit is configured to store knowledge graph data;

[0049] The front-end processing platform 11 is configured to receive an access request and parse the access request to obtain a retrieval entity;

[0050] The field programmable gate array processing unit is connected with the front-end processing platform 11 and the storage unit, and is configured to perform information retrieval based on the knowledge graph data stored in the storage unit according to the retrieval entity, and return the retrieval result to the front-end processing platform 11.

[0051] For example, the retrieval entity can be a person, a school, or other entities, which are not limited in the embodiment. The field programmable gate array processing unit can be a circuit architecture customized for specific functions, and has good programmability and flexibility, so that the developer can program it according to the needs.

[0052] In an embodiment, the storage unit includes a flash memory. On the one hand, since the flash memory has a large storage capacity, using the flash memory as the storage unit can support the entire knowledge graph data to be put in at one time, which facilitates the subsequent retrieval of knowledge graph data from the flash memory, thereby improving the retrieval efficiency. On the other hand, since the flash memory also has the characteristics of high read-write bandwidth, based on this characteristic, the knowledge graph data acquisition speed in the retrieval process can be improved, thereby improving the retrieval efficiency.

[0053] In an actual application, the type of the front-end processing platform component is not limited, and in an embodiment, the front-end processing platform includes a general-purpose processor and a memory unit. The general-purpose processor is connected with the memory unit, and is configured to receive an access request, and parse the access request to obtain a retrieval entity; and store the retrieval entity in the memory unit. The field programmable gate array processing unit is connected with the memory unit, and is further configured to obtain the retrieval entity stored in the memory unit. The general-purpose processor is a CPU (Central Processing Unit, Central Processing Unit), and the memory unit is the memory of the CPU. The access request is a knowledge graph retrieval request. In an example, a user initiates a knowledge graph retrieval request by clicking a button, and the general-purpose processor can receive the knowledge graph retrieval request and parse the knowledge graph retrieval request to obtain a retrieval entity. Then, the retrieval entity is stored in the memory unit. Since the field programmable gate array processing unit is connected with the memory unit, the field programmable gate array processing unit can obtain the retrieval entity from the memory unit. In the embodiment, the general-purpose processor parses the retrieval entity from the knowledge graph retrieval request and transmits it to the field programmable gate array processing unit, which can support the subsequent field programmable gate array processing unit to perform knowledge graph retrieval based on the retrieval entity.

[0054] In practical applications, the storage unit and the field-programmable gate array (FPGA) processing unit can be integrated. Specifically, in one embodiment, the storage unit and the FPGA processing unit are integrated on the same PCB (printed circuit board). In this embodiment, on the one hand, by placing the storage unit and the FPGA processing unit on the same PCB, users only need to insert the board into their personal computers when they need to use the knowledge graph platform; this operation is simple and convenient for users. On the other hand, integrating the storage unit and the FPGA processing unit also reduces their space requirements.

[0055] In practical applications, the communication between the field-programmable gate array (FPGA) processing unit and the storage unit can be single-channel or multi-channel. This embodiment does not limit the communication method between the FPGA processing unit and the storage unit. In one embodiment, the FPGA processing unit and the storage unit use a multi-channel communication method. In this embodiment, using a multi-channel communication method can speed up the FPGA processing unit's retrieval of knowledge graph data from the storage unit, thus improving retrieval efficiency.

[0056] The knowledge graph platform provided in this embodiment includes a front-end processing platform and a back-end processing platform. The back-end processing platform includes an integrated storage unit and a field-programmable gate array (FPGA) processing unit. The front-end processing platform receives access requests and parses them to obtain the search entity. The FPGA processing unit retrieves knowledge graph data from the storage unit based on the search entity and returns the search results to the front-end processing platform. In this solution, since the FPGA processing unit can directly retrieve knowledge graph data from the storage unit for retrieval without multiple data transfers, the efficiency of knowledge graph retrieval is improved.

[0057] In practical applications, based on Embodiment 1, the knowledge graph platform described above also includes other parts, which will be illustrated below with a specific embodiment.

[0058] Example 2

[0059] Figure 2 This is a schematic diagram of an integrated board design scheme based on flash memory and FPGA provided in Embodiment 2 of this application. Figure 2 As shown, based on Embodiment 1, the back-end processing platform further includes: a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memory unit; the field-programmable gate array (FPGA) processing unit includes: a knowledge graph retrieval module, a DDR memory control module, a first communication processing module, and a second communication processing module;

[0060] The knowledge graph retrieval module is connected with the DDR memory control module and the second communication processing module, the DDR memory control module is connected with the DDR memory unit, the first communication processing module and the second communication processing module, the first communication processing module is connected with the front-end processing platform, and the second communication processing module is connected with the storage unit.

[0061] The first communication processing module is configured to acquire the retrieval entity and send the retrieval entity to the knowledge graph retrieval module through the DDR memory control module.

[0062] The knowledge graph retrieval module is configured to send an acquisition request to the storage unit through the second communication processing module.

[0063] The storage unit is configured to send corresponding knowledge graph data to the DDR memory control module through the second communication processing module, so that the DDR memory control module stores the knowledge graph data in the DDR memory unit.

[0064] The knowledge graph retrieval module is configured to acquire the knowledge graph data stored in the DDR memory unit through the DDR memory control module for retrieval, and return the retrieval result to the front-end processing platform through the DDR memory control module and the first communication processing module in sequence.

[0065] The DDR (Double Data Rate) memory unit is a memory unit of the FPGA chip. Figure 2 In the embodiment, the type of the DDR memory control module is not limited, and in an example, the DDR memory control module can be a DDR IP core. The DDR IP core is a hardware description language program with memory control function, which can be used to control the storage and acquisition of data in the DDR memory unit, and can also be used to transmit retrieval entity data and knowledge graph data. In the embodiment, the DDR IP core can be transplanted into the FPGA chip, which is convenient for the production and manufacturing of the FPGA chip.

[0066] In the embodiment, the type of the knowledge graph retrieval module is not limited, and in an example, the knowledge graph retrieval module can be a knowledge graph retrieval IP core. Similarly, the knowledge graph retrieval IP core is a hardware description language program with knowledge graph retrieval function, which is used for knowledge graph retrieval according to retrieval entity data. In the embodiment, the knowledge graph retrieval IP core can be transplanted into the FPGA chip, which is convenient for the production and manufacturing of the FPGA chip.

[0067] In an actual application, in one example, the first communication processing module acquires the search entity data in the memory unit of the front-end platform and sends the search entity data to the knowledge graph search module; the knowledge graph search module sends a request for acquiring knowledge graph data to the storage unit according to the received search entity data; the storage unit sends the knowledge graph data corresponding to the request for acquiring knowledge graph data to the DDR memory control module through the second communication processing module after receiving the request; the DDR memory control module controls the storage of the knowledge graph data to the DDR memory unit after receiving the knowledge graph data; the knowledge graph search module acquires the knowledge graph data stored in the DDR memory unit for searching through the DDR memory control module and returns the search result to the memory unit of the front-end platform to support the display of the search result to the user.

[0068] In the embodiment, the IP core is transplanted into the FPGA chip, the production and manufacturing process of the FPGA chip is simplified, and the chip manufacturing efficiency is improved.

[0069] In the embodiment, the components of the first communication processing module are not limited, and in one example, the processing unit and the front-end processing platform are connected through a PCIe (computer high-speed serial bus) interface; the first communication processing module includes a PCIe control module; the PCIe control module is configured to receive the search entity by using an NVMe (non-volatile memory host controller interface protocol) communication protocol. Specifically, for example, the processing unit and the front-end processing platform are connected through a PCIe interface, and the PCIe control module controls the transmission of the search entity data on the PCIe based on the NVMe communication protocol. In the embodiment, the type of the PCIe control module is not limited, and in one example, the PCIe control module can be a PCIe IP core, which can realize data conversion, for example, converting the search entity data into machine code that can be processed by the FPGA chip. In the embodiment, the PCIe IP core converts the search entity data into machine code that can be processed by the FPGA chip, which facilitates the knowledge graph search of the FPGA chip based on the machine code in the subsequent step.

[0070] In the embodiment, the components of the second communication processing module are not limited, and in an example, the second communication processing module includes a SERDES (serializer / deserializer) module and a storage control module; the SERDES module is connected with the knowledge graph retrieval module and is configured to convert the acquisition request into a serial signal; and the storage control module is connected with the SERDES module and the storage unit and is configured to encode the serial signal and send the encoded signal to the storage unit. Specifically, the SERDES module converts the knowledge graph data acquisition request into a serial signal; the storage control module encodes the serial signal to obtain a signal in an encoding format readable by the storage unit, and sends the signal to the storage unit. In the embodiment, the type of the SERDES module is not limited, and in an example, the SERDES module can be a SERDES IP core, which can convert machine code into a serial signal; in the embodiment, the type of the storage control module is not limited, and in an example, the storage control module can be a flash control IP core, which is used to convert the serial signal into a signal in an encoding format readable by the storage unit. In the embodiment, by converting the machine code into a signal in an encoding format readable by the storage unit, the storage unit can read the knowledge graph data acquisition request sent by the FPGA chip and return the corresponding knowledge graph data to the FPGA chip, so as to realize the knowledge graph retrieval process.

[0071] In the embodiment, the IP core is transplanted into the FPGA chip to support the knowledge graph retrieval function, which simplifies the production and manufacturing process of the FPGA chip and improves the chip manufacturing efficiency.

[0072] Embodiment Three

[0073] Figure 3 Another structure diagram of a knowledge graph platform provided in Embodiment Three of the present application is provided. As shown in Figure 3 the knowledge graph platform provided in Embodiment One, the knowledge graph platform further includes an IO (input / output) controller; the IO controller is configured to control the information transmission between the modules in the back-end processing platform. In the embodiment, the IO controller is used to realize the information transmission between the front-end processing platform, the FPGA chip, and the flash storage unit (storage unit), so as to support the implementation of the knowledge graph retrieval function.

[0074] In this embodiment, the components of the IO controller are not limited, and in one example, the IO controller includes a command parser and a scheduler. The general I / O command parser is used to parse the commands, such as read and write commands, from the machine code transmitted by the PCIe under the control of the IO controller, so that the CPU can control the read and write operations of the flash memory unit in the figure through the commands. The knowledge graph parser is used to parse the commands for knowledge graph retrieval, such as read, request, and write commands, from the machine code of the search entity transmitted by the PCIe under the control of the IO controller, so that the FPGA chip can control the read and write of the flash memory unit in the figure through the commands, and the operation of obtaining knowledge graph data. The IO controller further includes a request scheduler, which can sort the multiple commands received by the flash memory unit according to the execution priority according to the memory access scheduling perceived by the priority, so that the flash memory unit executes the commands according to the sorting of the multiple commands; the request scheduler can also determine the order of obtaining the knowledge graph data according to the data layout according to the memory access scheduling perceived by the data layout, so that the flash memory unit performs the return operation of the knowledge graph data according to the order.

[0075] Based on Figure 3 The knowledge graph platform provided includes a front-end processing platform for knowledge graph access request analysis composed of a general processor and a storage-computing integrated back-end platform based on flash and FPGA. The knowledge graph retrieval method that can be implemented is as follows: the front-end processing platform is used to analyze the access request of the knowledge graph, and the analyzed search entity is sent to the back-end platform for information retrieval. The FPGA of the back-end platform performs information retrieval in the knowledge graph database based on flash according to the entity search request of the front-end. The search adopts a FPGA-based graph search accelerator to quickly process the entity search request in the knowledge graph. The searched information is returned to the front-end processing platform through PCIe and visually presented to the user.

[0076] In this embodiment, the IO controller is used to realize the information transmission among the front-end processing platform, the FPGA chip, and the flash memory unit, so as to support the implementation of the knowledge graph retrieval function.

[0077] Embodiment Four

[0078] Figure 4 The knowledge graph retrieval processing flowchart provided in Embodiment Four of the present application is shown. In one example, the user sends a search request instruction to the knowledge graph platform, and then receives the search result returned by the platform. The internal specific processing flow is as follows Figure 4As shown. First, the general processor parses the access request of the knowledge graph, and the result of the parsing is the entity in the knowledge graph that needs to be searched; then, the access request of the knowledge graph can be processed in a separate processing manner or in a batch processing manner on the flash memory and FPGA-based knowledge graph storage and computing integrated platform; subsequently, the FPGA searches for the entity according to the front-end search request (search request micro instruction) and searches for information in the flash memory-based knowledge graph database, and the search adopts the FPGA-based graph search accelerator to quickly process the entity search request in the knowledge graph; finally, the searched information is returned to the front-end platform through the PCIe and visually presented to the user. The result of the general processor parsing the access request of the knowledge graph also includes the relationship between the entities.

[0079] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0080] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the appended claims.

Claims

1. A knowledge graph platform, characterized in that, The application relates to a knowledge graph retrieval system, comprising: a front-end processing platform and a back-end processing platform, wherein the back-end processing platform comprises an integrated storage unit and a field programmable gate array processing unit; the storage unit is configured to store knowledge graph data; the front-end processing platform is configured to receive an access request and parse the access request to obtain a retrieval entity; the field programmable gate array processing unit is connected with the front-end processing platform and the storage unit and is configured to perform information retrieval based on the knowledge graph data stored in the storage unit according to the retrieval entity and return a retrieval result to the front-end processing platform, wherein the back-end processing platform further comprises a DDR memory unit; the field programmable gate array processing unit comprises a knowledge graph retrieval module, a DDR memory control module, a first communication processing module and a second communication processing module; wherein the knowledge graph retrieval module is connected with the DDR memory control module and the second communication processing module, the DDR memory control module is connected with the DDR memory unit, the first communication processing module and the second communication processing module; the first communication processing module is connected with the front-end processing platform; and the second communication processing module is connected with the storage unit; the first communication processing module is configured to obtain the retrieval entity and send the retrieval entity to the knowledge graph retrieval module through the DDR memory control module; the knowledge graph retrieval module is configured to send an acquisition request to the storage unit through the second communication processing module; the storage unit is configured to send corresponding knowledge graph data to the DDR memory control module through the second communication processing module so that the DDR memory control module stores the knowledge graph data into the DDR memory unit; the knowledge graph retrieval module is configured to acquire the knowledge graph data stored in the DDR memory unit through the DDR memory control module for retrieval; and sequentially return the retrieval result to the front-end processing platform through the DDR memory control module and the first communication processing module.

2. The knowledge graph platform of claim 1, wherein, the front-end processing platform comprises a general-purpose processor and a memory unit; the general-purpose processor is connected with the memory unit and is configured to receive an access request, parse the access request to obtain a retrieval entity and store the retrieval entity in the memory unit; the field programmable gate array processing unit is connected with the memory unit and is further configured to acquire the retrieval entity stored in the memory unit.

3. The knowledge graph platform of claim 1, wherein, the processing unit and the front-end processing platform are connected through a PCIe interface; the first communication processing module comprises a PCIe control module; the PCIe control module is configured to receive the retrieval entity by adopting an NVMe communication protocol.

4. The knowledge graph platform of claim 1, wherein, the second communication processing module comprises a SERDES module and a storage control module; the SERDES module is connected with the knowledge graph retrieval module and is configured to convert the acquisition request into a serial signal; The storage control module is connected with the SERDES module and the storage unit, and is configured to encode the serial signal and send the encoded signal to the storage unit.

5. The knowledge graph platform of claim 1, wherein, The storage unit includes a flash memory.

6. The knowledge graph platform of claim 1, wherein, The storage unit and the field programmable gate array processing unit are integrally arranged on the same PCB card.

7. The knowledge graph platform of claim 1, wherein, A multi-channel communication mode is adopted between the field programmable gate array processing unit and the storage unit.

8. The knowledge graph platform of claim 1, wherein, The knowledge graph platform further includes an IO controller. The IO controller is configured to control information transmission between modules in the back-end processing platform.

9. The knowledge graph platform of claim 8, wherein, The IO controller includes a command parser and a scheduler.

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