Six-and-a-half-bit analog-to-digital converter

Abstract

A six-and-a-half-bit analog-to-digital converter belongs to the technical field of measuring and testing instruments. The problem of poor conversion speed and accuracy of the existing analog-to-digital converter is solved. The calibration reference circuit of the present invention uses a given voltage signal, a voltage divider circuit and an isolation circuit to obtain three stable DC voltage signals; the calibration conversion circuit is used to receive the measured voltage signal and the three stable DC voltage signals, and send the measured voltage signal or three accurate and stable DC voltage signals to the measured voltage integrator I and the measured voltage integrator II respectively; when calibrating the analog-to-digital converter, the measured voltage integrator I and the measured voltage integrator II simultaneously and sequentially integrate the three stable DC voltage signals to obtain three time reference signals, and transmit the obtained time reference signals to the FPGA control system, and the FPGA control system performs calibration and analog-to-digital conversion of the analog-to-digital converter. The present invention is suitable for analog-to-digital conversion of signals.

Description

Technical Field

[0001] The invention belongs to the technical field of measuring and testing instruments. Background Art

[0002] The common analog converters in the market are mainly of the following types: integral type, successive approximation type, parallel comparison type / serial parallel type, ∑-Δ modulation type and voltage-frequency conversion type. The following discusses the characteristics and uses of various AD converters.

[0003] The working principle of the integral AD converter is to convert the input voltage into time (pulse width signal) or frequency (pulse frequency), and then obtain the digital value by the timer / counter. Its advantage is that high resolution can be obtained with a simple circuit, but its disadvantage is that the conversion accuracy depends on the integration time, so the conversion rate is extremely low.

[0004] Typical devices of successive approximation AD, such as TLC0831, are composed of a comparator and a DA converter through successive comparison logic. Starting from the MSB, the input voltage is compared with the output of the built-in DA converter for each bit in sequence, and the digital value is output after n comparisons. Its circuit scale is medium. Its advantages are high speed and low power consumption. It is cheap at low resolution (<12 bits), but very expensive at high precision (>12 bits). At present, the maximum resolution of integrated products is 16-bit binary and the maximum speed can reach 10MHz. It is mainly suitable for high-speed and low-resolution industrial instruments.

[0005] Typical parallel comparison AD devices such as TLC5510 use multiple comparators and perform conversion only once, also known as Flash (fast) type. Due to the extremely high conversion rate, the conversion of n bits requires 2n-1 comparators, so the circuit scale is also very large and the price is high. It is only suitable for fields with particularly high speeds such as video AD converters. The structure of serial-parallel comparison AD is between the parallel type and the successive comparison type. The most typical one is composed of 2 n / 2-bit parallel AD converters and DA converters, and the conversion is achieved by two comparisons, so it is called Halfflash (semi-fast) type. There are also AD conversions that are divided into three or more steps, called multi-step / subranging ADs, and from the perspective of conversion timing, they can be called pipelined ADs. Modern hierarchical ADs also add functions such as performing digital operations on multiple conversion results to correct characteristics. This type of AD has a higher speed than the successive comparison type and a smaller circuit scale than the parallel type.

[0006] Typical ∑-Δ AD devices, such as AD7705, consist of an integrator, a comparator, a 1-bit DA converter, and a digital filter. The principle is similar to the integral type, converting the input voltage into a time (pulse width) signal, and processing it with a digital filter to obtain a digital value. The digital part of the circuit is easy to monolithic, so it is easy to achieve high resolution, but the linearity and accuracy are not high, and it is mainly used for audio and low-frequency measurements.

[0007] Typical devices of voltage-frequency conversion, such as AD650, realize analog-to-digital conversion by indirect conversion. The principle is to first convert the input analog signal into frequency, and then use a counter to convert the frequency into a digital quantity. Theoretically, the resolution of this AD can be increased almost infinitely as long as the sampling time can meet the output frequency resolution requirements. Its advantages are high resolution, low power consumption and low price, but it requires an external counting circuit to complete the AD conversion together, which is also limited by the device frequency, and the price is too high to achieve high resolution.

[0008] In summary, existing analog-to-digital converters have problems with poor resolution, conversion speed and accuracy, and cannot meet the accuracy requirements of a 6-bit and a half analog-to-digital converter. Summary of the invention

[0009] The invention aims to solve the problem of poor conversion speed and accuracy of the existing analog-to-digital converter and proposes a six-and-a-half-bit analog-to-digital converter.

[0010] The six-and-a-half-bit analog-to-digital converter of the present invention comprises: a calibration conversion circuit 1, a calibration reference circuit 2, a DC reference circuit 3, a low-bit reference circuit 4, a high-bit reference circuit 5, an FPGA control circuit 6, a serial output circuit 7, a measured voltage integrator I8 and a measured voltage integrator II9;

[0011] The DC reference circuit 3 uses a given voltage signal, a voltage divider circuit and an isolation circuit to obtain three stable DC voltage signals; and sends the three stable DC voltage signals to the calibration conversion circuit 1, the high-bit reference circuit 5 and the low-bit reference circuit 4 at the same time;

[0012] The calibration conversion circuit 1 is used to receive the measured voltage signal and three stable DC voltage signals, and simultaneously send the measured voltage signal or three accurate and stable DC voltage signals to the measured voltage integrator I8 and the measured voltage integrator II9;

[0013] When calibrating the analog-to-digital converter, the measured voltage integrator I8 and the measured voltage integrator II9 simultaneously and sequentially integrate the three stable DC voltage signals to obtain three time reference signals, and transmit the obtained three time reference signals to the FPGA control circuit 6;

[0014] The high-order reference circuit 5 is used to integrate the high-order reference voltage, and output the time pulse signal generated by the integrator as the high-order reference signal to the FPGA control circuit 6;

[0015] The low-bit reference integrator (4) is used to integrate the low-bit reference voltage, and output the time pulse signal generated by the integrator as the low-bit reference signal to the FPGA control circuit 6;

[0016] The FPGA control circuit 6 is used to select the calibration mode and the measurement mode of the analog-to-digital converter. In the calibration mode of the analog-to-digital converter, the calibration conversion circuit 1 is controlled to output three stable DC voltage signals; and the high-order time pulse signal and the low-order time pulse signal of the three standard time pulse signals generated by the measured voltage integrator I8 and the measured voltage integrator II9 are compared with the high-order reference signal and the low-order reference signal respectively, and the high-order reference signal and the low-order reference signal are calibrated;

[0017] In the measurement mode, the FPGA control circuit 6 controls the calibration conversion circuit 1 to output the measured signal, and uses the low drift control algorithm to perform analog-to-digital conversion on the measured signal, obtains the digital signal of the measured signal, and transmits the digital signal of the measured signal to the serial output circuit 7;

[0018] The serial output circuit 7 is used to output the received digital signal in serial form.

[0019] Furthermore, in the present invention, the high-bit reference circuit 5 uses a high-speed operational amplifier.

[0020] Furthermore, in the present invention, the FPGA control circuit 6 is implemented using a low drift control algorithm, and the low drift control formula is:

[0021] U X =K(T 1 +1 / M×T 2 )+T 0

[0022] Among them, U X is the measured voltage value, K is the linear coefficient, T 1 is the time value of the high-order reference integrator, T 2 is the time value of the low-order reference integrator, T 0 is the zero point offset value, and M is the ratio of the reference voltage of the low-order reference integrator to that of the high-order reference integrator.

[0023] The present invention includes a calibration mode and a measurement mode, and the timing calibration is implemented to ensure the accuracy of the measurement conversion. At the same time, two integrators are used for data processing to effectively improve the data processing speed. The structure of the present invention is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the electrical principle block diagram of the six-and-a-half-bit analog-to-digital converter of the present invention. DETAILED DESCRIPTION

[0025] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0027] Specific implementation method 1: The following is combined Figure 1 The present embodiment is described. The six-and-a-half-bit analog-to-digital converter of the present embodiment comprises: a calibration conversion circuit 1, a calibration reference circuit 2, a DC reference circuit 3, a low-bit reference circuit 4, a high-bit reference circuit 5, an FPGA control circuit 6, a serial output circuit 7, a measured voltage integrator I8 and a measured voltage integrator II9;

[0028] The DC reference circuit 3 uses a given voltage signal, a voltage divider circuit and an isolation circuit to obtain three stable DC voltage signals; and sends the three stable DC voltage signals to the calibration conversion circuit 1, the high-bit reference circuit 5 and the low-bit reference circuit 4 at the same time;

[0029] The calibration conversion circuit 1 is used to receive the measured voltage signal and three stable DC voltage signals, and simultaneously send the measured voltage signal or three accurate and stable DC voltage signals to the measured voltage integrator I8 and the measured voltage integrator II9;

[0030] When calibrating the analog-to-digital converter, the measured voltage integrator I8 and the measured voltage integrator II9 simultaneously and sequentially integrate the three stable DC voltage signals to obtain three time reference signals, and transmit the obtained three time reference signals to the FPGA control circuit 6;

[0031] The high-order reference circuit 5 is used to integrate the high-order reference voltage, and output the time pulse signal generated by the integrator as the high-order reference signal to the FPGA control circuit 6;

[0032] The low-bit reference integrator (4) is used to integrate the low-bit reference voltage, and output the time pulse signal generated by the integrator as the low-bit reference signal to the FPGA control circuit 6;

[0033] The FPGA control circuit 6 is used to select the calibration mode and the measurement mode of the analog-to-digital converter. In the calibration mode of the analog-to-digital converter, the calibration conversion circuit 1 is controlled to output three stable DC voltage signals; and the high-order time pulse signal and the low-order time pulse signal of the three standard time pulse signals generated by the measured voltage integrator I8 and the measured voltage integrator II9 are compared with the high-order reference signal and the low-order reference signal respectively, and the high-order reference signal and the low-order reference signal are calibrated;

[0034] In the measurement mode, the FPGA control circuit 6 controls the calibration conversion circuit 1 to output the measured signal, and uses the low drift control algorithm to perform analog-to-digital conversion on the measured signal, obtains the digital signal of the measured signal, and transmits the digital signal of the measured signal to the serial output circuit 7;

[0035] The serial output circuit 7 is used to output the received digital signal in serial form.

[0036] Furthermore, in this embodiment, the high-bit reference circuit 5 uses a high-speed operational amplifier.

[0037] Furthermore, in this embodiment, the FPGA control circuit 6 is implemented using a low drift control algorithm, and the low drift control formula is:

[0038] U X =K(T 1 +1 / M×T 2 )+T 0

[0039] Among them, U X is the measured voltage value, K is the linear coefficient, T 1 is the time value of the high-order reference integrator, T 2 is the time value of the low-order reference integrator, T 0 is the zero point offset value, and M is the ratio of the reference voltage of the low-order reference integrator to that of the high-order reference integrator.

[0040] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and features described herein may be combined in a manner different from that described in the original claims. It will also be understood that the features described in conjunction with the individual embodiments may be used in other described embodiments.

Claims

1. Six and a half bit analog-to-digital converter, It is characterized in that include: A calibration conversion circuit (1), a calibration reference circuit (2), a DC reference circuit (3), a low-bit reference circuit (4), a high-bit reference circuit (5), an FPGA control circuit (6), a serial output circuit (7), a measured voltage integrator I (8), and a measured voltage integrator II (9); The DC reference circuit (3) uses a given voltage signal, a voltage divider circuit and an isolation circuit to obtain three stable DC voltage signals; and simultaneously sends the three stable DC voltage signals to the calibration conversion circuit (1), the high-order reference circuit (5) and the low-order reference circuit (4); The calibration conversion circuit (1) is used for receiving a measured voltage signal and three stable DC voltage signals, and simultaneously sending the measured voltage signal or the three accurate and stable DC voltage signals to a measured voltage integrator I (8) and a measured voltage integrator II (9); When calibrating the analog-to-digital converter, the measured voltage integrator I (8) and the measured voltage integrator II (9) simultaneously and sequentially integrate the three stable DC voltage signals to obtain three time reference signals, and transmit the obtained three time reference signals to the FPGA control circuit (6); The high-order reference circuit (5) is used to integrate the high-order reference voltage, and output the time pulse signal generated by the integrator as the high-order reference signal to the FPGA control circuit (6); The low-bit reference circuit (4) is used to integrate the low-bit reference voltage, and output the time pulse signal generated by the integrator as a low-bit reference signal to the FPGA control circuit (6); The FPGA control circuit (6) is used to select a calibration mode and a measurement mode of the analog-to-digital converter. In the calibration mode of the analog-to-digital converter, the calibration conversion circuit (1) is controlled to output three stable DC voltage signals; and the high-order time pulse signal and the low-order time pulse signal of the three standard time pulse signals generated by the measured voltage integrator I (8) and the measured voltage integrator II (9) are respectively compared with the high-order reference signal and the low-order reference signal, and the high-order reference signal and the low-order reference signal are calibrated; In the measurement mode, the FPGA control circuit (6) controls the calibration conversion circuit (1) to output the measured signal, and uses the low drift control algorithm to perform analog-to-digital conversion on the measured signal to obtain a digital signal of the measured signal, and transmits the digital signal of the measured signal to the serial output circuit (7); The serial output circuit (7) is used for serially outputting the received digital signal.

2. The six-and-a-half-bit analog-to-digital converter according to claim 1, It is characterized in that The high-bit reference circuit (5) uses a high-speed operational amplifier.

3. The six-and-a-half-bit analog-to-digital converter according to claim 1, It is characterized in that The FPGA control circuit (6) is implemented using a low drift control algorithm, and the low drift control formula is: U X =K(T 1 +1 / M×T 2 )+T 0 Among them, U X is the measured voltage value, K is the linear coefficient, T 1 is the time value of the high-order reference integrator, T 2 is the time value of the low-order reference integrator, T 0 is the zero point offset value, and M is the ratio of the reference voltage of the low-order reference integrator to that of the high-order reference integrator.

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