A memory computing circuit, an in-memory computing circuit and a chip thereof

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a storage operation circuit, an SRAM in-memory computing circuit with TCAM and logic operation functions and a chip. Each basic storage operation circuit comprises two storage units T1 and T2 for storing data and two operation logic units ALU1 and ALU2. The operation logic units ALU1 and ALU2 each comprise a control end, a first input end, a second input end and an output end. The operation logic unit ALU1 is an AND gate when the control end is connected to VSS and is an XNOR gate when the control end is connected to VDD. The operation logic unit ALU2 is an XOR gate when the control end is connected to VSS and is an OR gate when the control end is connected to VDD. The input end of the operation logic unit ALU1 is connected to an external input IN and the storage unit T1. The input end of the operation logic unit ALU2 is connected to the output of the operation logic unit ALU1 and the storage unit T2. The application solves the problem that a conventional SRAM storage operation circuit is difficult to implement a composite Boolean logic operation in a single cycle, and improves the operation performance and stability of the storage operation circuit.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a storage operation circuit, and an SRAM in-memory computing circuit and chip with TCAM and logic operation functions and adopting the storage operation circuit as a basic circuit. BACKGROUND

[0002] Machine learning, image recognition and edge computing are all data processing tasks with large data computing scales, and most existing artificial intelligence applications need to be based on the above technologies. The continuous development and wide application of artificial intelligence have caused a development bottleneck for data processing devices based on the traditional von Neumann architecture, that is, data processing devices cannot achieve an effective balance between computing efficiency and power consumption; the improvement of computing efficiency usually causes a substantial increase in device running power consumption.

[0003] Under this background, the concept of in-memory computing (Computing in Memory, abbreviated as CIM) is proposed. Since in-memory computing does not need to transmit data from the memory to the processor, and can perform computing inside the memory array, in-memory computing greatly reduces the access energy consumption in the computing process, greatly increases the throughput, and greatly improves the computing speed and energy efficiency. It can be said without exaggeration that the birth of in-memory computing technology breaks through the von Neumann bottleneck and breaks the "memory wall" in the traditional computing architecture, and has revolutionary significance for the "computing power era".

[0004] Among them, considering that the static random access memory (Static Random-Access Memory, SRAM) has a fast reading speed and good compatibility with advanced logic processes, the in-memory computing technology based on SRAM first attracts the attention of domestic and foreign scholars. The in-memory computing design based on SRAM can not only realize the basic read-write function of SRAM, but also can realize the computing function by setting the bit line voltage, changing the cell structure and modifying the peripheral circuit. Due to the repeatability of the array cell structure, simple and repetitive operations in in-memory computing are relatively easy to implement.

[0005] Boolean operation is a simple repetitive operation, so it is very promising to realize Boolean operation in the in-memory computing of SRAM memory. Compound Boolean operation requires multiple operands to participate together, so it is often necessary to simultaneously turn on multiple row word lines in the storage array to perform compound Boolean operation in the SRAM memory. However, simultaneously turning on multiple row word lines in the memory will cause read disturbance and other problems. At the same time, in the existing SRAM computing circuit, it is almost necessary to use two or more periods to realize compound Boolean logic operation, which will also bring difficulties to the timing control in the running process of the circuit. In summary, there is a lack of circuit structure capable of realizing compound Boolean logic operation in a single period in the existing SRAM computing circuit. SUMMARY

[0006] In order to solve the problem that the existing SRAM computing circuit is difficult to realize compound Boolean logic operation in a single period, the present application provides an SRAM in-memory computing circuit and chip with TCAM and logic operation function using a storage operation circuit as a basic circuit.

[0007] The present application realizes the following technical solutions:

[0008] A storage operation circuit, the storage operation circuit comprising two storage units T1 and T2 for storing data, and two operation logic units ALU1 and ALU2; wherein, the ALU1 and the ALU2 each comprise a control end, a first input end, a second input end and an output end.

[0009] The operation logic unit ALU1 is an AND gate when the control end is connected to VSS, and is an XNOR gate when the control end is connected to VDD. The operation logic unit ALU2 is an XOR gate when the control end is connected to VSS, and is an OR gate when the control end is connected to VDD.

[0010] The first input end of the operation logic unit ALU1 is connected to one of the storage nodes Q1 of the storage unit T1; the second input end of the operation logic unit ALU1 is connected to an independent input signal line IN; and the output end of the operation logic unit ALU1 is Y1.

[0011] The first input end of the operation logic unit ALU2 is connected to the output end Y1 of the operation logic unit ALU1; the second input end of the operation logic unit ALU2 is connected to one of the storage nodes Q2 of the storage unit T2; and the output end of the operation logic unit ALU2 is Y2.

[0012] The output terminal Y1 of the ALU1 has three application modes, i.e. as the output terminal of the operation result when the ALU1 performs the "and" operation or the "XOR" operation alone. The output terminal Y2 of the ALU2 has three application modes, i.e. (1) as the output terminal of the operation result when the ALU2 performs the "or" operation or the "XOR" operation alone; (2) as the output terminal of the operation result when the TI, T2, ALU1 and ALU2 perform the four compound Boolean logic operations; and (3) as the output terminal of the matching result when the TI, T2, ALU1 and ALU2 perform the TCAM addressing operation.

[0013] As a further improvement of the present application, the ALU1 circuit comprises two PMOS tubes PM3 and PM4 and two NMOS tubes NM5 and NM6. The source of the PM3 is connected to the control signal SD1; the gate of the PM3, the source of the NM5 and the gate of the NM5 are connected and connected to the input signal line IN; the gate of the PM4, the gate of the NM5 and the source of the NM6 are connected and connected to the storage node Q1 of the storage unit T1; the drain of the PM4, the drain of the NM5 and the drain of the NM6 are connected and serve as the output node Y1; the drain of the PM3 is connected to the source of the PM4.

[0014] As a further improvement of the present application, the ALU2 circuit comprises two PMOS tubes PM7 and PM8 and two NMOS tubes NM11 and NM12. The gate of the PM7, the source of the PM8 and the gate of the NM11 are connected and connected to the output node Y1 of the ALU1; the gate of the PM8, the source of the PM7 and the gate of the NM12 are connected and connected to the storage node Q2 of the storage unit T2; the drain of the PM8, the drain of the PM7 and the drain of the NM11 are connected and serve as the output node Y2 of the ALU2; the source of the NM11 is connected to the drain of the NM12; the source of the NM12 is connected to the control signal SD2.

[0015] As a further improvement of the present application, the storage units T1 and T2 adopt the 6T storage unit comprising six transistors. The 6T storage unit comprises two PMOS tubes PM1 and PM2 and four NMOS tubes NM1, NM2, NM3 and NM4. The PM1 and the NM1 constitute an inverter structure, the PM2 and the NM2 constitute another inverter structure, and the NM3 and the NM4 serve as transmission tubes respectively. The sources of the PM1 and the PM2 are connected to VDD, and the sources of the NM1 and the NM2 are connected to VSS; the drain of the PM1, the drain of the NM1, the gate of the PM2 and the gate of the NM2 are connected and serve as the storage node Q1 and are connected to the drain of the NM3, the gate of the NM3 is connected to the word line WL, and the source of the NM3 is connected to the bit line BL; the drain of the PM2, the drain of the NM2, the gate of the PM1 and the gate of the NM1 are connected and serve as the storage node QB1 and are connected to the drain of the NM4, the gate of the NM4 is connected to the word line WL, and the source of the NM4 is connected to the bit line BLB.

[0016] In the storage operation circuit provided by the present application, the operation functions that can be realized are as follows:

[0017] 1. The storage unit T1 and the operation logic unit ALU1 are used as the basic circuit for realizing the AND operation and the XNOR operation in the storage operation circuit. IN and Q1 are two operation numbers, and Y1 is the output result.

[0018] When SD1=VSS, the ALU1 realizes the AND operation, that is:

[0019] Y1=AND(IN, Q1)

[0020] When SD1=VDD, the ALU1 realizes the XNOR operation, that is:

[0021] Y1=XNOR(IN, Q1).

[0022] 2. The storage unit T2 and the operation logic unit ALU2 are used as the basic circuit for realizing the OR operation and the XOR operation in the storage operation circuit. Y1 and Q2 are two operation numbers, and Y2 is the output result.

[0023] When SD2=VSS, the ALU2 realizes the OR operation, that is:

[0024] Y2=XOR(Y1, Q2)

[0025] When SD1=VDD, the ALU2 realizes the XOR operation.

[0026] Y2=OR(Y1, Q2)

[0027] 3. The storage units T1 and T2 and the operation logic units ALU1 and ALU2 are used as the basic circuit for realizing four kinds of compound Boolean logic operations. IN, Q1 and Q2 are three operation numbers, and Y2 is the output result. The expressions of the four kinds of compound Boolean logic operations are as follows:

[0028]

[0029] In the storage operation circuit provided by the present application, the realization of the TCAM addressing operation is as follows:

[0030] The control signals of the storage operation circuit including T1, T2, ALU1 and ALU2 are set as SD1=VSS and SD2=VSS. The two-bit binary number formed by the node data Q1 and Q2 stored in the two storage units T1 and T2 can be used to represent three state bits; wherein, “10” represents TCAM state 1, “11” represents TCAM state 2, and “01” represents TCAM state x. The two-bit binary number represented by Q1 and Q2 is taken as target data, and IN represents search data; when the value output by Y2 is “1”, it indicates that the target data matches the search data, and when the value output by Y2 is “0”, it indicates that the target data does not match the search data.

[0031] The application further provides an SRAM in-memory computing circuit with TCAM and logic operation functions, which comprises an SRAM storage array, a logic unit array, a timing control circuit, an input signal line, a bit line pair, a precharge circuit, a word line, a word line driving module, a row decoding module, and a column output circuit.

[0032] The SRAM storage array is formed by 4N 2 identical storage units in a 2N*2N array form; each storage unit contains two opposite storage nodes Q and QB.

[0033] The logic unit array is formed by a plurality of operation logic units corresponding to the storage units one by one. In the logic unit array, the operation logic units corresponding to the storage units in the odd-numbered columns are all operation logic units ALU1, and the operation logic units corresponding to the storage units in the even-numbered columns are all operation logic units ALU2.

[0034] The timing control circuit is used to generate clock signals required by each functional module.

[0035] The input signal line is connected to each column of operation logic units ALU1 and is used to input corresponding input signals IN to each operation logic unit ALU1.

[0036] The bit line pair includes 2N pairs of bit lines BL and BLB; each storage unit in each column is connected to the same group of bit lines BL and BLB.

[0037] The precharge circuit is used to perform a precharge operation on the bit lines BL and BLB connected to each column of storage units in the SRAM storage array.

[0038] The word line WL is used to input corresponding word line signals to each storage unit in the SRAM storage array.

[0039] The word line driving module is used to control the opening or closing of the word line WL connected to each storage unit in the storage array.

[0040] The row decoding module is configured to decode the input signal and control the word line driving module according to the decoding result.

[0041] The column output circuit is connected with the bit line BL and BLB of each column of memory cells in the SRAM memory array through a sense amplifier SA, and further outputs the storage data of the memory cells in any column or the calculation result of the operation logic unit.

[0042] In particular, the two memory cells T1 and T2 located in the same row in the SRAM memory array and the corresponding ALU1 and ALU2 both constitute a storage operation circuit as in Embodiment 1 and can realize the complete function of the basic circuit.

[0043] In the formula, the number of sense amplifiers inside the SRAM memory calculation circuit is 4N, and BL or BLB in each column of memory cells is respectively used as one-way input of a corresponding group of sense amplifiers, and the other-way input of the sense amplifier is a reference level Vref; when the level of BL or BLB is higher than the reference level Vref, the sense amplifier outputs a high level, otherwise a low level.

[0044] The application also includes a memory and calculation chip, which is an integrated circuit packaged by the aforementioned SRAM memory-in-computation circuit with TCAM and logic operation functions. The interface of the memory and calculation chip at least includes: a power supply interface, a ground interface, a charging interface, a control signal interface, an input signal interface, a switching signal, a word line interface, and an output signal interface.

[0045] In the formula, the power supply interface VDD is used to connect the power supply. The ground interface VSS is used to connect the ground. The charging interface PRE is used to input the control signal for adjusting the charging state of each bit line. The control signal interface SD is used to input the control signal for adjusting the running state of each operation logic unit. The input signal interface IN is used to input the corresponding input signal to each operation logic unit ALU1. The switching signal SW is used to input a switching signal to the circuit, and the switching signal is used to adjust the access state of the memory cell and the pre-budget logic unit on the bit line. Further, the circuit is switched between the normal read-write and memory-in-computation working modes.

[0046] The word line interface WL is used to input the corresponding word line signal to each memory cell, and the word line signal is used to adjust the access state of each memory cell on each bit line. The output signal interface Y is used to read the data stored in each memory cell or read the logic operation result of each operation logic unit.

[0047] The technical scheme provided by the application has the following beneficial effects:

[0048] This invention designs a novel storage and operation circuit structure using only a few transistors. This circuit structure can simultaneously perform data storage and reading / writing, simple logic operations, complex Boolean logic operations, and TCAM addressing operations. The circuit designed in this invention can be applied to large-scale SRAM storage circuits, resulting in an SRAM in-memory computing circuit with TCAM addressing and complex logic operation capabilities. A significant advantage of this circuit is that it can perform composite Boolean logic operations within a single cycle; and by rationally arranging various signal lines, it can achieve conflict-free operation of each function, improving circuit stability. This overcomes the problems of read interference and the need for multiple cycles to perform a complex Boolean logic operation present in existing in-memory computing circuits. Attached Figure Description

[0049] Figure 1 This is a circuit diagram of the storage and operation circuit provided in Embodiment 1 of the present invention.

[0050] Figure 2 for Figure 1 Detailed circuit diagram of the 6T memory cell.

[0051] Figure 3 for Figure 1 A feasible circuit structure for ALU1 used in this paper.

[0052] Figure 4 for Figure 1 A feasible circuit structure for ALU2 used in this paper.

[0053] Figure 5 The storage and operation circuit in Embodiment 1 of the present invention adopts Figures 2-4 A complete circuit diagram for a specific circuit structure.

[0054] Figure 6 This is a circuit architecture diagram of the SRAM in-memory computing circuit with TCAM and logic operation functions provided in Embodiment 2 of the present invention.

[0055] Figure 7 This is a schematic diagram of the circuit provided in Embodiment 2 of the present invention when implementing TCAM addressing operation.

[0056] Figure 8 The results of 5000 Monte Carlo simulations when the in-memory computing chip performs TCAM operations with a target data of 1001.

[0057] Figure 9 The results of 5000 Monte Carlo simulations when the in-memory computing chip performs TCAM operations with a target data of 100X.

[0058] Figure 10The average energy consumption statistical chart of the storage and computing chip provided in the embodiment executing four kinds of composite logic operations under different process angles is shown. DETAILED DESCRIPTION

[0059] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0060] Embodiment 1

[0061] The storage and operation circuit provided in the embodiment, as shown in the figure, comprises two storage units T1 and T2 for storing data, and two operation logic units ALU1 and ALU2; wherein, the ALU1 and ALU2 each comprises a control end, a first input end, a second input end and an output end. Figure 1 In the basic circuit provided in the embodiment, the operation logic unit ALU1 is an AND gate when the control end is connected to VSS, and is an XNOR gate when the control end is connected to VDD. The operation logic unit ALU2 is an XOR gate when the control end is connected to VSS, and is an OR gate when the control end is connected to VDD.

[0062] The first input end of the operation logic unit ALU1 is connected to one of the storage nodes Q1 of the storage unit T1; the second input end of the operation logic unit ALU1 is connected to an independent input signal line IN; and the output end of the operation logic unit ALU1 is Y1.

[0063] The first input end of the operation logic unit ALU2 is connected to the output end Y1 of the operation logic unit ALU1; the second input end of the operation logic unit ALU2 is connected to one of the storage nodes Q2 of the storage unit T2; and the output end of the operation logic unit ALU2 is Y2.

[0064] The application mode of the output end Y1 of the ALU1 is one, that is, as the operation result output end when the ALU1 performs the AND / XNOR operation alone. The application mode of the output end Y2 of the ALU2 is three, which are respectively: (1) as the operation result output end when the ALU2 performs the OR / XOR operation alone; (2) as the operation result output end when the TI, T2, ALU1, ALU2 collectively perform four kinds of composite Boolean logic operations; and (3) as the matching result output end when the TI, T2, ALU1, ALU2 collectively implement the TCAM addressing operation.

[0065]

[0066] ​Based on the foregoing circuit structure, when the arithmetic logic units ALU1 and ALU2 are not involved, the storage units T1 and T2 can be used as a conventional storage circuit to store 1 or 2 bytes of data. When the storage units T1 and T2 work in cooperation with the arithmetic logic units ALU1 and ALU2, the storage arithmetic circuit can also realize the following operation functions:

[0067] 1. The storage unit T1 and the arithmetic logic unit ALU1 are used as the basic circuit to realize the AND operation and the XNOR operation in the storage arithmetic circuit. IN and Q1 are two operands, and Y1 is the output result.

[0068] When SD1 = VSS, ALU1 realizes the AND operation, i.e.:

[0069] Y1 = AND (IN, Q1)

[0070] When SD1 = VDD, ALU1 realizes the XNOR operation, i.e.:

[0071] Y1 = XNOR (IN, Q1).

[0072] 2. The storage unit T2 and the arithmetic logic unit ALU2 are used as the basic circuit to realize the OR operation and the XOR operation in the storage arithmetic circuit. Y1 and Q2 are two operands, and Y2 is the output result.

[0073] When SD2 = VSS, ALU2 realizes the OR operation, i.e.:

[0074] Y2 = XOR (Y1, Q2)

[0075] When SD1 = VDD, ALU2 realizes the XOR operation, i.e.:

[0076] Y2 = OR (Y1, Q2)

[0077] 3. The storage units T1 and T2 and the arithmetic logic units ALU1 and ALU2 are used as the basic circuit to realize four kinds of compound Boolean logic operations. IN, Q1, and Q2 are three operands, and Y2 is the output result. The expressions of the four kinds of compound Boolean logic operations are as follows:

[0078]

[0079] Specifically, the truth table of the first compound Boolean logic operation Y2 = (IN·Q1)⊕Q2 is as follows:

[0080] Table 1: Truth table of the first compound Boolean logic operation

[0081] Y2 = (IN·Q1)⊕Q2

[0082]

[0083] The truth table of the second composite Boolean logic operation Y2 = (IN-Q1) + Q2 is as follows:

[0084] Table 2: Truth table of the second composite Boolean logic operation

[0085] Y2 = (IN-Q1) + Q2

[0086]

[0087] The truth table of the third composite Boolean logic operation is as follows:

[0088] Table 3: Truth table of the third composite Boolean logic operation

[0089]

[0090]

[0091] The truth table of the fourth composite Boolean logic operation is as follows:

[0092] Table 4: Truth table of the fourth composite Boolean logic operation

[0093]

[0094]

[0095] In particular, the simple circuit composed of the storage units T1, T2 and the operation logic units ALU1, ALU2 can also be used to provide an addressing function. In the storage operation circuit provided in the embodiment, the TCAM addressing operation is implemented in the following manner:

[0096] The control signals of the storage operation circuit containing T1, T2, ALU1 and ALU2 are set as SD1 = VSS and SD2 = VSS. The two-bit binary number formed by the node data Q1 and Q2 stored in the two storage units T1 and T2 can be used to represent three state bits; wherein "10" represents TCAM state 1, "11" represents TCAM state 2, and "01" represents TCAM state x. The two-bit binary number represented by Q1 and Q2 is used as target data, and IN represents search data; when the value of Y2 output is "1", it indicates that the target data matches the search data, and when the value of Y2 output is "0", it indicates that the target data does not match the search data.

[0097] The foregoing defines the functions of each basic unit in the storage operation circuit in the embodiment, and thus as long as a circuit with corresponding functions is designed and connected and used, the circuit functions described above can be realized. That is, the storage units T1 and T2 and the operation logic units ALU1 and ALU2 in the embodiment are basic functional units of the storage operation circuit. However, the elements and circuit connection relationship of each basic functional unit are not limited to a certain form.

[0098] Specifically, the storage units T1 and T2 in the embodiment can adopt conventional storage unit circuits with different numbers of transistors, such as 6T, 8T, 10T, 12T, and the like. For example, in the embodiment, a corresponding storage operation circuit is designed by taking a 6T storage unit containing six transistors as an example. The 6T storage unit contains two opposite storage nodes Q1 and QB1. As shown in the figure, the 6T storage unit includes two PMOS transistors PM1 and PM2 and four NMOS transistors NM1, NM2, NM3, and NM4. Among them, PM1 and NM1 form an inverter structure, PM2 and NM2 form another inverter structure, and NM3 and NM4 are transmission tubes. The sources of PM1 and PM2 are connected to VDD, and the sources of NM1 and NM2 are connected to VSS; the drain of PM1, the drain of NM1, the gate of PM2, and the gate of NM2 are connected to form a storage node Q1 and are connected to the drain of NM3, the gate of NM3 is connected to a word line WL, and the source of NM3 is connected to a bit line BL. The drain of PM2, the drain of NM2, the gate of PM1, and the gate of NM1 are connected to form a storage node QB1 and are connected to the drain of NM4, the gate of NM4 is connected to the word line WL, and the source of NM4 is connected to a bit line BLB. Figure 2

[0099] ALU1 and ALU2 are special gate circuits designed and applied in the embodiment. Specifically, as shown in the figure, the ALU1 circuit provided in the embodiment includes two PMOS transistors PM3 and PM4 and two NMOS transistors NM5 and NM6. Among them, the source of PM3 is connected to a control signal SD1. The gate of PM3, the source of NM5, and the gate of NM5 are connected and connected to an input signal line IN. The gate of PM4, the gate of NM5, and the source of NM6 are connected and connected to the storage node Q1 of the storage unit T1; the drain of PM4, the drain of NM5, and the drain of NM6 are connected and serve as an output node Y1. The drain of PM3 is connected to the source of PM4. Figure 3

[0100] As shown in the figure, the ALU2 circuit provided in the embodiment includes two PMOS transistors PM7 and PM8 and two NMOS transistors NM9 and NM10. Among them, the source of PM7 is connected to a control signal SD2. The gate of PM7, the source of NM9, and the gate of NM9 are connected and connected to an input signal line IN. The gate of PM8, the gate of NM9, and the source of NM10 are connected and connected to the storage node QB1 of the storage unit T2; the drain of PM8, the drain of NM9, and the drain of NM10 are connected and serve as an output node Y2. The drain of PM7 is connected to the source of PM8. Figure 4 ​​As shown, the circuit of ALU2 includes two PMOS tubes PM7, PM8, and two NMOS tubes NM11, NM12. The gate of PM7, the source of PM8, and the gate of NM11 are connected and connected to the output node Y1 of ALU1. The gate of PM8, the source of PM7, and the gate of NM12 are connected and connected to the storage node Q2 of the storage unit T2. The drain of PM8, the drain of PM7, and the drain of NM11 are connected and serve as the output node Y2 of ALU2. The source of NM11 is connected to the drain of NM12; the source of NM12 is connected to the control signal SD2.

[0101] Based on the above design, the final circuit diagram provided by the embodiment includes T1, T2, ALU1, and ALU2, as shown in Figure 5 It is emphasized that the scheme of Figure 5 provided by the embodiment is only one of the ways to claim the storage operation circuit, and does not serve as a feature limiting the protection scope of the case. For example, Figure 3 and Figure 4 ALU1 and ALU2 in

[0102] Embodiment 2

[0103] The scheme provided by Embodiment 1 is a basic circuit for realizing storage function, simple logic operation, complex Boolean logic operation, and TCAM addressing function. On the basis of Embodiment 1, the embodiment further provides a large-scale storage-in-computing circuit including a large number of basic circuits as in Embodiment 1.

[0104] Specifically, as shown in Figure 6 , the SRAM storage-in-computing circuit provided by the embodiment with TCAM and logic operation functions includes an SRAM storage array, a logic unit array (Embedded Multiplexed ALU), a timing control circuit (Timing Control), an input signal line (IN), a bit line pair (BL, BLB), a precharge circuit (Precharge Control), a word line (WL), a word line driving module, a row decoding module (Row Decoder), and a column output circuit (Column Output Circuit).

[0105] Among them, the SRAM storage array is composed of 4N 2The same storage unit constitutes a 2N*2N array; each storage unit contains two inverted storage nodes Q and QB. The SRAM storage array in this embodiment includes a plurality of storage units 6T, and also includes a sensitive amplifier connected to each bit line. For example, in this embodiment, the number of sensitive amplifiers is 4N, and BL or BLB in each column storage unit is respectively input to one input of the sensitive amplifier, and the other input of the sensitive amplifier is a reference level Vref; when the level of BL or BLB is higher than the reference level Vref, the sensitive amplifier outputs a high level, otherwise a low level. The sensitive amplifier is mainly used for detecting and amplifying small signals (voltage signals or current signals). In the SRAM, the sensitive amplifier can be used to detect and amplify the small swing signal on the bit line of the SRAM storage unit, thereby improving the speed and accuracy of data reading.

[0106] The logic unit array is composed of a plurality of operation logic units corresponding to the storage units one by one. In the logic unit array, the operation logic units corresponding to the storage units in the odd columns are all operation logic units ALU1, and the operation logic units corresponding to the storage units in the even columns are all operation logic units ALU2.

[0107] The timing control circuit is used to generate the clock signals required by each functional module. The input signal line is connected to the operation logic units ALU1 in each column, and is used to input corresponding input signals IN to each operation logic unit ALU1. The bit line pair includes 2N pairs of bit lines BL and BLB; each storage unit in each column is connected to the same group of bit lines BL and BLB.

[0108] The precharge circuit is used to perform a precharge operation on the bit lines BL and BLB connected to each column of storage units in the SRAM storage array. The precharge operation is to precharge each bit line to a high level during operation or data reading, and if the bit line voltage remains at a high level later, it represents an output of 1; if the bit line is discharged, it represents an output of 0.

[0109] The word line WL is used to input corresponding word line signals to each storage unit in the SRAM storage array. The word line driving module is used to control the opening or closing of the word line WL connected to each storage unit in the storage array. When it is necessary to select an arbitrary row of storage units and / or operation logic units to work, only the corresponding word line signal needs to be input.

[0110] The row decoding module is used to decode the input signal and control the word line driving module according to the decoding result. The column output circuit is connected to the bit lines BL and BLB connected to each column of storage units in the SRAM storage array through the sensitive amplifier SA; and then outputs the storage data of the storage units or the calculation result of the operation logic units in any column.

[0111] Specifically, two memory cells T1 and T2 located in adjacent columns of the same row in the SRAM memory array, together with their corresponding ALU1 and ALU2, constitute the memory operation circuit described above, and can realize the complete function of the basic circuit.

[0112] The difference between this embodiment and Embodiment 1 is that this embodiment, within a conventional large-scale 6T-SRAM memory circuit, utilizes memory cells in any adjacent rows to completely design the memory operation circuit described in Embodiment 1. Therefore, a series of functions, such as simple logic operations, complex Boolean logic operations, and TCAM addressing operations, as described in Embodiment 1, can be implemented on the SRAM memory circuit.

[0113] The following combination Figure 6 The circuit architecture of this embodiment will be described in detail: Figure 6 In the original 6T-SRAM memory array, the original array was 64×64. However, considering that this embodiment requires the use of two memory cells in adjacent columns as the basic circuit units, the final designed "computing unit array" is actually 64×32. This is because each adjacent odd-numbered and even-numbered column in the original memory cell array forms the same column in the new functional circuit array. In the new array, the basic circuit in any row and column includes two identical 6T SRAM cells, one arithmetic logic unit (ALU1), and one arithmetic logic unit (ALU2). Specifically, in this embodiment, all transistors in the 6T cell ALU1 and ALU2 circuit structures are of the same size.

[0114] like Figure 6 As shown, two identical 6T SRAM cells share one word line WL. <63> The 6T unit on the left is connected to bit line BL1. <31> and BLB1 <31> The storage nodes are designated Q1 and QB1; the 6T cell on the right is connected to bit line BL2. <31> and BLB2 <31> The storage nodes are designated Q2 and QB2. ALU1 is connected to an input signal line IN. <63> ALU1 is also connected to bit line BL1 <31> and BLB1 <31> ALU2 is connected to bit line BL2. <31> and BLB2 <31> .

[0115] Storage nodes Q1 and IN of the 6T unit on the left <63> The input of ALU1 is connected to the 6T memory cell Q2 on the right, and the output of ALU1 is connected to the bit line BL. <63> This constitutes IN <63> The logical operation of the three operands Q1, Q2, and bit line BL. <63> The reference voltage Vref serves as the two input signals to the sensitive amplifier SA.

[0116] It should be noted that for the calculation units of a row, their 6T units are connected to the same word line WL, and their ALU1s are connected to the same input IN. For the calculation units of a column, the 6T units and ALU1s on the left are connected to bit lines BL1, BLB1, and the 6T units and ALU2s on the right are connected to bit lines BL2, BLB2. Among them, the bit line BL2<31> and the reference voltage Vref serve as two input signals of the SA. When the voltage on the bit line is higher than the reference voltage, the SA outputs a high level, and vice versa.

[0117] For example, for all the calculation units of the 64th row, their 6T units are connected to the same word line WL<63>, and their ALU1s are connected to the same input IN<63>; for all the calculation units of the 32nd column, the 6T units and ALU1s on the left are connected to bit lines BL1<31>, BLB1<31>, and the 6T units and ALU2s on the right are connected to bit lines BL2<31>, BLB2<31>.

[0118] Based on the above circuit structure, the implementation of the storage function is still consistent with the original SRAM storage unit, that is, the data in the storage node corresponding to each storage unit is obtained by positioning the sub-line and the bit line. The processes of implementing four kinds of composite Boolean logic operation functions and implementing TCAM addressing operation are described in detail below.

[0119] I. Implementing four kinds of composite Boolean logic operation functions

[0120] The in-memory computing circuit provided in this embodiment contains a large number of (64x32 groups) unit structures of basic storage operation circuits as shown in Figure 1 By multiplexing the ground terminals and power terminals in the two embedded arithmetic logic units ALU1 and ALU2, AND / XNOR operation and XOR / OR operation can be respectively implemented in one cycle, and in combination with two SRAM 6T storage units, four kinds of composite Boolean logic operations can be implemented.

[0121] For ALU1, the operands are the external input IN and the storage node Q1 of the above 6T unit, and the output is Y1. When SD1=VSS, the AND operation can be implemented, and when SD1=VDD, the XNOR operation can be implemented. For ALU2, the operands are the output Y1 of ALU1 and the storage node Q2 of the below 6T unit, and the output is Y2. When SD2=VSS, the XOR operation can be implemented, and when SD2=VDD, the OR operation can be implemented.

[0122] Two embedded arithmetic logic units ALU1, ALU2 combined with two SRAM 6T storage units can realize the following four kinds of composite Boolean logic operations. That is: when SD1 = VSS, SD2 = VSS, the composite logic operation function of formula is realized. When SD1 = VSS, SD2 = VDD, the composite logic operation function of formula Y2 = (IN·Q1) + Q2 is realized. When SD1 = VDD, SD2 = VSS, the composite logic operation function of formula is realized. When SD1 = VDD, SD2 = VDD, the composite logic operation function of formula is realized.

[0123] The truth table of the four kinds of composite Boolean logic operations is shown in Tables 1-4 in Embodiment 1. In fact, the value of Y2 may have strong 1, weak 1, strong 0, and weak 0 output results according to different inputs, so it is necessary to reasonably set the reference voltage of SA to correctly read the calculation result. Based on the above, it can be known that in the in-memory computing circuit designed in the embodiment, complex Boolean logic operations can be realized in a single cycle by using two different storage units T1, T2 and two different operation logic units ALU1, ALU2,

[0124] II. Realize TCAM addressing operation

[0125] In the circuit structure provided in the embodiment, it can also constitute a ternary content addressable memory by reasonably configuring the signal lines. When the circuit is in the mode of SD1 = VSS, SD2 = VSS, the T1, T2, ALU1 and ALU2 overall circuit constitutes a complex logic operation module for realizing operation. Therefore, the TCAM can be formed by configuring the signal line IN. The data stored in the two SRAM 6T units are marked as Q1 and Q2, as shown in Figure 4 . The two-bit binary value composed of Q1 and Q2, when Q1 and Q2 are 1 and 0 respectively, indicates TACM state 1, and when the values of Q1 and Q2 are 1 and 1, it indicates TACM state 0, and when the values of Q1 and Q2 are 0 and 1, it indicates TACM state x. IN represents search data. The condition of Y2 = 1 indicates that the target data (IN) matches the search data (the two-bit binary value composed of Q1 and Q2), and the condition of Y2 = 0 indicates that the data does not match.

[0126] In the actual application process, the data search process is as follows: 1. Precharge the bit line to high level; 2. Connect various calculation values Y2 to the same bit line. If the bit line voltage remains at high level, it indicates matching, and if the bit line is discharged, it indicates mismatch; 3. Read out the final matching result through the readout amplifier.

[0127] Taking a 4*4 array as an example, if the external input is 1001, and the internal storage is 1001 or 100X, the Y2 output is 1, indicating a match. When the internal storage is 1010 or 1110, the Y2 output is 0, indicating a mismatch. Specifically, the operation logic of the data matching process is as shown in Figure 7

[0128] It should be noted that the 6T-SRAM storage unit, the 64*64 storage array, and the like are examples listed by the embodiment for the purpose of illustrating the scheme, and are not a limitation of the case. In other embodiments, based on the same technical idea, other types of storage units can be used to form other storage arrays of a larger scale to obtain the required "computing unit array".

[0129] Embodiment 3

[0130] The embodiment provides a storage and computing chip, which is an integrated circuit packaged by the SRAM in-memory computing circuit with the TCAM and logic operation function provided in Embodiment 2. The interface of the storage and computing chip at least includes: a power supply interface, a ground wire interface, a charging interface, a control signal interface, an input signal interface, a switching signal, a word line interface, and an output signal interface.

[0131] The power supply interface VDD is used to connect the power supply. The ground wire interface VSS is used to connect the ground. The charging interface PRE is used to input a control signal for adjusting the charging state of each bit line. The control signal interface SD is used to input a control signal for adjusting the running state of each operation logic unit. The input signal interface IN is used to input a corresponding input signal to each operation logic unit ALU1. The switching signal SW is used to input a switching signal to the circuit, and the switching signal is used to adjust the access state of the storage unit and the pre-budget logic unit on the bit line; and further to switch the circuit between the normal read-write and in-memory operation modes. The word line interface WL is used to input a corresponding word line signal to each storage unit, and the word line signal is used to adjust the access state of each storage unit on each bit line. The output signal interface Y is used to read the data stored in each storage unit or read the logic operation result of each operation logic unit.

[0132] Performance testing

[0133] In order to verify the effectiveness of the scheme provided by the embodiment, the embodiment also designs an integrated circuit in Embodiment 3 on the Cadence Virtuoso software by using the SMIC 55nm process, and comprehensively tests the performances of the circuit in the simulation system. The test content and results are as follows:

[0134] ​1. The 5000 times Monte Carlo simulation results of the circuit are verified by the TCAM operation. Since all the logical operation modes of the circuit are used in the TCAM operation process, the output results of the 5000 times Monte Carlo simulation have reference value for evaluating the performance and stability of the circuit.

[0135] In the embodiment, the target data IN inputted from outside is set as 1001 in a 4*4 array, and only when the internal storage data is 1001 or 100X, the output is 1, which indicates that the target data and the internal storage data match, otherwise, it indicates that the two do not match. Specifically, when the value of the internal storage data is X (i.e. the values of Q1 and Q2 are 01), it means that the value inputted from outside is matched, and the output value outputted by the sense amplifier SA is 1. When the data inputted from outside is 1, if the value of the internal storage data is 1 (i.e. the values of Q1 and Q2 are 10) or X (i.e. the values of Q1 and Q2 are 01), it means that the match, and the SA output is 1; if the value of the internal storage data is 0 (i.e. the values of Q1 and Q2 are 11), it means that the mismatch, and the SA output is 0. When the data inputted from outside is 0, if the value of the internal storage data is 0 (i.e. the values of Q1 and Q2 are 11) or X (i.e. the values of Q1 and Q2 are 01), it means that the match, and the SA output is 1; if the value of the internal storage data is 1 (i.e. the values of Q1 and Q2 are 10), it means that the mismatch, and the SA output is 0.

[0136] In the test process, when the internal storage data is 1001 and 100X, the Y2 outputs are respectively shown in Figure 8 and Figure 9 Based on the results of Figure 8 and Figure 9 , it can be known that the circuit provided in the embodiment outputs the correct results in the 5000 times operation process, the success rate is 100%, and no error occurs, which reflects the excellent logical operation ability and circuit stability of the circuit provided in the embodiment.

[0137] 2. In integrated circuit design, the performance range provided to designers is typically only applicable to digital circuits and is given in the form of "process corners." The idea is to limit the speed fluctuations of NMOS and PMOS transistors within a rectangle defined by four corners. These four corners are: fast NFET and fast PFET, slow NFET and slow PFET, fast NFET and slow PFET, and slow NFET and fast PFET. When extracting the device model corresponding to each corner from the wafer, the on-chip NMOS and PMOS test structures show different gate delays, and the actual selection of these corners is to obtain acceptable yield. Simulating the circuit under various process corners and extreme temperature conditions is the basis for determining the yield. Therefore, ss, tt, and ff refer to the lower left corner, the center corner, and the upper right corner, respectively.

[0138] To test the performance of the designed circuit under different process corners, this embodiment also uses different simulation schemes to obtain the average power consumption of four load logic operations under each process corner condition. The power consumption test results are as follows: Figure 10 As shown. Analysis Figure 10 The data shows that the power consumption fluctuation of the same logic operation under different process corners does not exceed 5.07%, indicating that the circuit has good adaptability to different process corners. Furthermore, among the SS, TT, and FF process corners, the SS process corner has the lowest average power consumption, while the FF process corner has the highest average power consumption; therefore, the circuit design provided in this case achieves the best performance in the SS process corner.

[0139] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A storage and operation circuit, characterized in that: The storage and arithmetic circuit includes two storage units T1 and T2 for storing data, and two arithmetic logic units ALU1 and ALU2; wherein ALU1 and ALU2 each include a control terminal, a first input terminal, a second input terminal, and an output terminal; The arithmetic logic unit ALU1 is an AND gate when VSS is connected to the control terminal, and an XNOR gate when VDD is connected to the control terminal; the arithmetic logic unit ALU2 is an XOR gate when VSS is connected to the control terminal, and an OR gate when VDD is connected to the control terminal. The first input terminal of the arithmetic logic unit ALU1 is connected to the storage node Q1 of the storage unit T1; the second input terminal of the arithmetic logic unit ALU1 is connected to an independent input signal line IN; the first input terminal of the arithmetic logic unit ALU2 is connected to the output terminal Y1 of the arithmetic logic unit ALU1; the second input terminal of the arithmetic logic unit ALU2 is connected to the storage node Q2 of the storage unit T2; the output terminal of the arithmetic logic unit ALU2 is Y2. The output terminal Y1 of ALU1 serves as the output terminal for the operation result when ALU1 performs "AND" or "XNOR" operation alone; the output terminal Y2 of ALU2 serves as the output terminal for the operation result when ALU2 performs "OR" or "XOR" operation alone, or as the output terminal for the operation result when TI, T2, ALU1, and ALU2 jointly perform four compound Boolean logic operations, or as the matching result output terminal when TI, T2, ALU1, and ALU2 jointly implement TCAM addressing operation.

2. The storage and operation circuit as described in claim 1, characterized in that, The ALU1 circuit includes two PMOS transistors PM3 and PM4, and two NMOS transistors NM5 and NM6. The source of PM3 is connected to the control signal SD1. The gate of PM3, the source of NM5, and the gate of NM5 are connected and connected to the input signal line IN. The gate of PM4, the gate of NM5, and the source of NM6 are connected and connected to the storage node Q1 of the storage cell T1. The drain of PM4, the drain of NM5, and the drain of NM6 are connected and serve as the output node Y1. The drain of PM3 is connected to the source of PM4.

3. The storage and operation circuit as described in claim 1, characterized in that, The circuit of ALU2 includes two PMOS transistors PM7 and PM8, and two NMOS transistors NM11 and NM12. The gate of PM7, the source of PM8, and the gate of NM11 are connected to the output node Y1 of ALU1. The gate of PM8, the source of PM7, and the gate of NM12 are connected to the storage node Q2 of storage cell T2. The drains of PM8, PM7, and NM11 are connected and serve as the output node Y2 of ALU2. The source of NM11 is connected to the drain of NM12. The source of NM12 is connected to the control signal SD2.

4. The storage and operation circuit as described in claim 1, characterized in that: The memory cells T1 and T2 employ a 6T memory cell containing six transistors. The 6T memory cell includes two PMOS transistors PM1 and PM2, and four NMOS transistors NM1, NM2, NM3, and NM4. PM1 and NM1 form one inverter structure, PM2 and NM2 form another inverter structure, and NM3 and NM4 serve as transmission transistors. The sources of PM1 and PM2 are both connected to VDD, and the sources of NM1 and NM2 are connected to VDD. The sources of all three nodes are connected to VSS; the drains of PM1, NM1, PM2, and NM2 are connected together as storage node Q1 and connected to the drain of NM3. The gate of NM3 is connected to the word line WL, and the source of NM3 is connected to the bit line BL; the drains of PM2, NM2, PM1, and NM1 are connected together as storage node QB1 and connected to the drain of NM4. The gate of NM4 is connected to the word line WL, and the source of NM4 is connected to the bit line BLB.

5. The storage and operation circuit as described in any one of claims 1-4, characterized in that, The operational functions of the storage and processing circuit are as follows: The storage unit T1 and the arithmetic logic unit ALU1 are used as the basic circuits to implement the "AND" operation and the "XNOR" operation in the storage arithmetic circuit, where IN and Q1 are two operands and Y1 is the output result; when SD1=VSS, ALU1 implements the AND operation; when SD1=VDD, ALU1 implements the XNOR operation. The storage unit T2 and the arithmetic logic unit ALU2 are used as the basic circuits to implement the "OR" and "XOR" operations in the storage arithmetic circuit, where Y1 and Q2 are two operands and Y2 is the output result; when SD2=VSS, ALU2 implements the OR operation; when SD1=VDD, ALU2 implements the XOR operation. The storage units T1 and T2, and the arithmetic logic units ALU1 and ALU2 together serve as the basic circuit for implementing four types of compound Boolean logic operations, where IN, Q1, and Q2 are three operands, and Y2 is the output result. The expressions for the four types of compound Boolean logic operations are as follows: 。 6. The storage and operation circuit according to any one of claims 1-4, characterized in that: The storage and processing circuit implements TCAM addressing operations in the following way: The control signals of the storage and operation circuit containing T1, T2, ALU1, and ALU2 are set to SD1=VSS and SD2=VSS. The two binary numbers consisting of node data Q1 and Q2 stored in the two storage units T1 and T2 can be used to represent three status bits. Among them, "10" represents TCAM status 1, "11" represents TCAM status 2, and "01" represents TCAM status x. The two binary numbers represented by Q1 and Q2 are used as target data, and IN represents search data. When the value of Y2 output is "1", it means that the target data matches the search data. When the value of Y2 output is "0", it means that the target data does not match the search data.

7. An SRAM in-memory computing circuit with TCAM and logic operation functions, characterized in that, It includes: SRAM memory array, which consists of 4N 2 Identical storage cells form a 2N×2N array; each storage cell contains two inverted storage nodes Q and QB; The logic unit array is composed of multiple arithmetic logic units that correspond one-to-one with the storage units; in the logic unit array, the arithmetic logic units corresponding to the storage units in the odd-numbered columns are all arithmetic logic units ALU1, and the arithmetic logic units corresponding to the storage units in the even-numbered columns are all arithmetic logic units ALU2. Timing control circuit, which is used to generate the clock signals required by each functional module; The input signal line is connected to the ALU1 of each column and is used to input the corresponding input signal IN to each ALU1. Bit line pairs, which include 2N pairs of bit lines BL and BLB; each memory cell in each column and the corresponding arithmetic logic unit ALU1 or ALU2 are connected to the same set of bit lines BL and BLB; A pre-charge circuit is used to pre-charge the bit lines BL and BLB connected to each column of memory cells in the SRAM memory array. Word lines WL are used to input corresponding word line signals to each memory cell in the SRAM memory array; Word line driver module, which is used to control the opening or closing of word lines WL connected to each memory cell in the memory array; The line decoding module is used to decode the input signal and control the word line driving module according to the decoding result; A switching circuit, used to switch the access states of the SRAM memory array and logic cell array on the bit lines to adjust different operating modes of the circuit; and The column output circuit, whose bit lines BL and BLB connected to each column of memory cells in the SRAM memory array are connected through a sensitive amplifier SA, can output the stored data of any column of memory cells or the calculation result of the arithmetic logic unit. In this SRAM storage array, two storage cells T1 and T2 located in adjacent columns of the same row, together with their corresponding ALU1 and ALU2, constitute the storage operation circuit as described in any one of claims 1-4, and can realize the complete function of the storage operation circuit.

8. The SRAM in-memory computing circuit with TCAM and logic operation functions as described in claim 7, characterized in that: The number of sensitive amplifiers is 4N. In each column storage unit, BL or BLB is one input of a sensitive amplifier, and the other input of the sensitive amplifier is the reference level Vref. When the level of BL or BLB is higher than the reference level Vref, the sensitive amplifier outputs a high level; otherwise, it outputs a low level.

9. A memory computing chip, characterized in that: It is an integrated circuit packaged with an SRAM in-memory computing circuit having TCAM and logic operation functions as described in claim 7 or 8.

10. The memory chip as described in claim 9, characterized in that, The interface of the in-memory computing chip includes at least: The power interface VDD is used to connect to the power supply. The grounding interface VSS is used for grounding. The charging interface PRE is used to input control signals that adjust the charging status of each line. The control signal interface SD is used to input control signals that adjust the operating state of each arithmetic logic unit. The input signal interface IN is used to input corresponding input signals to each arithmetic logic unit (ALU1). The switching signal SW is used to input a switching signal into the circuit, which is used to adjust the access state of the memory cell and the budget logic cell on the bit line; thereby enabling the circuit to switch between two working modes: normal read / write and in-memory operation. The word line interface (WL) is used to input corresponding word line signals to each memory cell, and these word line signals are used to adjust the access status of each memory cell on each bit line; and The output signal interface Y is used to read the data stored in each memory unit or the results of logical operations in each arithmetic logic unit.

Images