Semiconductor structure and method of manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises an electrode covering layer on a substrate, a contact structure comprising a first part and a second part, the first part being in contact with the electrode covering layer, and the bottom of the second part being in contact with the top of the first part, the width of the first part being greater than the width of the bottom of the second part, and the lower surface of the contact structure being not lower than the lower surface of the electrode covering layer. Compared with the contact structure with equal width, the electrode covering layer contact structure increases the contact area between the contact structure and the electrode covering layer, reduces the contact resistance and eliminates the voids in the contact structure. Moreover, the first part in contact with the electrode covering layer serves as a support during the chemical mechanical polishing process, avoiding the problems of load effect or depression of the contact structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In a typical dynamic random access memory (DRAM) fabrication process, the metal interconnect layer leads to the capacitor's top electrode capping layer through contact structures in vias. In typical fabrication processes, the vias extend deep into the electrode capping layer to reduce the contact resistance between the contact structures within the vias and the capacitor's top electrode capping layer. Because the vias differ from the adjacent pattern structure, excessively large vias can easily lead to loading effects or contact structure depressions during chemical polishing; conversely, excessively small vias can result in voids in the contact structure, causing a sharp increase in contact resistance. Summary of the Invention

[0003] Therefore, it is necessary to provide a new semiconductor structure and its fabrication method to address the problems in the existing technology, so as to increase the contact area and reduce the contact resistance.

[0004] To achieve the above objectives, in one aspect, the present invention provides a semiconductor structure comprising:

[0005] Electrode capping layer, located on the substrate;

[0006] The contact structure includes a first part and a second part, the first part being in contact with the electrode cover layer, and the bottom of the second part being in contact with the top of the first part; the width of the first part is greater than the width of the bottom of the second part.

[0007] The lower surface of the contact structure is not lower than the lower surface of the electrode cover layer.

[0008] In one embodiment, the longitudinal cross-sectional shape of the first portion is elliptical, and the first portion is located within the electrode cover layer.

[0009] In one embodiment, the semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer;

[0010] The first part includes a first conductive layer and a first barrier layer, wherein the first conductive layer is located within the electrode capping layer and the first barrier layer is located between the first conductive layer and the electrode capping layer.

[0011] The second part includes a second conductive layer and a second barrier layer. The second conductive layer is located inside the insulating layer and is integrally connected with the first conductive layer. The second barrier layer is located between the second conductive layer and the insulating layer and is integrally connected with the first barrier layer.

[0012] In one embodiment, the first portion is located on the upper surface of the electrode cover layer.

[0013] In one embodiment, the semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer;

[0014] The first part includes a first conductive layer and a first barrier layer. The first conductive layer is located inside the insulating layer, and the first barrier layer is located between the first conductive layer and the insulating layer and between the first conductive layer and the electrode cover layer.

[0015] The second part includes a second conductive layer and a second barrier layer, wherein the second conductive layer is located within the insulating layer; and the second barrier layer is located between the second conductive layer and the insulating layer and between the second conductive layer and the first conductive layer.

[0016] In one embodiment, the first portion is embedded within the electrode capping layer, and the upper surface of the first portion is higher than the upper surface of the electrode capping layer.

[0017] In one embodiment, the longitudinal cross-sectional shape of the first part is rectangular.

[0018] In one embodiment, the first part includes:

[0019] Multiple insertion sections, each located within the electrode cover layer;

[0020] The horizontal part is located on the upper surface of the electrode cover layer and is integrally connected with the insertion part.

[0021] In one embodiment, the semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer;

[0022] The first part includes a first conductive layer and a first barrier layer. The first conductive layer is located inside the insulating layer and the electrode covering layer, and the first barrier layer is located between the first conductive layer and the insulating layer and between the first conductive layer and the electrode covering layer.

[0023] The second part includes a second conductive layer and a second barrier layer, wherein the second conductive layer is located within the insulating layer; and the second barrier layer is located between the second conductive layer and the insulating layer and between the second conductive layer and the first conductive layer.

[0024] In one embodiment, the semiconductor structure further includes: a metal interconnect layer located on the contact structure and in contact with the top of the contact structure; the coefficient of thermal expansion of the first portion is not greater than the coefficient of thermal expansion of the second portion and is not greater than the coefficient of thermal expansion of the electrode capping layer, the coefficient of thermal expansion of the contact structure is not greater than the coefficient of thermal expansion of the electrode capping layer; and the resistivity of the first portion is not greater than the resistivity of the second portion.

[0025] A method for fabricating a semiconductor structure, comprising:

[0026] An electrode capping layer is formed on the substrate;

[0027] An insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer or within the insulating layer and the electrode cover layer. The contact structure includes a first part and a second part. The first part is in contact with the electrode cover layer, and the bottom of the second part is in contact with the top of the first part. The width of the first part is greater than the width of the bottom of the second part.

[0028] The lower surface of the contact structure is not lower than the lower surface of the electrode cover layer.

[0029] In one embodiment, forming an insulating layer on the electrode capping layer and forming a contact structure within the insulating layer and the electrode capping layer includes:

[0030] An insulating layer is formed on the upper surface of the electrode capping layer;

[0031] A top contact hole is formed within the insulating layer, exposing the electrode cover layer;

[0032] The electrode capping layer is etched based on the top contact hole to form a bottom contact hole within the electrode capping layer, and the width of the bottom contact hole is greater than the width of the bottom of the top contact hole;

[0033] A contact structure is formed inside the bottom contact hole and the top contact hole;

[0034] The bottom of the bottom contact hole is not lower than the lower surface of the electrode cover layer.

[0035] In one embodiment, the insulating layer includes a first insulating layer and a second insulating layer. The insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer, including:

[0036] A first insulating layer is formed on the upper surface of the electrode capping layer;

[0037] A first contact hole is formed within the first insulating layer, and the first contact hole exposes the upper surface of the electrode cover layer;

[0038] The first portion is formed within the first contact hole;

[0039] A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0040] A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0041] The second portion is formed within the second contact hole.

[0042] In one embodiment, the insulating layer includes a first insulating layer and a second insulating layer. The insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer and the electrode cover layer, including:

[0043] A first insulating layer is formed on the upper surface of the electrode capping layer;

[0044] A first contact hole is formed in the first insulating layer and the electrode covering layer, the first contact hole penetrating the first insulating layer and extending into the electrode covering layer;

[0045] The first portion is formed within the first contact hole;

[0046] A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0047] A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0048] The second portion is formed within the second contact hole.

[0049] In one embodiment, the insulating layer includes a first insulating layer and a second insulating layer. The insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer and the electrode cover layer, including:

[0050] A first insulating layer is formed on the upper surface of the electrode capping layer;

[0051] An initial contact hole is formed within the first insulating layer, and the initial contact hole exposes the electrode cover layer;

[0052] The electrode capping layer is etched to form multiple insertion holes within the electrode capping layer. The multiple insertion holes and the initial contact hole together constitute the first contact hole.

[0053] The first portion is formed within the first contact hole. The first portion includes a plurality of insertion portions and a horizontal portion, wherein the insertion portions are located within the insertion hole and the horizontal portion is located within the initial contact hole.

[0054] A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0055] A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0056] The second portion is formed within the second contact hole.

[0057] In one embodiment, after forming the contact structure, the method further includes:

[0058] A metal interconnect layer is formed on the upper surface of the insulating layer, and the metal interconnect layer is in contact with the top of the contact structure;

[0059] Wherein, the coefficient of thermal expansion of the first part is not greater than the coefficient of thermal expansion of the second part, and is not greater than the coefficient of thermal expansion of the electrode covering layer, and the coefficient of thermal expansion of the contact structure is not greater than the coefficient of thermal expansion of the electrode covering layer; the resistivity of the first part is not greater than the resistivity of the second part.

[0060] The semiconductor structure and its preparation method of the present invention have the following beneficial effects:

[0061] The semiconductor structure of the present invention includes an electrode capping layer located on a substrate; a contact structure including a first portion and a second portion, wherein the first portion contacts the electrode capping layer, and the bottom of the second portion contacts the top of the first portion; the width of the first portion is greater than the width of the bottom of the second portion; compared with directly forming a contact structure with equal top and bottom widths, this increases the contact area between the contact structure and the electrode capping layer, reducing contact resistance while eliminating voids in the contact structure. Furthermore, the first portion in contact with the electrode capping layer provides support during chemical mechanical polishing, avoiding problems such as load effects or contact structure depressions.

[0062] The method for fabricating a semiconductor structure according to the present invention includes forming an electrode capping layer on a substrate; forming an insulating layer on the electrode capping layer, and forming a contact structure within the insulating layer or within the insulating layer and the electrode capping layer. The contact structure includes a first portion and a second portion, wherein the first portion contacts the electrode capping layer, and the bottom of the second portion contacts the top of the first portion; the width of the first portion is greater than the width of the bottom of the second portion. Compared to directly forming a contact structure with equal top and bottom widths, this method increases the contact area between the contact structure and the electrode capping layer, reducing contact resistance while eliminating voids in the contact structure. Furthermore, the first portion in contact with the electrode capping layer provides support during chemical mechanical polishing, avoiding problems such as load effects or contact structure depressions. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment;

[0065] Figure 2 This is a schematic diagram of the process in the first embodiment where an insulating layer is formed on the electrode cover layer and a contact structure is formed between the insulating layer and the electrode cover layer.

[0066] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the bottom contact hole is formed in one embodiment corresponding to the first embodiment;

[0067] Figure 4 for Figure 3 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment;

[0068] Figure 5 This is a schematic diagram of the process of forming an insulating layer on the electrode cover layer and forming a contact structure within the insulating layer in the second embodiment;

[0069] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the first contact hole is formed in the second embodiment;

[0070] Figure 7 for Figure 6 A cross-sectional schematic diagram of the semiconductor structure after the second contact hole is formed in one corresponding embodiment;

[0071] Figure 8 for Figure 7 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment;

[0072] Figure 9 This is a schematic diagram of the process in the third embodiment where an insulating layer is formed on the electrode cover layer and a contact structure is formed between the insulating layer and the electrode cover layer;

[0073] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure after the first contact hole is formed in the third embodiment;

[0074] Figure 11 for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment;

[0075] Figure 12 This is a schematic diagram of the process in the fourth embodiment where an insulating layer is formed on the electrode cover layer and a contact structure is formed between the insulating layer and the electrode cover layer;

[0076] Figure 13 This is a cross-sectional schematic diagram of the semiconductor structure after the first contact hole is formed in the fourth embodiment;

[0077] Figure 14 for Figure 13 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment.

[0078] Explanation of reference numerals in the attached figures:

[0079] 102, Electrode capping layer; 104, Insulating layer; 106, Contact structure; 108, Metal interconnect layer; 202, Top contact hole; 204, Bottom contact hole; 206, First insulating layer; 208, First contact hole; 210, Second insulating layer; 212, Second contact hole; 302, First portion; 304, Second portion; 402, First barrier layer; 404, First conductive layer; 406, Second barrier layer; 408, Second conductive layer. Detailed Implementation

[0080] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0082] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0083] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0084] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0085] Embodiments of the invention are described herein with reference to a cross-sectional view illustrating an ideal embodiment (and intermediate structure) of the invention, thus allowing for the expectation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shape of the area shown herein, but rather include shape deviations due to, for example, manufacturing techniques.

[0086] See Figure 1 This is a schematic flowchart of a semiconductor structure fabrication method in one embodiment.

[0087] In one embodiment, a method for fabricating a semiconductor structure is provided, such as... Figure 1 As shown, the preparation method includes:

[0088] S102, forming an electrode capping layer on the substrate.

[0089] Specifically, an electrode capping layer is formed on a substrate, which covers the capacitor structure formed in the substrate. Exemplarily, the electrode capping layer may be made of boron-doped polycrystalline silicon and / or boron-doped germanium-silicon.

[0090] S104, an insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer or a contact structure is formed between the insulating layer and the electrode cover layer.

[0091] Specifically, using a deposition process well known to those skilled in the art, an insulating layer is formed on the electrode capping layer, and then a contact structure is formed in the insulating layer; or after forming an insulating layer on the electrode capping layer, a contact structure is formed in the insulating layer and the electrode capping layer; wherein, the contact structure includes a first part and a second part, the first part is in contact with the electrode capping layer, and the bottom of the second part is in contact with the top of the first part; the width of the first part is greater than the width of the bottom of the second part, and the lower surface of the contact structure is not lower than the lower surface of the electrode capping layer.

[0092] The method for fabricating a semiconductor structure according to the present invention includes forming an electrode capping layer on a substrate; forming an insulating layer on the electrode capping layer; and forming a contact structure within the insulating layer or within the insulating layer and the electrode capping layer. The contact structure includes a first portion and a second portion, wherein the first portion contacts the electrode capping layer, and the bottom of the second portion contacts the top of the first portion; the width of the first portion is greater than the width of the bottom of the second portion. Compared to directly forming a contact structure with equal top and bottom widths, this method increases the contact area between the contact structure and the electrode capping layer, reducing contact resistance while eliminating voids in the contact structure. Furthermore, the first portion in contact with the electrode capping layer provides support during chemical mechanical polishing, avoiding problems such as load effects or contact structure depressions.

[0093] See Figure 2 This is a schematic diagram illustrating the process of forming an insulating layer on the electrode capping layer and forming a contact structure between the insulating layer and the electrode capping layer in the first embodiment; see also Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the bottom contact hole is formed in one embodiment corresponding to the first embodiment; see also Figure 4 ,for Figure 3 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment.

[0094] like Figure 2 As shown, in one embodiment, the steps of forming an insulating layer on the electrode cover layer and forming a contact structure within the insulating layer and the electrode cover layer include S202-S208.

[0095] S202, an insulating layer is formed on the upper surface of the electrode covering layer.

[0096] Specifically, such as Figure 3 As shown, an insulating layer 104 is formed on the upper surface of the electrode cover layer 102. For example, the material of the insulating layer 104 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0097] S204, a top contact hole is formed within the insulating layer to expose the electrode cover layer.

[0098] Specifically, such as Figure 3 As shown, after removing the insulating layer 104 of the preset area of ​​the top contact hole 202 by a dry etching process, the top contact hole 202 located in the insulating layer 104 is obtained, and the top contact hole 202 exposes the upper surface of the electrode cover layer 102.

[0099] S206, based on the top contact hole etching of the electrode cover layer, to form the bottom contact hole within the electrode cover layer.

[0100] Specifically, such as Figure 3As shown, a wet etching process is performed to etch the electrode capping layer 102 exposed by the top contact hole 202, forming a bottom contact hole 204 within the electrode capping layer 102. The width W1 of the bottom contact hole 204 along the X-axis direction is (e.g., ...). Figure 3 The width W1 is exemplarily indicated, where the X-axis is perpendicular to the extension direction of the contact structure, and the Y-axis is parallel to the line connecting the first part and the second part. The width W1 is greater than the width W2 of the bottom of the top contact hole 202 along the X-axis direction, and the bottom of the bottom contact hole 204 is not lower than the lower surface of the electrode cover layer 102, i.e., the depth D1 of the bottom contact hole 204 is not greater than the thickness T1 of the electrode cover layer 102.

[0101] In one embodiment, the bottom contact hole 204 has a shape that includes at least one of elliptical, bowl-shaped, and circular.

[0102] S208, a contact structure is formed in the bottom contact hole and the top contact hole.

[0103] Specifically, such as Figure 4 As shown, a contact structure 106 is formed in the bottom contact hole 204 and the top contact hole 202 through a deposition process. By setting the width W1 of the bottom contact hole 204 along the X-axis direction to be greater than the width W2 of the bottom of the top contact hole 202 along the X-axis direction, the contact area of ​​the contact structure 106 in contact with the electrode cover layer 102 is greater than the area of ​​the contact structure 106 in the top contact hole 202 in direct contact with the electrode cover layer 102, thereby achieving the purpose of reducing contact resistance.

[0104] In one embodiment, the first part 302 includes a first conductive layer 404 and a first barrier layer 402, and the second part 304 includes a second conductive layer 408 and a second barrier layer 406. Specifically, firstly, a first barrier layer 402 is formed on the sidewall and bottom of the bottom contact hole 204, and a second barrier layer 406 is formed on the sidewall of the top contact hole 202; then, the bottom contact hole 204 is filled with the first conductive layer 404 and the top contact hole 202 is filled with the second conductive layer 408 through a film-forming process, wherein the first conductive layer 404 and the second conductive layer 408 may be made of the same material. The first barrier layer 402 covers the bottom and sidewalls of the bottom contact hole 204, and the first conductive layer 404 fills the bottom contact hole 204. That is, the first conductive layer 404 is located inside the electrode cover layer 102, and the first barrier layer 402 is located between the first conductive layer 404 and the electrode cover layer 102. The second barrier layer 406 covers the sidewalls of the top contact hole 202, and the second conductive layer 408 fills the top contact hole 202. That is, the second conductive layer 408 is located inside the insulating layer 104 and is integrally connected with the first conductive layer 404. The second barrier layer 406 is located between the second conductive layer 408 and the insulating layer 104 and is integrally connected with the first barrier layer 402.

[0105] See Figure 5 This is a schematic diagram illustrating the process of forming an insulating layer on the electrode cover layer and forming a contact structure within the insulating layer in the second embodiment; see also Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the first contact hole is formed in the second embodiment; see also Figure 7 ,for Figure 6 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second contact hole in one corresponding embodiment; see also Figure 8 ,for Figure 7 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment.

[0106] like Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, in one embodiment, the insulating layer 104 includes a first insulating layer 206 and a second insulating layer 210. The insulating layer 104 is formed on the electrode cover layer 102, and the contact structure 106 formed within the insulating layer 104 includes:

[0107] S302, a first insulating layer is formed on the upper surface of the electrode covering layer 102;

[0108] S304, a first contact hole is formed in the first insulating layer 206, and the first contact hole exposes the upper surface of the electrode cover layer;

[0109] S306, the first portion is formed within the first contact hole;

[0110] S308, a second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0111] S310, a second contact hole is formed in the second insulating layer, the second contact hole exposes the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0112] S312, the second portion is formed within the second contact hole.

[0113] Specifically, such as Figure 6 , Figure 7 , Figure 8As shown, in the first step, a first insulating layer 206 is formed on the upper surface of the electrode capping layer 102. Then, excess first insulating layer 206 is removed by photolithography etching, forming a first contact hole 208 in the first insulating layer 206 that exposes the upper surface of the electrode capping layer 102. That is, the depth D2 of the first contact hole 208 is equal to the thickness T2 of the first insulating layer 206. In the second step, a first conductive material layer is filled into the first contact hole 208 to obtain a first portion 302 constituting the contact structure 106. The upper surface of the first conductive material layer (first portion 302) is flush with the upper surface of the first insulating layer 206. In the third step, a second insulating layer 210 is formed on the first insulating layer 206, covering the upper surfaces of the first insulating layer 206 and the first conductive material layer. Then, a second contact hole 212 is formed in the second insulating layer 210 that exposes the first conductive material layer by photolithography etching. The width W3 of the bottom of the second contact hole 212 along the X-axis is smaller than the width W4 of the first conductive material layer (first portion 302) along the X-axis. Fourth step: Fill the second contact hole 212 with the second conductive material layer to obtain the second part 304 constituting the contact structure 106. At this time, the cross-sectional view of the semiconductor structure is as follows. Figure 8 As shown.

[0114] In one embodiment, the first insulating layer 206 and the second insulating layer 210 are made of the same material, for example, both are silicon oxide insulating layers 104.

[0115] In one embodiment, the first conductive material layer includes a first barrier layer 402 and a first conductive layer 404. The step of filling the first conductive material layer in the first contact hole 208 includes: First, forming the first barrier layer 402 on the sidewall and bottom of the first contact hole 208. In practical applications, the first barrier layer 402 can be made of different materials according to process requirements, such as titanium nitride barrier layer, titanium barrier layer, etc. Second, forming the first conductive layer 404 on the upper surface of the first barrier layer 402, wherein the upper surface of the first barrier layer 402 is flush with the upper surface of the first insulating layer 206, the first conductive layer 404 fills the first contact hole 208, and the first barrier layer 402 is located between the first conductive layer 404 and the upper surface of the electrode cover layer 102, and between the first conductive layer 404 and the first insulating layer 206. In practical applications, the first barrier layer 402 can be made of different materials according to process requirements, such as tungsten conductive layer, copper conductive layer, aluminum conductive layer, etc.

[0116] In one embodiment, the second conductive material layer includes a second barrier layer 406 and a second conductive layer 408. The step of filling the second contact hole 212 with the second conductive material layer includes: First, forming the second barrier layer 406 on the sidewall and bottom of the second contact hole 212. In practical applications, the second barrier layer 406 can be made of different materials according to process requirements, such as titanium nitride barrier layer, titanium barrier layer, etc. Second, forming the second conductive layer 408 at the location of the second contact hole 212 not filled by the second barrier layer 406. The second conductive layer 408 fills the second contact hole 212, that is, the second barrier layer 406 is located between the second conductive layer 408 and the upper surface of the first portion 302, and between the second conductive layer 408 and the second insulating layer 210. In practical applications, the second barrier layer 406 can be made of different materials according to process requirements, such as tungsten conductive layer, copper conductive layer, aluminum conductive layer, etc.

[0117] In one embodiment, the upper surface of the second conductive material layer is flush with the upper surface of the second insulating layer 210.

[0118] In one embodiment, the first barrier layer 402 and the second barrier layer 406 are made of the same material, and / or the first conductive layer 404 and the second conductive layer 408 are made of the same material.

[0119] See Figure 9 This is a schematic diagram illustrating the process of forming an insulating layer on the electrode capping layer and forming a contact structure between the insulating layer and the electrode capping layer in the third embodiment; see also Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the first contact hole is formed in the third embodiment; see also Figure 11 ,for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment.

[0120] like Figure 9 , Figure 10 , Figure 11 As shown, in one embodiment, the insulating layer 104 includes a first insulating layer 206 and a second insulating layer 210. The insulating layer 104 is formed on the electrode cover layer 102, and the contact structure 106 formed between the insulating layer 104 and the electrode cover layer 102 includes:

[0121] S402, a first insulating layer is formed on the upper surface of the electrode cover layer;

[0122] S404, a first contact hole is formed in the first insulating layer and the electrode covering layer, the first contact hole penetrates the first insulating layer and extends into the electrode covering layer;

[0123] S406, the first portion is formed within the first contact hole;

[0124] S408, a second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0125] S410, a second contact hole is formed in the second insulating layer, the second contact hole exposes the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0126] S412, the second portion is formed within the second contact hole.

[0127] Specifically, such as Figure 10 , Figure 11 As shown, in the first step, after forming a first insulating layer 206 on the upper surface of the electrode capping layer 102, a photoresist pattern with an opening is first formed on the first insulating layer 206. Then, the first insulating layer 206 exposed at the opening and at least a portion of the electrode capping layer 102 are removed sequentially by an etching process to obtain a first contact hole 208 located at the opening. At this time, the first contact hole 208 penetrates the first insulating layer 206 and extends into the electrode capping layer 102. The bottom of the first contact hole 208 is not lower than the lower surface of the electrode capping layer 102, that is, the depth D3 of the first contact hole 208 in the electrode capping layer 102 is not greater than the thickness T3 of the electrode capping layer 102. The cross-sectional view of the semiconductor structure at this time is shown in the figure. Figure 10 As shown. The etching process includes at least one of dry etching and wet etching. The second step involves filling the first contact hole 208 with a first conductive material layer to obtain the first portion 302 constituting the contact structure 106. The upper surface of the first conductive material layer is flush with the upper surface of the first insulating layer 206. The third step involves forming a second insulating layer 210 on the first insulating layer 206, covering the upper surfaces of the first insulating layer 206 and the first conductive material layer. Then, a second contact hole 212 exposing the first conductive material layer is formed in the second insulating layer 210 using photolithography etching. The width of the bottom of the second contact hole 212 along the X-axis is smaller than the width of the first conductive material layer along the X-axis. The fourth step involves filling the second contact hole 212 with a second conductive material layer to obtain the second portion 304 constituting the contact structure 106. The cross-sectional view of the semiconductor structure at this point is shown in the figure. Figure 11 As shown. Compared to the second embodiment, the first portion 302 of the contact structure 106 extends into the electrode cover layer 102, thereby increasing the contact area between the contact structure 106 and the electrode cover layer 102 by the portion in sidewall contact (e.g. Figure 11The sum of the areas of corresponding portions S1 and S2 reduces the contact resistance between the contact structure 106 and the electrode cover layer 102, and increases the adhesion between them. Compared to the second portion 304 directly contacting the electrode cover layer 102, the depth of the second contact hole 212 is reduced, avoiding voids in the contact structure 106 during subsequent filling.

[0128] See Figure 12 This is a schematic diagram illustrating the process of forming an insulating layer on the electrode capping layer and forming a contact structure between the insulating layer and the electrode capping layer in the fourth embodiment; see also Figure 13 This is a cross-sectional schematic diagram of the semiconductor structure after the first contact hole is formed in the fourth embodiment; see also Figure 14 ,for Figure 13 A cross-sectional schematic diagram of the semiconductor structure after the contact structure is formed in one corresponding embodiment.

[0129] like Figure 12 , Figure 13 , Figure 14 As shown, in one embodiment, the insulating layer 104 includes a first insulating layer 206 and a second insulating layer 210. Forming the insulating layer 104 on the electrode cover layer 102 and forming a contact structure 106 between the insulating layer 104 and the electrode cover layer 102 includes the following steps:

[0130] S502, a first insulating layer is formed on the upper surface of the electrode covering layer 102;

[0131] S504, an initial contact hole is formed in the first insulating layer, and the initial contact hole exposes the electrode cover layer;

[0132] S506, Etch the electrode cover layer to form multiple insertion holes within the electrode cover layer, the multiple insertion holes and the initial contact hole together constitute the first contact hole;

[0133] S508, the first part is formed in the first contact hole, the first part includes a plurality of insertion parts and a horizontal part, the insertion parts are located in the insertion hole, and the horizontal part is located in the initial contact hole;

[0134] S510, a second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion;

[0135] S512, a second contact hole is formed in the second insulating layer, the second contact hole exposes the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion;

[0136] S514, the second portion is formed within the second contact hole.

[0137] Specifically, such as Figure 13 , Figure 14 As shown, in the first step, after forming a first insulating layer 206 on the upper surface of the electrode capping layer 102, the excess first insulating layer 206 is first etched away using a first photolithography etching process, forming an initial contact hole in the first insulating layer 206 that exposes the upper surface of the electrode capping layer 102. The depth D4 of the initial contact hole is equal to the thickness T4 of the first insulating layer 206. Next, a portion of the electrode capping layer 102 exposed by the initial contact hole is etched away using a second photolithography etching process, resulting in multiple insertion holes located in the electrode capping layer 102. The depth D5 of the insertion holes is not greater than the thickness T5 of the electrode capping layer 102. The insertion holes and the initial contact holes together constitute the first contact hole 208. At this point, the cross-sectional view of the semiconductor structure is shown in the figure. Figure 13 As shown, the first photolithography etching process and the second photolithography etching process include at least one of wet etching and dry etching processes. In the second step, the first contact hole 208 is filled with a first conductive material layer to obtain a first portion 302 constituting the contact structure 106. The upper surface of the first conductive material layer is flush with the upper surface of the first insulating layer 206. The first portion 302 includes a horizontal portion formed by the first conductive material layer in the initial contact hole and an insertion portion formed by the first conductive material layer in the insertion hole. In the third step, after forming a second insulating layer 210 covering the upper surfaces of the first insulating layer 206 and the first conductive material layer, a second contact hole 212 exposing the first conductive material layer is formed in the second insulating layer 210 by a photolithography etching process. The width of the bottom of the second contact hole 212 along the X-axis direction is smaller than the width of the first conductive material layer along the X-axis direction (the width direction is the X-axis direction). This photolithography etching process includes at least one of wet etching and dry etching processes. Fourth step: Fill the second contact hole 212 with the second conductive material layer to obtain the second part 304 constituting the contact structure 106. At this time, the cross-sectional view of the semiconductor structure is as follows. Figure 14 As shown. Compared to the third embodiment, the portion of the contact structure 106 that extends into the electrode cover layer 102 is an insertion portion. While maintaining the same width of the first conductive material layer along the X-axis, this further increases the contact area between the contact structure 106 and the electrode cover layer 102 (e.g., ...). Figure 14 The sum of the areas of the corresponding parts of S3 and S4 makes the contact resistance between the contact structure 106 and the electrode cover layer 102 smaller. Under the condition that the contact resistance between the contact structure 106 and the electrode cover layer 102 remains unchanged, the width of the second contact hole 212 along the X-axis direction can be further reduced.

[0138] In one embodiment, the number of insertion holes formed in the electrode cover layer 102 is not less than 2.

[0139] like Figure 4 , Figure 8, Figure 11 , Figure 14 As shown, in one embodiment, after forming the contact structure 106, the method further includes:

[0140] A metal interconnect layer 108 is formed on the upper surface of the insulating layer 104. The metal interconnect layer 108 is in contact with the top of the contact structure 106. The capacitor array under the electrode cover layer 102 can be led out to the surface of the device through the metal interconnect layer 108, which makes it easy to connect the capacitor array to the required location.

[0141] Specifically, the coefficient of thermal expansion of the first portion 302 is not greater than that of the second portion 304, and not greater than that of the electrode capping layer 102; the coefficient of thermal expansion of the contact structure 106 is not greater than that of the electrode capping layer 102; and the resistivity of the first portion 302 is not greater than that of the second portion 304. During the operation of the semiconductor structure, the device temperature will rise. By setting the coefficient of thermal expansion of the first portion 302 to be no greater than that of the second portion 304, and not greater than that of the electrode capping layer 102, the abnormality of cracks appearing and extending in the electrode capping layer 102 due to thermal expansion mismatch is avoided. With the contact area remaining constant, by setting the resistivity of the first portion 302 to be no greater than that of the second portion 304, the contact resistance between the contact structure 106 and the electrode capping layer 102 is further reduced.

[0142] In one embodiment, the coefficient of thermal expansion of the second part 304 is greater than the coefficient of thermal expansion of the electrode cover layer 102, and the sum of the coefficients of thermal expansion of the first part 302 and the coefficients of thermal expansion of the second part 304 is not greater than the coefficient of thermal expansion of the electrode cover layer 102.

[0143] In one embodiment, the resistivity of the first portion 302 is less than the resistivity of the electrode capping layer 102; for example, the resistivity of the first conductive layer 404 is less than the resistivity of the electrode capping layer 102.

[0144] In one embodiment, the metal interconnect layer 108 includes a metal ion blocking layer and a metal connecting layer. The step of forming the metal interconnect layer 108 on the upper surface of the insulating layer 104 includes: forming a metal ion blocking layer on the upper surface of the insulating layer 104; and forming a metal connecting layer on the upper surface of the metal ion blocking layer and the contact structure 106, wherein the metal connecting layer is in contact with the top surface of the contact structure 106 (the top surface of the second portion 304). By providing the metal ion blocking layer, the purpose of preventing metal ions in the metal interconnect layer 108 from diffusing into the insulating layer 104 is achieved.

[0145] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0146] like Figure 4 , Figure 8 , Figure 11 , Figure 14 As shown, in one embodiment, the present invention also provides a semiconductor structure, comprising:

[0147] Electrode capping layer 102 is located on the substrate;

[0148] The contact structure 106 includes a first part 302 and a second part 304. The first part 302 is in contact with the electrode cover layer 102, and the bottom of the second part 304 is in contact with the top of the first part 302. The width of the first part 302 is greater than the width of the bottom of the second part 304.

[0149] The lower surface of the contact structure 106 is not lower than the lower surface of the electrode cover layer 102.

[0150] The semiconductor structure of the present invention includes an electrode capping layer 102 located on a substrate; a contact structure 106 including a first portion 302 and a second portion 304, wherein the first portion 302 contacts the electrode capping layer 102, and the bottom of the second portion 304 contacts the top of the first portion 302; the width of the first portion 302 is greater than the width of the bottom of the second portion 304; compared with directly forming a contact structure 106 with equal top and bottom widths, this increases the contact area between the contact structure 106 and the electrode capping layer 102, reducing contact resistance while eliminating voids in the contact structure 106. Furthermore, the first portion 302, which contacts the electrode capping layer 102, provides support during chemical mechanical polishing, avoiding load effects or the problem of contact structure 106 depression.

[0151] In one embodiment, the electrode capping layer 102 is made of boron-doped polycrystalline silicon and / or boron-doped germanium-silicon.

[0152] like Figure 4As shown, in one embodiment, the longitudinal cross-sectional shape of the first portion 302 is elliptical, and the first portion 302 is located within the electrode cover layer 102.

[0153] In other embodiments, the longitudinal cross-sectional shape of the first portion 302 includes a bowl shape and a circle.

[0154] like Figure 4 As shown, in one embodiment, the semiconductor structure further includes an insulating layer 104 located on the upper surface of the electrode capping layer 102.

[0155] The first part 302 includes a first conductive layer 404 and a first barrier layer 402. The first conductive layer 404 is located inside the electrode cover layer 102, and the first barrier layer 402 is located between the first conductive layer 404 and the electrode cover layer 102. The upper surfaces of the first barrier layer 402 and the first conductive layer 404 are flush with the upper surface of the electrode cover layer 102.

[0156] The second portion 304 includes a second conductive layer 408 and a second barrier layer 406. The second conductive layer 408 is located within the insulating layer 104 and is integrally connected to the first conductive layer 404. The second barrier layer 406 is located between the second conductive layer 408 and the insulating layer 104 and is integrally connected to the first barrier layer 402. The upper surfaces of both the second barrier layer 406 and the second conductive layer 408 are flush with the upper surface of the insulating layer 104. The width W1 of the first portion 302 along the X-axis is greater than the width W2 of the bottom of the second portion 304 along the X-axis, such that the contact area between the contact structure 106 and the electrode cover layer 102 is greater than the area of ​​direct contact between the second portion 304 and the electrode cover layer 102, thereby reducing the contact resistance.

[0157] In one embodiment, the material of the insulating layer 104 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0158] like Figure 8 As shown, in one embodiment, the first portion 302 is located on the upper surface of the electrode cover layer 102.

[0159] like Figure 8 As shown, in one embodiment, the semiconductor structure further includes an insulating layer 104 located on the upper surface of the electrode capping layer 102.

[0160] The first part 302 includes a first conductive layer 404 and a first barrier layer 402. The first conductive layer 404 is located inside the insulating layer 104, and the first barrier layer 402 is located between the first conductive layer 404 and the insulating layer 104 and between the first conductive layer 404 and the electrode cover layer 102.

[0161] The second part 304 includes a second conductive layer 408 and a second barrier layer 406. The second conductive layer 408 is located within the insulating layer 104. The second barrier layer 406 is located between the second conductive layer 408 and the insulating layer 104 and between the second conductive layer 408 and the first conductive layer 404.

[0162] Specifically, the insulating layer 104 includes a first insulating layer 206 and a second insulating layer 210 stacked sequentially from bottom to top on the upper surface of the electrode cover layer 102. The first part 302 includes a first conductive layer 404 and a first barrier layer 402. The first conductive layer 404 is located within the first insulating layer 206, and the first barrier layer 402 is located between the first conductive layer 404 and the first insulating layer 206, and between the first conductive layer 404 and the electrode cover layer 102. That is, the thickness of the first part 302 is equal to the thickness of the first insulating layer 206. The second part 304 includes a second conductive layer 408 and a second barrier layer 406. The second conductive layer 408 is located within the second insulating layer 210, and the second barrier layer 406 is located between the second conductive layer 408 and the second insulating layer 210, and between the second conductive layer 408 and the first conductive layer 404.

[0163] In one embodiment, the first insulating layer 206 and the second insulating layer 210 are made of the same material, for example, both are silicon oxide insulating layers 104.

[0164] In one embodiment, the first barrier layer 402 and the second barrier layer 406 are made of the same material, and / or the first conductive layer 404 and the second conductive layer 408 are made of the same material. For example, the first barrier layer 402 and the second barrier layer 406 include at least one of titanium nitride barrier layer and titanium barrier layer, and / or the first conductive layer 404 and the second conductive layer 408 include at least one of tungsten conductive layer, copper conductive layer and aluminum conductive layer.

[0165] In one embodiment, the upper surface of the second conductive material layer is flush with the upper surface of the second insulating layer 210.

[0166] In one embodiment, the first portion 302 is embedded within the electrode cover layer 102, and the upper surface of the first portion 302 is higher than the upper surface of the electrode cover layer 102.

[0167] In one embodiment, the semiconductor structure further includes an insulating layer 104 located on the upper surface of the electrode capping layer 102.

[0168] The first part 302 includes a first conductive layer 404 and a first barrier layer 402. The first conductive layer 404 is located inside the insulating layer 104 and the electrode cover layer 102. The first barrier layer 402 is located between the first conductive layer 404 and the insulating layer 104 and between the first conductive layer 404 and the electrode cover layer 102.

[0169] The second part 304 includes a second conductive layer 408 and a second barrier layer 406. The second conductive layer 408 is located within the insulating layer 104. The second barrier layer 406 is located between the second conductive layer 408 and the insulating layer 104 and between the second conductive layer 408 and the first conductive layer 404.

[0170] like Figure 11 As shown, in one embodiment, the longitudinal cross-sectional shape of the first part 302 is rectangular.

[0171] Specifically, the insulating layer 104 includes a first insulating layer 206 and a second insulating layer 210 sequentially stacked from bottom to top on the upper surface of the electrode cover layer 102. The first portion 302 includes a first conductive layer 404 and a first barrier layer 402. The first conductive layer 404 is located within the first insulating layer 206 and the electrode cover layer 102, and the first barrier layer 402 is located between the first conductive layer 404 and the first insulating layer 206, and between the first conductive layer 404 and the electrode cover layer 102. The second portion 304 includes a second conductive layer 408 and a second barrier layer 406. The second conductive layer 408 is located within the first insulating layer 206, and the second barrier layer 406 is located between the second conductive layer 408 and the first insulating layer 206, and between the second conductive layer 408 and the first conductive layer 404. (Compared to the second embodiment...) Figure 8 Compared to (as shown), the first portion 302 of the contact structure 106 extends into the electrode cover layer 102, increasing the contact area between the contact structure 106 and the electrode cover layer 102 by the portion in sidewall contact (e.g., Figure 11 The sum of the areas of corresponding portions S1 and S2 reduces the contact resistance between the contact structure 106 and the electrode cover layer 102, and increases the adhesion between them. Compared to the second portion 304 being directly attached to the electrode cover layer 102, the depth of the second contact hole 212 is reduced, avoiding voids in the contact structure 106 during subsequent filling.

[0172] like Figure 14 As shown, in one embodiment, the first portion 302 includes:

[0173] Multiple insertion portions are located within the electrode cover layer 102;

[0174] The horizontal portion is located on the upper surface of the electrode cover layer 102 and is integrally connected with the insertion portion.

[0175] Specifically, the first part 302 includes a plurality of insertion portions located within the electrode cover layer 102 and a horizontal portion located on the upper surface of the electrode cover layer 102, wherein the upper surface of the insertion portions is in contact with the lower surface of the horizontal portion, and the thickness D5 of the insertion portions is not greater than the thickness T5 of the electrode cover layer 102. Compared with the third embodiment, the portion of the contact structure 106 that extends into the electrode cover layer 102 is the insertion portion. While the width of the first part 302 along the X-axis remains unchanged, the contact area between the contact structure 106 and the electrode cover layer 102 is further increased (e.g., ...). Figure 14 The sum of the areas of the corresponding parts S3 and S4 in the middle makes the contact resistance between the contact structure 106 and the electrode cover layer 102 smaller. Under the condition that the contact resistance between the contact structure 106 and the electrode cover layer 102 remains unchanged, the width of the second part 304 along the X-axis direction can be further reduced.

[0176] In one embodiment, the number of insertion portions formed in the electrode cover layer 102 is not less than 2.

[0177] like Figure 4 , Figure 8 , Figure 11 , Figure 14 As shown, in one embodiment, the semiconductor structure further includes a metal interconnect layer 108, which is located on and in contact with the top of the contact structure 106. The metal interconnect layer 108 allows the capacitor array below the electrode capping layer 102 to be led out to the surface of the device, facilitating connection of the capacitor array to desired locations. The coefficient of thermal expansion of the first portion 302 is not greater than that of the second portion 304, and is not greater than that of the electrode capping layer 102. The coefficient of thermal expansion of the contact structure 106 is not greater than that of the electrode capping layer 102. The resistivity of the first portion 302 is not greater than that of the second portion 304. During operation, the device temperature rises. By setting the coefficient of thermal expansion of the first portion 302 to be no greater than that of the second portion 304, and no greater than that of the electrode capping layer 102, the abnormality of cracks appearing and extending in the electrode capping layer 102 due to thermal expansion mismatch is avoided. With the contact area remaining unchanged, by setting the resistivity of the first part 302 to be no greater than the resistivity of the second part 304, the contact resistance between the contact structure 106 and the electrode cover layer 102 is further reduced.

[0178] In one embodiment, the coefficient of thermal expansion of the second part 304 is greater than the coefficient of thermal expansion of the electrode cover layer 102, and the sum of the coefficients of thermal expansion of the first part 302 and the coefficients of thermal expansion of the second part 304 is not greater than the coefficient of thermal expansion of the electrode cover layer 102.

[0179] In one embodiment, the resistivity of the first portion 302 is less than the resistivity of the electrode capping layer 102; for example, the resistivity of the first conductive layer 404 is less than the resistivity of the electrode capping layer 102.

[0180] In one embodiment, the metal interconnect layer 108 includes:

[0181] A metal ion blocking layer is located on the upper surface of the insulating layer 104;

[0182] A metal connection layer is located on the upper surface of the metal ion blocking layer and the contact structure 106, and this metal connection layer is in contact with the top surface of the contact structure 106 (the top surface of the second part 304). By providing the metal ion blocking layer, the purpose of preventing metal ions in the metal interconnect layer 108 from diffusing into the insulating layer 104 is achieved.

[0183] In one embodiment, the semiconductor structure also includes a plurality of capacitor structures located beneath the electrode capping layer 102.

[0184] In one embodiment, the semiconductor structure is fabricated using any of the methods described above.

[0185] In one embodiment, the semiconductor structure includes a memory device.

[0186] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, include: Electrode capping layer, located on the substrate; The contact structure includes a first part and a second part, wherein the first part is in contact with the electrode cover layer, and the bottom of the second part is in contact with the top of the first part; The width of the first part is greater than the width of the bottom of the second part; Wherein, the lower surface of the contact structure is not lower than the lower surface of the electrode covering layer; The first portion is embedded within the electrode cover layer, and the upper surface of the first portion is higher than the upper surface of the electrode cover layer.

2. The semiconductor structure of claim 1, wherein, The first part has an elliptical longitudinal cross-sectional shape and is located within the electrode cover layer.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer; The first part includes a first conductive layer and a first barrier layer, wherein the first conductive layer is located within the electrode cover layer and the first barrier layer is located between the first conductive layer and the electrode cover layer; The second part includes a second conductive layer and a second barrier layer. The second conductive layer is located within the insulating layer and is integrally connected to the first conductive layer. The second barrier layer is located between the second conductive layer and the insulating layer and is integrally connected to the first barrier layer.

4. The semiconductor structure of claim 1, wherein, The first portion is located on the upper surface of the electrode cover layer.

5. The semiconductor structure of claim 4, wherein, The semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer; The first part includes a first conductive layer and a first barrier layer. The first conductive layer is located within the insulating layer, and the first barrier layer is located between the first conductive layer and the insulating layer and between the first conductive layer and the electrode cover layer. The second part includes a second conductive layer and a second barrier layer, wherein the second conductive layer is located within the insulating layer; and the second barrier layer is located between the second conductive layer and the insulating layer and between the second conductive layer and the first conductive layer.

6. The semiconductor structure of claim 1, wherein, The longitudinal cross-sectional shape of the first part is rectangular.

7. The semiconductor structure of claim 1, wherein, The first part includes: Multiple insertion portions, the insertion portions being located within the electrode cover layer; A horizontal portion, located on the upper surface of the electrode cover layer, and integrally connected with the insertion portion.

8. The semiconductor structure of any of claims 1-7, wherein, The semiconductor structure further includes an insulating layer located on the upper surface of the electrode capping layer; The first part includes a first conductive layer and a first barrier layer. The first conductive layer is located within the insulating layer and the electrode cover layer, and the first barrier layer is located between the first conductive layer and the insulating layer and between the first conductive layer and the electrode cover layer. The second part includes a second conductive layer and a second barrier layer, wherein the second conductive layer is located within the insulating layer; and the second barrier layer is located between the second conductive layer and the insulating layer and between the second conductive layer and the first conductive layer.

9. The semiconductor structure of claim 1, wherein, It also includes a metal interconnect layer, which is located on the contact structure and in contact with the top of the contact structure; the coefficient of thermal expansion of the first part is not greater than the coefficient of thermal expansion of the second part, and is not greater than the coefficient of thermal expansion of the electrode cover layer, and the coefficient of thermal expansion of the contact structure is not greater than the coefficient of thermal expansion of the electrode cover layer; the resistivity of the first part is not greater than the resistivity of the second part.

10. A method of fabricating a semiconductor structure, characterized by, include: An electrode capping layer is formed on the substrate; An insulating layer is formed on the electrode cover layer, and a contact structure is formed within the insulating layer or within the insulating layer and the electrode cover layer. The contact structure includes a first part and a second part, wherein the first part is in contact with the electrode cover layer, and the bottom of the second part is in contact with the top of the first part. The width of the first part is greater than the width of the bottom of the second part; Wherein, the lower surface of the contact structure is not lower than the lower surface of the electrode covering layer; The first portion is embedded within the electrode cover layer, and the upper surface of the first portion is higher than the upper surface of the electrode cover layer.

11. The method of claim 10, wherein, The step of forming an insulating layer on the electrode cover layer and forming a contact structure between the insulating layer and the electrode cover layer includes: An insulating layer is formed on the upper surface of the electrode cover layer; A top contact hole is formed within the insulating layer, the top contact hole exposing the electrode cover layer; The electrode cover layer is etched based on the top contact hole to form a bottom contact hole within the electrode cover layer, the width of the bottom contact hole being greater than the width of the bottom of the top contact hole; The contact structure is formed within the bottom contact hole and the top contact hole; Wherein, the bottom of the bottom contact hole is not lower than the lower surface of the electrode cover layer.

12. The method of claim 10, wherein, The insulating layer includes a first insulating layer and a second insulating layer, wherein forming the insulating layer on the electrode cover layer and forming a contact structure within the insulating layer includes: A first insulating layer is formed on the upper surface of the electrode cover layer; A first contact hole is formed within the first insulating layer, and the first contact hole exposes the upper surface of the electrode cover layer; The first portion is formed within the first contact hole; A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion; A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion; The second portion is formed within the second contact hole.

13. The preparation method according to claim 10, characterized in that, The insulating layer includes a first insulating layer and a second insulating layer. The step of forming the insulating layer on the electrode cover layer and forming a contact structure between the insulating layer and the electrode cover layer includes: A first insulating layer is formed on the upper surface of the electrode cover layer; A first contact hole is formed in the first insulating layer and the electrode covering layer, the first contact hole penetrating the first insulating layer and extending into the electrode covering layer; The first portion is formed within the first contact hole; A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion; A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion; The second portion is formed within the second contact hole.

14. The method of claim 10, wherein, The insulating layer includes a first insulating layer and a second insulating layer. The step of forming the insulating layer on the electrode cover layer and forming a contact structure between the insulating layer and the electrode cover layer includes: A first insulating layer is formed on the upper surface of the electrode cover layer; An initial contact hole is formed within the first insulating layer, the initial contact hole exposing the electrode cover layer; The electrode cover layer is etched to form a plurality of insertion holes within the electrode cover layer, and the plurality of insertion holes and the initial contact hole together constitute a first contact hole; The first portion is formed within the first contact hole, and the first portion includes a plurality of insertion portions and a horizontal portion, wherein the insertion portions are located within the insertion hole and the horizontal portion is located within the initial contact hole; A second insulating layer is formed on the upper surface of the first insulating layer, and the second insulating layer covers the first insulating layer and the first portion; A second contact hole is formed within the second insulating layer, the second contact hole exposing the first portion, and the width of the bottom of the second contact hole is smaller than the width of the first portion; The second portion is formed within the second contact hole.

15. The production method according to any one of claims 10 to 14, characterized by, After forming the contact structure, the method further includes: A metal interconnect layer is formed on the upper surface of the insulating layer, and the metal interconnect layer is in contact with the top of the contact structure; Wherein, the coefficient of thermal expansion of the first part is not greater than the coefficient of thermal expansion of the second part, and is not greater than the coefficient of thermal expansion of the electrode covering layer; the coefficient of thermal expansion of the contact structure is not greater than the coefficient of thermal expansion of the electrode covering layer; and the resistivity of the first part is not greater than the resistivity of the second part.

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