A driving unit applied to a special clock tree structure

Abstract

The present invention relates to the field of integrated circuit technology, and a driving unit applied to a special clock tree structure, including a large driving unit for driving a clock line of a high-level metal and transmitting a clock signal to a specific place; a small driving unit for receiving the clock signal conveyed by the large driving unit and converting it from a high-level metal to a low-level metal. The small driving unit of the present invention can resist electromigration and aging; a field effect transistor capacitor unit for isolating the sub-driving units that make up the large and small driving units can improve voltage drop and enhance dynamic performance. In the prior art, when performing Hspice simulation, accurate values cannot be given for the transition time under any conditions, resulting in distortion. However, the method provided by the present invention treats the entire large driving unit or small driving unit as an IP, so that accurate values under various conditions can be obtained by using static timing analysis, achieving full coverage, not affecting the chip yield, and at the same time reducing the number of driving units and the length of the clock tree.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and specifically to a driving unit applied to a special clock tree structure. Background Art

[0002] In current synchronous digital circuit designs, the clock tree is the benchmark for digital signal transmission. Its design quality determines the function and performance of integrated circuit chips. The clock signal will be transmitted to every corner of the integrated circuit chip. Due to its special function, the clock tree has the characteristics of the longest wiring, the widest distribution, the highest switching speed, and the largest power consumption. As the integrated circuit manufacturing process continues to improve, the number of transistors integrated per unit area is increasing. The latest A14 mobile processor has integrated 11.8 billion transistors. More and more functional modules are integrated into a single chip. The more transistors are integrated per unit area, the more leaf nodes of the clock are, and the longer the clock tree length becomes. The traditional tree-shaped clock structure can no longer meet the requirements of large chips, and a special clock structure has emerged.

[0003] Currently, the special clock structures applied in chip designs mainly include the grid-type clock structure and the fishbone-type clock structure. For example, a fishbone-type clock design disclosed by Zeng Yanfei in the article "Research and Implementation of Fishbone-Type Clock Structure" drives a high-level metal wire simultaneously by hundreds or thousands of driving units in the standard cell library. This high-level metal wire is very long and has a heavy load, and it can only be driven by the simultaneous action of multiple driving units. The purpose is to reduce the clock tree length. Shi Zhu disclosed a design method of a grid-type clock in the article "Design and Analysis of Clock Grid", which drives a clock grid simultaneously by 600 driving units in the standard cell library, aiming to obtain a clock tree with a smaller delay.

[0004] However, although the above-mentioned designs or methods can obtain a smaller clock tree length and improve the chip clock performance, they all use the drivers in the standard cell library to drive in parallel. In static timing analysis, the paths of this parallel structure cannot be analyzed. It is necessary to additionally use the Hspice tool for timing simulation, and then back-annotate the relevant information to the static timing analysis tool. The biggest drawback of this method is that it cannot achieve full coverage, which affects the yield of the chip. Summary of the Invention

[0005] The purpose of the present invention is to provide a driving unit applied to a special clock tree structure to solve the problems raised in the above background art.

[0006] To achieve the above purpose, a driving unit applied to a special clock tree structure includes:

[0007] A large driving unit (402) for driving the clock line of high-level metal and transmitting the clock signal to a specific location;

[0008] A small driving unit (404) for receiving the clock signal transmitted by the large driving unit (402) and converting it from high-level metal to low-level metal.

[0009] Preferably: The high-level metal refers to two layers of Top_Metal-1 and Top_Metal-2, and the low-level metal refers to Metal6.

[0010] Preferably: The input pin of the small driving unit (404) is on Top_Metal-3, and the output pin of the small driving unit (404) is on the low-level metal Metal6.

[0011] Preferably: The input pin of the large driving unit (402) is connected to Top_Metal-3, and the output pin of the large driving unit (402) is connected to Metal6.

[0012] Preferably: The small driving unit (404) is composed of 6 sub-driving units with the same driving ability evenly distributed, and the input ends and output ends of each sub-driving unit are respectively connected together.

[0013] Preferably: The input ends of each sub-driving unit are respectively connected in a grid manner through metal wire Metal2 and metal wire Metal3, and field effect transistor capacitor units are used for isolation placement between adjacent sub-driving units.

[0014] Preferably: The large driving unit (402) includes three-level units, and the large driving unit (402) is composed of 12 sub-driving units with the same driving ability in parallel.

[0015] Preferably: The pins of the large driving unit (402) are in an L shape, and the input ends of each sub-driving unit are respectively connected in a grid manner through metal wire Metal2 and metal wire Metal3, and field effect transistor capacitor units are used for isolation placement between adjacent sub-driving units.

[0016] Preferably: The output ends of the sub-driving units of each large driving unit (402) are respectively connected in a grid manner through metal wire Metal2 and metal wire Metal6, and field effect transistor capacitor units are used for isolation placement between adjacent sub-driving units.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] The small driving unit of the present invention can resist electromigration and aging; the field-effect transistor capacitor unit used to isolate the sub-driving units that make up the large and small driving units can improve voltage drop and enhance dynamic performance. In the prior art, when doing Hspice simulation, it is impossible to give accurate numerical values for the transition time under any conditions, resulting in distortion. However, the method provided by the present invention regards the entire large driving unit or small driving unit as an IP, so that accurate values under various conditions can be obtained by using static timing analysis, achieving full coverage, not affecting the chip yield, and at the same time reducing the number of driving units and the length of the clock tree. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of the driving unit in the embodiment of the present invention;

[0020] Figure 2 Schematic diagram of the internal input and output terminals of the large and small driving units in the embodiment of the present invention;

[0021] Figure 3 Schematic diagram of the internal input and output terminals of the large and small driving units in the embodiment of the present invention;

[0022] Figure 4 Schematic diagram of the full process of building and delivering the driving unit in the embodiment of the present invention;

[0023] Figure 5 Schematic diagram of the circuit of the driving unit in the embodiment of the present invention;

[0024] Figure 6 Schematic diagram of the connection of the large and small driving units and the high-low layer sequence relationship diagram in the embodiment of the present invention;

[0025] Figure 7 Schematic diagram of the application scenario of the driving unit in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0027] Embodiment

[0028] Refer to Figure 4 According to Figure 1Build the driving unit circuit as shown, then draw the layout of the driving unit circuit according to the requirements, extract the parasitic parameters of the driving unit through the layout, and then extract the timing information file and physical information file. Finally, deliver it in the form of an IP and apply it to the driving unit of the special clock tree structure. In addition, for the driving unit applied to the special clock tree structure in the present invention, there is no limit on the metal length of the driving clock line, and it is commonly 800um - 8000um.

[0029] Refer to Figure 7 This is the application scenario of the driving unit in the present invention, which is a special clock tree structure. The clock signal is input from the clock input point 401. The large driving unit 402 is used to drive the clock line of the top metal, and transmit the clock signal to a specific place. The driven top - layer clock metal line 403 has a length generally of 800um - 8000um. The small driving unit 404 will convert the top metal to the bottom metal and at the same time transmit the clock signal to the end node of the clock.

[0030] Among them, the small driving unit 404 includes a first - stage driving unit. After receiving the clock signal transmitted by the large driving unit 402, it converts it from the top metal to the bottom metal.

[0031] The top metal refers to the two layers of Top_Metal - 1 and Top_Metal - 2, and the bottom metal refers to Metal6. The specific arrangement is as Figure 6 shown in 505.

[0032] Refer to Figure 6 , the input pin of the small driving unit 404 is on Top_Metal - 3, and the output pin of the small driving unit 404 is on the bottom metal Metal6. In the figure, 503 is the Top_Metal - 3 connecting the input pin of the large driving unit, and 504 is the Metal6 connecting the output pin of the large driving unit.

[0033] The small driving unit 404 can also resist electromigration and aging, etc. Its driving ability is Xm, where m is an integer multiple of 6. It is composed of 6 sub-driving units with a driving ability of Xm / 6. The input terminals of each sub-driving unit are connected together, and the output terminals are connected together to form a parallel driving unit with a driving ability of Xm. The input terminal of each sub-driving unit is connected in a grid manner through Metal2 and Metal3, and at the same time, power and ground are used for shielding to avoid interference with each other. The output terminal of each sub-driving unit is connected in a grid manner through Metal2 and Metal3, and at the same time, power and ground are used for shielding to avoid interference with each other. The input terminal is on the left side of the small driving unit 404 and reaches Top_Metal-3 through a hole in Metal3. The output terminal is on the right side of the small driving unit and reaches Metal6 through a hole in Metal3.

[0034] Refer to Figure 3 , the small driving unit 404 is respectively provided with an input terminal 205 and an output terminal 206.

[0035] The 6 sub-driving units in the small driving unit 404 are evenly distributed. In order to reduce the influence between each other, they are placed separately, and the isolation unit is a field-effect transistor capacitor unit.

[0036] Refer to Figure 6 , the large driving unit 402 includes:

[0037] The first-stage unit has a small input pin capacitance, reducing the load of the previous-stage driving unit;

[0038] The second-stage unit is a pre-driving stage, used to drive the third-stage driving unit;

[0039] The third-stage unit is a driving stage, used to drive the high-level clock metal wires and quickly deliver the clock signal to a specific position.

[0040] The high-level clock metal wires are planned as Top_Metal-1 and Top_Metal-2.

[0041] The input pin of the large driving unit 402 is on Top_Metal-3, and the output pin of the large driving unit 402 is also on Top_Metal-3. As shown in the figure, 501 is the Top_Metal-3 connecting the input pin of the large driving unit 402, and 502 is the Top_Metal-3 connecting the output pin of the large driving unit 402.

[0042] The pins of the large driving unit 402 adopt an L shape, aiming to be conveniently connected regardless of whether the high-level clock metal wire is Top_Metal-1 or Top_Metal-2.

[0043] The large driving unit 402 has a driving capacity of Xn, where n is an integer multiple of 12. It is composed of 12 sub-driving units with a driving capacity of Xn / 12. The input ends of each sub-driving unit are connected together, and the output ends are connected together to form a parallel connection, resulting in a driving unit with a driving capacity of Xn. The input end of each sub-driving unit is connected in a grid pattern through Metal2 and Metal3, and at the same time, power and ground are used for shielding to avoid interference between them. The output end of each sub-driving unit is connected in a grid pattern through Metal2 and Metal6, and power and ground are used for shielding to eliminate interference between them. The input end is located on the left and upper sides of the large driving unit 402, and it reaches Top_Metal-3 through a hole drilled from Metal3. The output end is located on the right and lower sides of the large driving unit 402, and it reaches Top_Metal-3 through a hole drilled from Metal6. As Figure 2 shown, the large driving unit 402 is respectively provided with an input end 202 and an output end 203.

[0044] The large driving unit 402 contains three levels of units, which are placed according to regions from left to right. Shielding lines are added to isolate the connections between regions, and the sub-units within the regions are placed in a uniform manner. In order to reduce the influence between them, they are placed in an isolated manner. The isolation unit is a field-effect transistor capacitor unit. The isolation unit, the field-effect transistor capacitor unit, can also improve the voltage drop and enhance the dynamic performance.

[0045] The driving capacity of the large driving unit 402 is determined. The length of the clock line metal wire to be driven is set, and its RC parameters are extracted using a tool. Then, according to Figure 3 a SPICE simulation file is built for simulation. By adjusting different driving capacities, relevant data are obtained, and finally the driving capacity of the driver is determined.

[0046] The above content further elaborates on the present invention in combination with specific implementation manners. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope determined by the claims submitted for the present invention.

Claims

1. A driving unit applied to a special clock tree structure, characterized in that Including: A large driving unit (402) for driving the clock line of high-level metal and transmitting the clock signal to a specific location; A small driving unit (404) for receiving the clock signal transmitted by the large driving unit (402) and converting it from high-level metal to low-level metal. The high-level metal refers to the two layers of Top_Metal-1 and Top_Metal-2, and the low-level metal refers to Metal6. The input pin of the small driving unit (404) is on Top_Metal-3, and the output pin of the small driving unit (404) is on the low-level metal Metal6. The input pin of the large driving unit (402) is connected to Top_Metal-3, and the output pin of the large driving unit (402) is connected to Metal6. The small driving unit (404) is composed of 6 sub-driving units with the same driving ability evenly distributed, and the input ends and output ends of the sub-driving units of each small driving unit are respectively connected together. The input end of each sub-driving unit is respectively connected in a grid manner through metal wire Metal2 and metal wire Metal3, and adjacent sub-driving units are isolated and placed by field-effect transistor capacitor units. The large driving unit (402) includes three-level units, and the large driving unit (402) is composed of 12 sub-driving units with the same driving ability in parallel. The input ends of the sub-driving units of each large driving unit are respectively connected in a grid manner through metal wire Metal2 and metal wire Metal3, and adjacent sub-driving units are isolated and placed by field-effect transistor capacitor units. The output ends of the sub-driving units of each large driving unit (402) are respectively connected in a grid manner through metal wire Metal2 and metal wire Metal6, and adjacent sub-driving units are isolated and placed by field-effect transistor capacitor units.

2. The driving unit applied to the special clock tree structure according to claim 1, wherein: The pins of the large driving unit (402) adopt an L shape.

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