Discharge circuit, method, system, memory and storage system

Abstract

The present application discloses a discharge circuit, method, system, memory, and storage system. The discharge circuit includes: a first control branch including: a first control transistor connected in series between a node to be discharged and a negative power supply terminal; a second control branch including a second control transistor and a third control transistor connected in series between the node to be discharged and the negative power supply terminal; a controlled end of the second control transistor connected to a first node; the first node being the connection point between the negative power supply terminal and the first control transistor; a controlled end of the third control transistor connected to a first enable signal; a first discharge branch including a fourth control transistor connected in series between the node to be discharged and the negative power supply terminal; a controlled end of the fourth control transistor connected to a second node; and the second node being the connection point between the second control transistor and the third control transistor.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor integrated circuit technology, and in particular to a discharge circuit, method, and system. Background Art

[0002] Some components within an integrated circuit have outputs higher than the power supply voltage. When these components are not in use, their output nodes need to be discharged to ground. For example, in a memory chip, the output node of a high-voltage regulator that provides the programming voltage for the selected word line needs to be discharged to ground after it has completed a power supply. Another example is a charge pump coupled to a high-voltage regulator to provide a high voltage to the high-voltage regulator. After completing the power supply, its output node also needs to be discharged to ground. Currently, the discharge circuits used are complex and can only discharge the voltage, not reach the desired target value. Summary of the Invention

[0003] In view of this, the present application provides a discharge circuit, method, system, memory and storage system for a node to be discharged to solve the above problems.

[0004] To this end, the technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a discharge circuit, comprising: a first control branch, a second control branch, and a first discharge branch, wherein;

[0006] The first control branch includes: a first control transistor connected in series between the node to be discharged and the negative terminal of the power supply; the first control transistor is in a conductive state under the action of a first bias voltage, so that the voltage of the first node is a fixed first voltage; the first node is the end of the first control transistor connected to the negative terminal of the power supply;

[0007] The second control branch includes: a second control transistor and a third control transistor connected in series between the node to be discharged and the negative terminal of the power supply; a controlled terminal of the second control transistor is connected to the first node; the second control transistor is in an on state based on the effect of the first voltage before the voltage of the node to be discharged is discharged to a target voltage, and is turned off when the node to be discharged is discharged to the target voltage; the third control transistor is in an off state based on the first enable signal before the voltage of the node to be discharged is discharged to the target voltage;

[0008] The first discharge branch includes: a fourth control transistor connected in series between the node to be discharged and the negative end of the power supply; the controlled end of the fourth control transistor is connected to a second node; the second node is the connection point of the second control transistor and the third control transistor; the fourth control transistor is turned on when the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, to discharge the node to be discharged until the node to be discharged is discharged to the target voltage and is turned off.

[0009] In a second aspect, the present application also provides a discharge method.

[0010] A discharge circuit applied to a node to be discharged includes at least: a first control branch, a second control branch, and a first discharge branch connected in parallel between the node to be discharged and a negative terminal of a power supply; wherein the first control branch includes a first control transistor; the second control branch includes a second control transistor and a third control transistor connected in series; and the first discharge branch includes a fourth control transistor; and the method includes:

[0011] When the node to be discharged has not been discharged to the target voltage, the first control transistor is turned on based on the first bias voltage; when the first control transistor is turned on, the voltage of the first node is set to a fixed first voltage; under the action of the first voltage, the second control transistor is turned on; and the third control transistor is turned off based on the first enable signal;

[0012] When the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, the voltage of the second node is increased to a second voltage; under the action of the second voltage, the fourth control transistor is turned on, so that the first discharge branch forms a closed path, and the node to be discharged is discharged;

[0013] until the voltage of the to-be-discharged node is discharged to a target voltage, and the second control transistor is turned off under the action of the first voltage;

[0014] When the second control transistor is turned off, the voltage of the second node drops to a third voltage;

[0015] Under the action of the third voltage, the fourth control transistor is turned off, the first discharge branch is disconnected, and the discharge of the node to be discharged is stopped.

[0016] In a third aspect, an embodiment of the present application further provides a discharge system for a memory, comprising:

[0017] a first discharge circuit at a first output node of a charge pump of the memory; and a second discharge circuit at a second output node of a high-voltage regulator connected to an output end of the charge pump, wherein;

[0018] The first discharge circuit comprises: any of the discharge circuits described above; wherein the node to be discharged is the first output node; the first enable signal is the voltage of the fifth node included in the second discharge branch;

[0019] The second discharge circuit includes: a third control branch including a fifteenth control transistor and a second discharge branch including a sixteenth control transistor; wherein the fifteenth control transistor is connected in series between the second output node and a fifth node; the fifth node is a connection point for a controlled terminal of the sixteenth control transistor; and the controlled terminal of the fifteenth control transistor is connected to a second enable signal;

[0020] The sixteenth control transistor is connected in series between the second output node and the negative terminal of the power supply; the controlled terminal of the sixteenth control transistor is connected to the fifth node;

[0021] Wherein, under the action of the second enable signal, the second discharge circuit discharges the second output node before the first discharge circuit discharges the first output node.

[0022] In a fourth aspect, an embodiment of the present application provides a method for discharging a node to be discharged, using the aforementioned discharge system of the memory. The method includes:

[0023] Based on the access of the second enable signal, the second discharge circuit is turned on to discharge the second output node; the second enable signal is generated by a trigger included in the discharge system based on the received discharge trigger signal;

[0024] During the discharge process of the second discharge circuit, the first discharge circuit is turned off based on a first enable signal in a first state obtained from the second discharge circuit, so that the first discharge circuit does not discharge the first output node;

[0025] Until the voltage of the second output node is discharged to a first target voltage, the first enable signal changes from a first state to a second state, so that the first discharge circuit is turned on to discharge the first output node; until the voltage of the first output node is discharged to a second target value, a third enable signal that is inverted to the second enable signal is generated by the trigger; and the first discharge circuit and the second discharge circuit are turned off based on the third enable signal.

[0026] In a fifth aspect, an embodiment of the present application further provides a memory, comprising: a storage array for storing data;

[0027] and a peripheral circuit coupled to the memory array and configured to control the memory array; wherein,

[0028] The peripheral circuit includes: any one of the discharge circuits described above; or, includes the discharge system described above.

[0029] In a sixth aspect, an embodiment of the present application also provides a storage system comprising: one or more of the aforementioned memories; and a memory controller coupled to the one or more memories; the memory controller being configured to control various operations of the one or more memories.

[0030] The embodiment of the present application provides a discharge circuit, method, system, memory and storage system. The discharge circuit includes: a first control branch, a second control branch and a first discharge branch, wherein: the first control branch includes: a first control transistor connected in series between the node to be discharged and the negative end of the power supply; the first control transistor is in a conductive state under the action of a first bias voltage, so that the voltage of the first node is a fixed first voltage; the first node is the end of the first control transistor connected to the negative end of the power supply; the second control branch includes: a second control transistor and a third control transistor connected in series between the node to be discharged and the negative end of the power supply in sequence; the controlled end of the second control transistor is connected to the first node; the second control transistor is in a state of being ... In the on state, the node to be discharged is turned off when the node to be discharged is discharged to the target voltage; the third control transistor is in the off state based on the first enable signal before the voltage of the node to be discharged is discharged to the target voltage; the first discharge branch includes: a fourth control transistor connected in series between the node to be discharged and the negative end of the power supply; the controlled end of the fourth control transistor is connected to the second node; the second node is the connection point between the second control transistor and the third control transistor; the fourth control transistor is turned on when the first control transistor is on, the second control transistor is on, and the third control transistor is off, and discharges the node to be discharged until the node to be discharged is discharged to the target voltage and is turned off. The discharge circuit of the node to be discharged provided in the embodiment of the present application clamps the voltage of the node to be discharged by setting the first control transistor and the second control transistor, so that the first discharge branch can discharge the voltage of the node to be discharged to the required target voltage and then no longer discharges the node to be discharged. In addition, the discharge circuit provided in the embodiment of the present application is simple in design, uses a relatively small number of switch tubes, reduces logic control, reduces the mutual dependence between the components of the system in which it is located, and improves the robustness of the circuit itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic structural diagram of a discharge circuit for a node to be discharged provided in an embodiment of the present application;

[0032] Figure 2 A schematic flow chart of a method for discharging a node to be discharged provided in an embodiment of the present application;

[0033] Figure 3 A schematic structural diagram of a discharge system for a memory device provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0035] Figure 5 This is a working timing diagram of the discharge system provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of the working process of the discharge system provided in an embodiment of the present application;

[0037] Figure 7 A schematic flow chart of a method for discharging a memory provided in an embodiment of the present application;

[0038] Figure 8 is a schematic diagram of an exemplary memory including peripheral circuits;

[0039] Figure 9 for a side view of a cross section of an exemplary memory array including strings of memory cells according to some aspects of the present application;

[0040] Figure 10 A block diagram of an exemplary memory including a memory array and peripheral circuits

[0041] Figure 11 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0042] Figure 12 is a block diagram of an exemplary system having a memory in the related art;

[0043] Figure 13 is a schematic diagram of an exemplary memory card having a memory;

[0044] Figure 14 is a schematic diagram of an exemplary solid-state drive (SSD) having memory. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be arbitrarily combined with each other. The flowcharts in the accompanying drawings show a logical order, but in some cases, the steps shown or described can be performed in a different order than here.

[0046] The present application will be described in detail below with reference to the accompanying drawings.

[0047] See also Figure 1 , an embodiment of the present application provides a discharge circuit 100 for a node to be discharged, which includes: a first control branch ①, a second control branch ② and a first discharge branch ③, wherein;

[0048] The first control branch ① includes: a first control transistor M1 connected in series between the node to be discharged and the negative terminal of the power supply VSS; the first control transistor is in a conductive state under the action of a first bias voltage, so that the voltage of the first node is a fixed first voltage; the first node is the end of the first control transistor connected to the negative terminal of the power supply;

[0049] The second control branch ② includes: a second control transistor M2 and a third control transistor M3 connected in series between the node to be discharged and the negative terminal of the power supply; the controlled terminal of the second control transistor M2 is connected to the first node; the second control transistor is in an on state based on the effect of the first voltage before the voltage of the node to be discharged is discharged to the target voltage, and is turned off when the node to be discharged is discharged to the target voltage; the third control transistor is in an off state based on the first enable signal before the voltage of the node to be discharged is discharged to the target voltage;

[0050] The first discharge branch ③ includes: a fourth control transistor M4 connected in series between the node to be discharged and the negative end of the power supply; the controlled end of the fourth control transistor M4 is connected to a second node; the second node is the connection point between the second control transistor M2 and the third control transistor M3; the fourth control transistor is turned on when the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, to discharge the node to be discharged until the node to be discharged is discharged to the target voltage and is turned off.

[0051] It should be noted that the operating principle of the above-mentioned discharge circuit is as follows: when the node to be discharged has not been discharged to the target voltage, the first control transistor M1 is turned on under the action of the first bias voltage, and the voltage of the first node is a fixed first voltage; the second control transistor is turned on under the action of the first voltage and the voltage of the node to be discharged; the third control transistor is in the off state under the action of the first enable signal; when the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, the voltage of the second node is increased to a second voltage; under the action of the second voltage, the fourth control transistor is turned on, so that the first discharge branch forms a closed path to discharge the node to be discharged; until the voltage of the node to be discharged is discharged to the target voltage, the second control transistor is turned off under the action of the first voltage and the target voltage, so that the voltage of the second node drops to a third voltage, and the fourth control transistor is turned off under the action of the third voltage, so that the first discharge branch is disconnected, and the discharge of the node to be discharged is stopped, so that the voltage of the node to be discharged is maintained at the target voltage.

[0052] It should be noted that the discharge circuit of the node to be discharged described here includes a first control branch ①, a second control branch ② and a first discharge branch ③, wherein the first control transistor M1 in the first control branch ① and the second control transistor M2 in the second control branch ② clamp the voltage of the node to be discharged of the discharge circuit so as to maintain the voltage of the node to be discharged at the target voltage when the voltage of the node to be discharged is discharged to the target voltage.

[0053] Specifically, the first bias voltage vgsw2 signal is used to control the first control transistor M1 to be turned on, and one end of the first control transistor M1 (such as the source end, which is also the source end) is used to control the first control transistor M1 to be turned on. Figure 1 The voltage of the first node in the discharge circuit (i.e., the first control transistor M1) controls the conduction or shutoff of the second control transistor M2, thereby clamping the node to be discharged so that the voltage of the node to be discharged reaches the target voltage. In some embodiments, the first control transistor M1 may be an N-type MOS transistor; and the second control transistor M2 may be a P-type MOS transistor.

[0054] For example, when the first control transistor M1 is an N-type MOS transistor and the second control transistor M2 is a P-type MOS transistor, the source follower structure of the first control transistor M1 causes its source voltage to be a fixed first voltage vgsw2-vthn (the threshold voltage of the first control transistor M1). Under the action of the first voltage and the voltage of the node to be discharged, the second control transistor M2 is turned on, and when the fourth control transistor forms a closed path in the first discharge branch, the node to be discharged is discharged; when the voltage of the node to be discharged drops to a target voltage vgsw2-vthn+|vthp| (the threshold voltage of the second control transistor M2), the second control transistor M2 is turned off because its gate voltage is not less than its source terminal voltage, causing the fourth control transistor controlling the first discharge branch to be turned off, thereby disconnecting the first discharge branch and no longer discharging the node to be discharged.

[0055] Here, the voltage value of the first bias voltage vgsw2 is an available default value provided by a power supply system in a peripheral circuit included in the memory, and is used to control the turning on or off of related switches of the memory, for example, to control the turning on of the first control transistor M1.

[0056] The first enable signal can be a pre-set control logic signal or a signal related to the control signals of one or more discharge circuits in the discharge system formed by the discharge circuit. The source of the first enable signal is not limited here, as long as it can discharge or stop the node to be discharged. Here, before the first discharge branch discharges the node to be discharged to the target voltage, the first enable signal turns off the third control transistor M3. The first voltage is the voltage that can turn on the second control transistor M2; the second voltage is the voltage that can turn off the second control transistor M3. The second voltage is the voltage that can turn on the fourth control transistor M4; the third voltage is the voltage that can turn off the fourth control transistor M4.

[0057] In some embodiments, the node to be discharged may be an output terminal of a charge pump included in the memory for providing a programming voltage for a word line.

[0058] In some embodiments, the first control branch ① further includes: a fifth control transistor M5 connected in series between the first node and the negative terminal of the power supply; the fifth control transistor M5 is turned on or off under the action of the second enable signal, and is used to control the opening or closing of the first control branch ①.

[0059] It should be noted that the turning on or off of the first control branch ① mentioned herein may refer to turning on the fifth control transistor M5 under the action of a second enable signal before the first discharge branch ③ begins discharging the node to be discharged, thereby turning on the first control branch ① to prepare for the subsequent discharge of the node to be discharged by the first discharge circuit ③. Subsequently, when the voltage of the node to be discharged reaches the target voltage, the entire discharge process ends, and the fifth control transistor M5 is turned off under the action of the second enable signal, thereby turning off the first control branch ① to prevent leakage current in the first control branch ① from further reducing the voltage of the node to be discharged. Here, the second enable signal is a control signal different from the first enable signal.

[0060] In some embodiments, the first control branch ① further includes: a sixth control transistor M6 with a variable resistance connected in series between the fifth control transistor M5 and the negative terminal of the power supply; the sixth control transistor M6 is configured to be turned on under the action of the second bias voltage and to adjust the current flowing through the first control branch ① using different resistance values.

[0061] It should be noted that transistors with different aspect ratios result in different resistance values. Therefore, under the same voltage, the current flowing through transistors with different resistance values is different. Generally speaking, the larger the resistance, the smaller the current flowing through them, and the smaller the resistance, the larger the current flowing through them. Correspondingly, transistors with larger aspect ratios have smaller resistance values, while transistors with smaller aspect ratios have larger resistance values. Therefore, in some embodiments, the aspect ratio of the sixth control transistor can be changed to change the resistance of the sixth control transistor, thereby changing the current flowing through the sixth control transistor. Because the sixth control transistor is connected in series with the first control branch ①, the sixth control transistor is actually used to adjust the current flowing through the first control branch ①. Since the first control branch ① is a control branch, the current flowing through it must be relatively small to minimize the voltage discharge of the node to be discharged, that is, to minimize the impact on the discharge of the node to be discharged. Therefore, in some embodiments, by reducing the aspect ratio of the sixth control transistor, the resistance of the sixth control transistor is increased, thereby reducing the current flowing through the sixth control transistor, and thus reducing the current flowing through the first control branch ①.

[0062] In some embodiments, the first control branch further includes: a first protection transistor M7 connected in series between the first node and the fifth control transistor, for performing overvoltage protection on the fifth control transistor.

[0063] It should be noted that the voltage at the to-be-discharged node may be high, while the fifth control transistor used to control the opening or closing of the first control branch is a low-voltage transistor. To protect the fifth control transistor M5, a high-voltage-resistant first protection transistor M7 is connected in series with the first control branch near the first node. This reduces the voltage applied to the fifth control transistor M5 to a tolerable range, thereby protecting the fifth control transistor M5.

[0064] In some embodiments, the second control branch ② further includes: a seventh control transistor M8 connected in series between the third control transistor M3 and the negative terminal of the power supply; the seventh control transistor M8 is turned on or off under the action of the second enable signal, and is used to control the opening or closing of the second control branch.

[0065] It should be noted that the seventh control transistor M8 here has the same function as the fifth control transistor mentioned above, and is controlled by the same enable signal (both are controlled by the second enable signal). Please refer to the above description for understanding, and no further details will be given here.

[0066] In some embodiments, the second control branch ② further includes: an eighth control transistor M9 connected in series between the second control transistor M2 and the second node, and a ninth control transistor M10, a tenth control transistor M11, and an eleventh control transistor M12 forming a first current mirror with the eighth control transistor M9; wherein,

[0067] The ninth control transistor, the tenth control transistor and the eleventh control transistor are connected in series between a third node and the negative terminal of the power supply; the third node is a connection point between the second control transistor and the eighth control transistor;

[0068] The controlled end of the eighth control transistor and the controlled end of the ninth control transistor are connected together to a fourth node; the fourth node is the connection point between the ninth control transistor and the tenth control transistor;

[0069] The controlled terminal of the tenth control transistor is connected to the second enable signal, and is turned on or off under the action of the second enable signal, and is used to control the on or off of the first current mirror when the first current mirror is turned on;

[0070] The controlled end of the eleventh control transistor is connected to a second bias voltage. When the eleventh control transistor is turned on under the action of the second bias voltage and the first current mirror is turned on, the reference current of the first current mirror is adjusted by its own variable resistance; the reference circuit is the current flowing through the ninth control transistor, the tenth control transistor and the eleventh control transistor.

[0071] It should be noted that if Figure 1 As shown, control branch ④ and the second control branch ② form a first current mirror. The current flowing through the second control branch ② is affected by the current flowing through control branch ④, and the two are positively correlated. When the current flowing through control branch ④ is relatively small, the current flowing through the second control branch ② is also relatively small.

[0072] like Figure 1 As shown, the ninth control transistor, the tenth control transistor and the eleventh control transistor are connected in series to form a control branch ④, which forms a first current mirror with the second control branch ②. The control branch ④ can be used to control the current flowing through the second control branch ②.

[0073] Here, the eleventh control transistor M12 is similar in structure and functions to the aforementioned sixth control transistor M6, and can be understood with reference to the aforementioned description, and no further details are given. The tenth control transistor is similar in structure and functions to the aforementioned fifth and seventh control transistors, and can be understood with reference to the aforementioned description, and no further details are given.

[0074] Among them, the control branch ④ can control the current flowing through the second control branch ② only when it is turned on, and the control branch ④ has current only when the ninth control transistor, the tenth control transistor and the eleventh control transistor are all turned on. This current is the aforementioned reference current; the magnitude of the reference current is controlled by the eleventh control transistor.

[0075] In some embodiments, the second control branch ② further includes: a second protection transistor M13 connected in series between the second control transistor and the second node, for performing overvoltage protection on the third control transistor.

[0076] It should be noted that the second protection transistor M13 is similar in structure and function to the first protection transistor M7, and is used to provide overvoltage protection to the low-voltage third control transistor M3. Figure 1 As shown, the second protection transistor M13 performs overvoltage protection on the eighth control transistor M9 and the ninth control transistor M10.

[0077] In some embodiments, the second control branch further includes: a twelfth control transistor M14 connected in series between the second control transistor and the second protection transistor; the twelfth control transistor is turned on under the action of the fifth bias voltage and is used to: provide overvoltage protection for the second control transistor during the discharge process of the voltage node.

[0078] It should be noted that the voltage difference between the gate and drain terminals of the second control transistor M2 is subject to certain limits. Otherwise, the second control transistor M2 may burn out due to the excessive voltage difference between the gate and drain terminals. Therefore, to prevent the second control transistor M2 from being damaged, a transistor M14 is connected to the drain terminal of the second control transistor M2. Like M2, M14 is a P-type transistor and acts as a clamp, clamping the voltage at the drain terminal of the second control transistor M14 within a certain range to provide overvoltage protection for the second control transistor M2.

[0079] In some embodiments, the second control branch ② further includes: a thirteenth control transistor M15 connected in series between the second node and the negative end of the power supply, and the controlled end of the thirteenth control transistor is connected to the second node; the thirteenth control transistor and the fourth control transistor form a second current mirror for regulating the current flowing through the first discharge branch ③.

[0080] It should be noted that when the voltage at the second node drops to the second voltage, the thirteenth control transistor M15 is turned off; when the voltage at the second node rises to the first voltage, the thirteenth control transistor M15 is turned on. In other words, the thirteenth control transistor M15 regulates the current flowing through the first discharge branch ③ only when it is turned on. M15 can also be a transistor with a variable resistance.

[0081] In some embodiments, the first discharge branch ③ further includes: at least one third protection transistor M16 connected in series between the to-be-discharged node and the fourth control transistor, for performing overvoltage protection on the fourth control transistor.

[0082] It should be noted that the third protection transistor M16 has a similar structure and the same function as the first protection transistor M7 and the second protection transistor 13 , and is used to provide overvoltage protection for the low-voltage fourth control transistor M4 . Figure 1 , two third protection transistors M16 are included, and the controlled voltages of the two third protection transistors M16 are different.

[0083] In some embodiments, the discharge circuit 100 further includes: a fourteenth control transistor M17 connected in series between the second node and the negative terminal of the power supply; a third enable signal that is inverted with respect to the second enable signal is connected to the controlled terminal of the fourteenth control transistor; the fourteenth control transistor is turned on when the third enable signal is valid, so that the voltage of the second node drops to the low voltage of the negative terminal of the power supply, and the fourth control transistor is turned off, thereby ensuring that the first discharge branch is disconnected.

[0084] It should be noted that the third enable signal and the second enable signal are inverse signals of each other. It should be understood that when the component with the node to be discharged provides voltage to other components, the discharge circuit 100 should not discharge the node to be discharged. For example, when the component with the node to be discharged is a charge pump, it should not discharge the output node of the charge pump when it provides voltage to a coupled high-voltage regulator. To ensure the disconnection of the first discharge branch ③ of the discharge circuit 100, a fourteenth control transistor M17 is connected in series between the second node and the negative power supply terminal (ground), and its controlled terminal receives a third enable signal that is the inverse of the second enable signal. When the second enable signal is valid, the third enable signal is invalid; when the second enable signal is invalid, the third enable signal is valid. When the third enable signal is valid, the fourteenth control transistor M17 turns on, pulling the voltage of the second node down to the ground voltage vss, thereby turning off the fourth control transistor M4, disconnecting the first discharge branch and preventing discharge of the node to be discharged.

[0085] also, Figure 1 M1, M2, M14, M7, M13, and the two M16s can be high-voltage transistors used to protect the low-voltage transistors below. M1, M7, M13, and the two M16s can all be multi-finger N-type MOS transistors (including NPN junctions); M2 and M14 are multi-finger P-type MOS transistors (including PNP junctions). The number of single-finger N-type MOS transistors included in the third protection transistor M16 is greater than the number of single-finger N-type MOS transistors included in the first protection transistor M7 and / or the second protection transistor M13, making the discharge branch ② the main discharge branch. The multi-finger can be equivalent to multiple single-finger MOS transistors connected in parallel, where the single-finger MOS can refer to the NPN junction formed between each pair of source electrodes S and drain electrodes D, or the PNP junction formed between each pair of source electrodes S and drain electrodes D. Figure 1The remaining transistors except the above-mentioned transistors are all low-voltage transistors. It should be noted that in the memory, when the above-mentioned discharge circuit is the discharge circuit of the output node of the charge pump, since, before the output node (vpeh) of the charge pump is discharged, the output node (vpe) of the high-voltage regulator connected thereto is first discharged, therefore, in order to ensure that vpeh is discharged immediately after vpe is discharged to the first target voltage value, the first control branch, the second control branch, and the third control branch have entered the working state before the first discharge branch discharges the node to be discharged, that is: a small amount of current flows (leakage current) on the first control branch, the second control branch, and the third control branch, but it has little effect on the voltage of the node to be discharged. During the discharge process of the first discharge branch, the first control branch, the second control branch, and the third control branch are also always working, with a small amount of leakage current. In order not to have too much impact on the voltage of the node to be discharged, the current on the first control branch, the second control branch, and the third control branch is relatively small.

[0086] The discharge circuit of the node to be discharged provided in the embodiment of the present application, by providing a first control transistor and a second control transistor, clamps the voltage of the node to be discharged, so that the first discharge branch can discharge the voltage of the node to be discharged to the required target voltage and then no longer discharges the node to be discharged. In addition, the discharge circuit provided in the embodiment of the present application is simple in design and uses a relatively small number of switch tubes, which reduces logic control, reduces the mutual dependence between the components of the system in which it is located, and improves the robustness of the circuit itself. In addition, through the layout of the above-mentioned discharge circuit, the number of switches used is relatively small, which can save chip area.

[0087] like Figure 2 As shown, an embodiment of the present application further provides a method for discharging a node to be discharged, which is applied to a discharge circuit of the node to be discharged, and includes at least: a first control branch, a second control branch, and a first discharge branch connected in parallel between the node to be discharged and the negative end of the power supply; wherein the first control branch includes a first control transistor; the second control branch includes a second control transistor and a third control transistor connected in series; and the first discharge branch includes a fourth control transistor. The method may include:

[0088] S201: When the to-be-discharged node has not been discharged to the target voltage, turning on the first control transistor based on the first bias voltage;

[0089] S202: When the first control transistor is turned on, the voltage of the first node is set to a fixed first voltage; and under the action of the first voltage, the second control transistor is turned on;

[0090] S203: Turning off the third control transistor based on the input first enable signal;

[0091] S204: When the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, the voltage of the second node is increased to a second voltage;

[0092] S205: Under the action of the second voltage, turning on the fourth control transistor, so that the first discharge branch forms a closed path, and discharges the node to be discharged;

[0093] S206: until the voltage of the to-be-discharged node is discharged to a target voltage, the second control transistor is turned off under the action of the first voltage;

[0094] S207: When the second control transistor is turned off, causing the voltage of the second node to drop to a third voltage;

[0095] S208: Under the action of the third voltage, the fourth control transistor is turned off, the first discharge branch is disconnected, and the discharge of the node to be discharged is stopped.

[0096] It should be noted that the discharge method provided in the embodiment of the present application is based on the aforementioned discharge circuit. How each transistor works has been described in detail above and will not be repeated here.

[0097] like Figure 3 As shown, an embodiment of the present application further provides a discharge system 300 for a memory, comprising: a first discharge circuit 10 at a first output node of a charge pump of the memory; and a second discharge circuit 20 at a second output node of a high-voltage regulator connected to the first output node of the charge pump, wherein;

[0098] The first discharge circuit includes: the discharge circuit 100 described in any one of the above items; wherein the node to be discharged is the first output node; the first enable signal is the voltage of the fifth node included in the second discharge branch;

[0099] The second discharge circuit 20 includes at least: a third control branch ⑤ including a fifteenth control transistor M17 and a second discharge branch ⑥ including a sixteenth control transistor M18; wherein the fifteenth control transistor is connected in series between the second output node and a fifth node; the fifth node is a connection point for a controlled terminal of the sixteenth control transistor; and the controlled terminal of the fifteenth control transistor is connected to a second enable signal.

[0100] The sixteenth control transistor is connected in series between the second output node and the negative terminal of the power supply; the controlled terminal of the sixteenth control transistor is connected to the fifth node;

[0101] Wherein, under the action of the second enable signal, the second discharge circuit discharges the second output node before the first discharge circuit discharges the first output node.

[0102] It should be noted that the working principle of the above circuit is as follows: when the second enable signal is valid (in the first state of high level), the fifteenth control transistor included in the second discharge circuit is turned on, so that the voltage of the fifth node increases to the fourth voltage; under the action of the fourth voltage, the sixteenth control transistor is turned on, and the second discharge branch forms a closed path to discharge the second output node; under the action of the fourth voltage, the third control transistor is turned on, the second node drops to the third voltage, the fourth control transistor is turned off, the first discharge branch is disconnected, and the discharge to the first output node is not started; until the voltage of the second output node is discharged to the first target voltage, the voltage of the fifth node drops to the sixth voltage, the sixteenth control transistor is turned off, and the second discharge branch is disconnected; under the action of the sixth voltage, the third control transistor is turned off, so that the voltage of the second node rises to the second voltage, the first discharge branch forms a closed path, and discharges the first output node until the voltage of the first output node drops to the second target voltage.

[0103] Among them, Figure 3 In the figure, vpe represents the second output node of the output terminal of the high-voltage regulator; vpeh represents the first output node of the output terminal of the charge pump; vgsw1 represents the bias voltage applied to turn on M21; vgsw2 represents the aforementioned first bias voltage; vpe_disc represents the second enable signal; vmdis represents the first enable signal, also the voltage at the fifth node; vpe_disc_n represents the third enable signal; vpeh_en represents the second enable signal in the second state, also referred to as an invalid signal; vpe_dis represents the second enable signal in the first state, also referred to as a valid signal; and vndis represents the voltage at the second node. In some embodiments, the first state may be a high level state; and the second state may be a low level state.

[0104] It should be noted that, since the first discharge circuit 10 includes the discharge circuit 100 of the node to be discharged as described in any of the above descriptions, it has been described in detail above and will not be repeated here. For the second discharge circuit 20, it may also include: high-voltage transistors M19, M21, and M25 for protecting the low-voltage control transistor. In some embodiments, the second discharge circuit 20 may also include M22 that is similar in structure and has the same function as the sixth control transistor M6 in the first discharge circuit 10. In some embodiments, the second discharge circuit 20 may also include M23 that is similar in structure and has the same function as the thirteenth control transistor M15 in the first discharge circuit 10. In some embodiments, the second discharge circuit 20 also includes M24 that is similar in structure and has the same function as the fourteenth control transistor M17 in the first discharge circuit 10. Among them, the connection and position of the above-mentioned control transistors included in the second discharge circuit 20 can be as follows. Figure 3 shown.

[0105] It should also be noted that the charge pump included in the memory is connected in series with the high voltage regulator and coupled to the word line included in the memory, as shown in FIG. Figure 4 As shown in the figure. When a word line is selected for programming or other operations require a high voltage word line, the charge pump generates a high voltage vpeh. However, the generated high voltage vpeh cannot be applied directly to the word line. It must be stabilized by a high-voltage regulator to obtain a voltage vpe before being applied to the word line. After each high voltage is applied to the word line, the output of the charge pump and the output of the high-voltage regulator need to be discharged.

[0106] Combine Figure 3 The discharge system of the memory shown and Figure 5 shown Figure 3 For the control timing of each key control transistor, see Figure 6 The discharge process of the discharge system of the memory provided in the embodiment of the present application is as follows:

[0107] At the beginning of the discharge process, the RS trigger detects the rising edge of vpe_dis and generates a valid vpe_disc signal (vpe_disc is active high); the high-voltage regulator discharge circuit works to discharge vpe; the charge pump discharge circuit is turned on (enable), but does not start discharging, that is: the first control branch, the second control branch and the control branch ④ start working, but the first discharge branch is not turned on and does not discharge vpeh; it is detected whether vpe is discharged to the first target voltage; when the first target voltage is not reached, vpe continues to be discharged; when the first target voltage is reached, the clamping effect causes vpe to stop discharging after reaching the first target voltage, vmdis decreases, vndis increases, and vpeh starts to be discharged; the clamping effect causes vpeh to stop discharging after reaching the second target voltage; the falling edge of vpeh_en sets vpe_disc to a low level, which is an invalid second enable signal, all circuits no longer work (disable), and the entire discharge process ends.

[0108] Based on the same inventive concept, see Figure 7 As shown, an embodiment of the present application provides a method for discharging a node to be discharged, which is applied to the discharge system of the aforementioned memory. The method includes:

[0109] S701: Turn on a second discharge circuit to discharge a second output node based on a second enable signal; the second enable signal is generated by a trigger included in the discharge system based on a received external discharge trigger signal.

[0110] It should be noted that, for S701, the second enabling signal is Figure 3 The second enable signal is generated by a trigger included in the discharge system based on a received external discharge trigger signal and is in a first state. The second discharge circuit is a discharge circuit for the output node of the output terminal of the high-voltage regulator. Since the second discharge circuit needs to discharge the output terminal of the high-voltage regulator and its coupled load (including: coupled word line, control switch and connection point) simultaneously, if a discharge enable signal with a fixed effective duration is used, due to the large parasitic resistance and capacitance of the load coupled to the high-voltage regulator, it may result in that after the voltage at the output terminal of the high-voltage regulator is discharged to the first target voltage, the load has not yet discharged to the same voltage value, and the high-voltage regulator is recharged, which pulls up the voltage vpe at the output terminal of the high-voltage regulator again, thereby causing vpe to overshoot. To solve the above problem, the external discharge trigger signal is used only as a discharge trigger signal, rather than as an effective discharge signal, and an RS trigger is used to generate a second enable signal whose effective duration is not affected by the external trigger signal.

[0111] When the second enable signal is valid (in the first state), the fifteenth control transistor included in the second discharge circuit is turned on, so that the voltage of the fifth node increases to a fourth voltage; under the action of the fourth voltage, the sixteenth control transistor is turned on, and the second discharge branch forms a closed path to discharge the second output node until the voltage of the second output node reaches the first target voltage, so that the voltage of the fifth node drops to a sixth voltage, and the second discharge branch is disconnected, and no longer discharges the second output node.

[0112] S702 : During the discharge process of the second discharge circuit, shut down the first discharge circuit based on a first enable signal in a first state obtained from the second discharge circuit, so that the first discharge circuit does not discharge the first output node.

[0113] It should be noted that based on Figure 3 In the discharge system shown, during the discharge process of the second discharge circuit, only the first discharge branch of the first discharge circuit is disconnected, while the first control branch, the second control branch, and control branch (4) are substantially open, thereby controlling the closing of the first discharge branch and discharging the first output node. It should be noted that although the first control branch, the second control branch, and control branch (4) are open, their leakage current is small and has little impact on the voltage of the first output node. Therefore, there is no need to worry about the voltage of the first output node being excessively discharged during the discharge process of the second discharge circuit, thereby affecting normal circuit operation. Here, the first enable signal in the first state is also the first enable signal at a high level.

[0114] S703 : until the voltage of the second output node is discharged to a first target voltage, the first enable signal changes from a first state to a second state, so that the first discharge circuit is turned on to discharge the first output node.

[0115] Here, the discharge process of the first discharge circuit has been described in detail in the aforementioned discharge method, and will not be repeated here. The second state mentioned here may refer to the state where the first enable signal is at a low level.

[0116] S704: until the voltage of the first output node is discharged to a second target value, generate a third enable signal that is inverted to the second enable signal using the trigger; and turn off the first discharge circuit and the second discharge circuit based on the third enable signal.

[0117] It should be noted that the discharge method provided in the embodiment of the present application is based on the aforementioned discharge system. How each transistor works has been described in detail above and will not be repeated here.

[0118] The present application also provides a memory device, such as Figure 8 As shown, the memory 800 includes: a storage array 801 for storing data;

[0119] and a peripheral circuit 802 coupled to the memory array and configured to control the memory array;

[0120] in,

[0121] The peripheral circuit includes: the discharge circuit 100 described in any one of the above items.

[0122] It should be noted that the above description only describes the structure of the peripheral circuit 802 that is relevant to the embodiment of the present application. In fact, the memory array 801 can be a NAND flash memory array, wherein the memory cell 806 is provided in the form of an array of NAND memory cell strings 808, and each NAND memory cell string 808 extends vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 808 includes a plurality of memory cells 806 coupled in series and stacked vertically. Each memory cell 806 can maintain a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the storage area of the memory cell 806. Each memory cell 806 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0123] In some embodiments, each memory cell 806 is a single-level cell (SLC) having two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 806 is a multi-level cell (MLC) capable of storing a single bit of data in a plurality of four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC), or four bits per cell (also known as a quadruple-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of the three possible nominal storage values to the memory cell. A fourth nominal storage value can be used for the erased state.

[0124] like Figure 8As shown, each NAND memory cell string 808 may include a source select gate (SSG) 810 at its source terminal and a drain select gate (DSG) 812 at its drain terminal. The SSG 810 and DSG 812 may be configured to activate a selected NAND memory cell string 808 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory cell strings 808 in the same block 804 are coupled via the same source line (SL) 814 (e.g., a common SL). In other words, according to some embodiments, all NAND memory cell strings 808 in the same block 804 have an array common source (ACS). According to some embodiments, the DSG 812 of each NAND memory cell string 808 is coupled to a corresponding bit line 816, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory cell string 808 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 812) or a deselect voltage (e.g., 0 volts (V)) to a corresponding DSG 812 via one or more DSG lines 813 and / or applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 810) or a deselect voltage (e.g., 0 V) to a corresponding SSG 810 via one or more SSG lines 815.

[0125] like Figure 8As shown, a NAND memory cell string 808 can be organized into a plurality of blocks 804, each of which can have a common source line 814 (e.g., coupled to ground). In some embodiments, each block 804 is a basic unit of data for an erase operation, i.e., all memory cells 806 on the same block 804 are erased simultaneously. To erase the memory cells 806 in a selected block 804, the source lines 814 coupled to the selected block 804 and to unselected blocks 804 in the same plane as the selected block 804 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of a block. The memory cells 806 of adjacent NAND memory cell strings 808 can be coupled via word lines 818, which select which row of memory cells 806 receives read and program operations. In some embodiments, the memory cells 806 coupled to the same word line 818 are referred to as a (physical) page 820. A page 820 is a basic data unit for a programming operation or a read operation, and the size of a page 820 in bits may be related to the number of NAND memory cell strings 808 coupled by word lines 818 in a block 804. Each word line 818 may include a plurality of control gates (gate electrodes) at each memory cell 806 in a corresponding page 820 and a gate line coupling the control gates.

[0126] Figure 9 8 shows a side view of a cross section of an exemplary memory array 801 including NAND memory cell strings 808 according to some aspects of the present application. Figure 9 As shown in FIG, NAND memory cell string 808 can extend vertically through memory stack layer 902 above substrate 901. Substrate 901 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0127] The memory stack 902 may include alternating gate conductive layers 903 and gate-to-gate dielectric layers 904. The number of pairs of gate conductive layers 903 and gate-to-gate dielectric layers 904 in the memory stack 902 may determine the number of memory cells 806 in the memory array 801. The gate conductive layers 903 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 903 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 903 includes a doped polysilicon layer. Each gate conductive layer 903 may include a control gate surrounding a memory cell 806 and may extend laterally at the top of the memory stack 902 as a DSG line 813, at the bottom of the memory stack 902 as an SSG line 815, or between the DSG line 813 and the SSG line 815 as a word line 818.

[0128] like Figure 9 As shown in FIG, NAND memory cell string 808 includes a channel structure 905 extending vertically through memory stack layer 902. In some embodiments, channel structure 905 includes a channel hole filled with (one or more) semiconductor materials and (one or more) dielectric materials. In some embodiments, the semiconductor channel includes silicon, such as polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Channel structure 905 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0129] Return Reference Figure 8, the peripheral circuit 802 can be coupled to the memory array 801 through the bit line 816, the word line 818, the source line 814, the SSG line 815, and the DSG line 813. The peripheral circuit 802 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 801 by applying a voltage signal and / or a current signal to each target memory cell 806 and sensing a voltage signal and / or a current signal from each target memory cell 806 via the bit line 816, the word line 818, the source line 814, the SSG line 815, and the DSG line 813. The peripheral circuit 802 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 10 Some exemplary peripheral circuits are shown, and the peripheral circuit 802 includes a page buffer / sense amplifier 1004, a column decoder / bit line driver 1006, a row decoder / word line driver 1008, a voltage generator 1010, a control logic unit 1012, a register 1014, an interface 1016, and a data bus 1018. It should be understood that in some examples, the peripheral circuit 802 may also include Figure 10 Additional peripheral circuits not shown.

[0130] The page buffer / sense amplifier 1004 can be configured to read data from the memory array 801 and program (write) data to the memory array 801 based on control signals from the control logic unit 1012. In one example, the page buffer / sense amplifier 1004 can store a page of program data (write data) to be programmed into one page 820 of the memory array 801. In another example, the page buffer / sense amplifier 1004 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 806 coupled to the selected word line 818. In yet another example, the page buffer / sense amplifier 1004 can also sense a low-power signal from the bit line 816 representing a data bit stored in the memory cell 806 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 1006 can be configured to be controlled by the control logic unit 1012 and select one or more NAND memory cell strings 808 by applying a bit line voltage generated by the voltage generator 1010.

[0131] The row decoder / word line driver 1008 can be configured to be controlled by the control logic unit 1012 and select / deselect the block 804 of the memory array 801 and select / deselect the word line 818 of the block 804. The row decoder / word line driver 1008 can also be configured to drive the word line 818 using the word line voltage generated from the voltage generator 1010. In some embodiments, the row decoder / word line driver 1008 can also select / deselect and drive the SSG line 815 and the DSG line 813. As described in detail below, the row decoder / word line driver 1008 is configured to perform an erase operation on the memory cell 806 coupled to the selected word line(s) 818. The voltage generator 1010 can be configured to be controlled by the control logic unit 1012 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 801.

[0132] The control logic unit 1012 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 1014 can be coupled to the control logic unit 1012 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 1016 can be coupled to the control logic unit 1012 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1012, as well as buffer status information received from the control logic unit 1012 and relay it to the host. The interface 1016 can also be coupled to the column decoder / bitline driver 1006 via the data bus 1018 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 801. The charge pump and high-voltage regulator involved in the embodiments of the present application can be included in the voltage generator 1010.

[0133] The present application also provides a storage system. Figure 11 As shown, the storage system 1100 includes: one or more memories 800 as described above; and a memory controller 1101 coupled to the one or more memories; the memory controller is configured to control various operations of the one or more memories.

[0134] In some embodiments, the storage system is a solid state drive (SSD) or a memory card.

[0135] It should be noted that the storage system can be coupled with the host to form a data system, such as Figure 12The data system 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 12 As shown, the data system 1200 may include a host 1208 and a storage system 1100, wherein the storage system 1100 has one or more memories 800 and a memory controller 1101; the host 1208 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 1208 may be configured to send data to the memory 800 or receive data from the memory 800. Specifically, the memory 800 may be any memory disclosed in this application, such as phase change random access memory (PCRAM), three-dimensional NAND flash memory, and the like.

[0136] According to some embodiments, the memory controller 1101 is coupled to the memory 800 and the host 1208 and is configured to control the memory 800. The memory controller 1101 can manage data stored in the memory 800 and communicate with the host 1208. In some embodiments, the memory controller 1101 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 1101 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablet computers, and laptop computers, as well as enterprise storage arrays. The memory controller 1101 can be configured to control operations of the memory 800, such as read, erase, and program operations. The memory controller 1101 can also be configured to manage various functions related to data stored or to be stored in the memory 800, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1101 is also configured to process error correction codes (ECC) on data read from or written to the memory 800. The memory controller 1101 can also perform any other suitable functions, such as formatting the memory 800. The memory controller 1101 can communicate with an external device (e.g., the host 1208) according to a specific communication protocol.For example, the memory controller 1101 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. The memory controller 1101 and one or more memories 800 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 1100 can be implemented and packaged into different types of terminal electronic products. In such as. Figure 13 In one example shown, the memory controller 1101 and the single memory 800 may be integrated into a memory card 1302. Memory cards may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 12 1208 in the host) coupled to the memory card connector 1304. Figure 14 In another example shown, the memory controller 1101 and the plurality of memories 800 may be integrated into the SSD 1402. The SSD may also include a processor that connects the SSD to a host (e.g., Figure 12 The SSD connector 1404 is coupled to the host 1208 in the memory card. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 1101 can also be configured to control erase, read, and write operations of the memory 800. The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A discharge circuit, characterized in that: include: a first control branch, a second control branch and a first discharge branch, wherein; The first control branch includes: a first control transistor connected in series between the node to be discharged and the negative terminal of the power supply; the first control transistor is in a conductive state under the action of a first bias voltage, so that the voltage of the first node is a fixed first voltage; the first node is the end of the first control transistor connected to the negative terminal of the power supply; The second control branch includes: a second control transistor and a third control transistor connected in series between the node to be discharged and the negative terminal of the power supply; a controlled terminal of the second control transistor is connected to the first node; the second control transistor is in an on state based on the effect of the first voltage before the voltage of the node to be discharged is discharged to a target voltage, and is turned off when the node to be discharged is discharged to the target voltage; the third control transistor is in an off state based on the first enable signal before the voltage of the node to be discharged is discharged to the target voltage; The first discharge branch includes: a fourth control transistor connected in series between the node to be discharged and the negative end of the power supply; the controlled end of the fourth control transistor is connected to a second node; the second node is the connection point of the second control transistor and the third control transistor; the fourth control transistor is turned on when the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, to discharge the node to be discharged until the node to be discharged is discharged to the target voltage and is turned off.

2. The discharge circuit according to claim 1, characterized in that: The first control branch also includes: a fifth control transistor connected in series between the first node and the negative end of the power supply; the fifth control transistor is turned on or off under the action of the second enable signal, and is used to control the opening or closing of the first control branch.

3. The discharge circuit according to claim 2, characterized in that: The first control branch also includes: a sixth control transistor with a variable resistance connected in series between the fifth control transistor and the negative end of the power supply, which is used to be turned on under the action of the second bias voltage and adjust the current flowing through the first control branch using different resistance values.

4. The discharge circuit according to claim 2, characterized in that: The first control branch further includes: a first protection transistor connected in series between the first node and the fifth control transistor, for performing overvoltage protection on the fifth control transistor.

5. The discharge circuit according to claim 1, wherein: The second control branch also includes: a seventh control transistor connected in series between the third control transistor and the negative end of the power supply; the seventh control transistor is turned on or off under the action of the second enable signal, and is used to control the opening or closing of the second control branch.

6. The discharge circuit according to claim 1, characterized in that: The second control branch further includes: an eighth control transistor connected in series between the second control transistor and the second node, and a ninth control transistor, a tenth control transistor, and an eleventh control transistor forming a first current mirror with the eighth control transistor; wherein, The ninth control transistor, the tenth control transistor and the eleventh control transistor are connected in series between a third node and the negative terminal of the power supply; the third node is a connection point between the second control transistor and the eighth control transistor; The controlled end of the eighth control transistor and the controlled end of the ninth control transistor are connected together to a fourth node; the fourth node is the connection point between the ninth control transistor and the tenth control transistor; The controlled end of the tenth control transistor is connected to the second enable signal, and is turned on or off under the action of the second enable signal, so as to control the on or off of the first current mirror; The controlled end of the eleventh control transistor is connected to a second bias voltage. When the eleventh control transistor is turned on under the action of the second bias voltage and the first current mirror is turned on, the reference current of the first current mirror is adjusted by its own variable resistance; the reference current is the current flowing through the ninth control transistor, the tenth control transistor and the eleventh control transistor.

7. The discharge circuit according to claim 1, wherein: The second control branch further includes: a second protection transistor connected in series between the second control transistor and the second node, for performing overvoltage protection on the third control transistor.

8. The discharge circuit according to claim 7, characterized in that: The second control branch also includes: a twelfth control transistor connected in series between the second control transistor and the second protection transistor; the twelfth control transistor is turned on under the action of the fifth bias voltage and is used to: provide overvoltage protection for the second control transistor during the discharge process of the node to be discharged.

9. The discharge circuit according to claim 1, characterized in that: The second control branch also includes: a thirteenth control transistor connected in series between the second node and the negative end of the power supply, and the controlled end of the thirteenth control transistor is connected to the second node; the thirteenth control transistor and the fourth control transistor form a second current mirror for regulating the current flowing through the first discharge branch.

10. The discharge circuit according to claim 1, characterized in that: The first discharge branch further includes: at least one third protection transistor connected in series between the node to be discharged and the fourth control transistor, for performing overvoltage protection on the fourth control transistor.

11. The discharge circuit according to claim 1, wherein: The discharge circuit further includes: a fourteenth control transistor connected in series between the second node and the negative terminal of the power supply; a third enable signal that is inversely proportional to the second enable signal is connected to the controlled terminal of the fourteenth control transistor; the fourteenth control transistor is turned on when the third enable signal is valid, so that the voltage of the second node drops to the low voltage of the negative terminal of the power supply, turning off the fourth control transistor, and ensuring that the first discharge branch is disconnected.

12. The discharge circuit according to claim 1, wherein: The node to be discharged is a node at the output end of a charge pump included in the memory and used for providing a programming voltage for a word line.

13. A discharge method, characterized in that: A discharge circuit applied to a node to be discharged includes at least: a first control branch, a second control branch, and a first discharge branch connected in parallel between the node to be discharged and a negative terminal of a power supply; wherein the first control branch includes a first control transistor; the second control branch includes a second control transistor and a third control transistor connected in series; and the first discharge branch includes a fourth control transistor; and the method includes: When the node to be discharged has not been discharged to the target voltage, the first control transistor is turned on based on the first bias voltage; when the first control transistor is turned on, the voltage of the first node is set to a fixed first voltage; under the action of the first voltage, the second control transistor is turned on; and the third control transistor is turned off based on the first enable signal; When the first control transistor is turned on, the second control transistor is turned on, and the third control transistor is turned off, the voltage of the second node is increased to a second voltage; under the action of the second voltage, the fourth control transistor is turned on, so that the first discharge branch forms a closed path, and the node to be discharged is discharged; until the voltage of the to-be-discharged node is discharged to a target voltage, and the second control transistor is turned off under the action of the first voltage; When the second control transistor is turned off, the voltage of the second node drops to a third voltage; Under the action of the third voltage, the fourth control transistor is turned off, the first discharge branch is disconnected, and the discharge of the node to be discharged is stopped.

14. A discharge system for a memory, characterized in that: include: a first discharge circuit for a first output node of a charge pump of the memory; and a second discharge circuit connected to a second output node of a high voltage regulator at the first output node of the charge pump, wherein; The first discharge circuit comprises: the discharge circuit according to any one of claims 1 to 12; wherein the node to be discharged is the first output node; the first enable signal is the voltage of the fifth node included in the second discharge circuit; The second discharge circuit includes: a third control branch including a fifteenth control transistor and a second discharge branch including a sixteenth control transistor; wherein the fifteenth control transistor is connected in series between the second output node and a fifth node; the fifth node is a connection point for a controlled terminal of the sixteenth control transistor; and the controlled terminal of the fifteenth control transistor is connected to a second enable signal; The sixteenth control transistor is connected in series between the second output node and the negative terminal of the power supply; the controlled terminal of the sixteenth control transistor is connected to the fifth node; Wherein, under the action of the second enable signal, the second discharge circuit discharges the second output node before the first discharge circuit discharges the first output node.

15. A discharge method, characterized in that: The discharge system applied to the memory device according to claim 14, wherein the discharge method comprises: Based on the access of the second enable signal, the second discharge circuit is turned on to discharge the second output node; the second enable signal is generated by a trigger included in the discharge system based on the received discharge trigger signal; During the discharge process of the second discharge circuit, the first discharge circuit is turned off based on a first enable signal in a first state obtained from the second discharge circuit, so that the first discharge circuit does not discharge the first output node; Until the voltage of the second output node is discharged to a first target voltage, the first enable signal changes from a first state to a second state, so that the first discharge circuit is turned on to discharge the first output node; until the voltage of the first output node is discharged to a second target value, a third enable signal that is inverted to the second enable signal is generated by the trigger; and the first discharge circuit and the second discharge circuit are turned off based on the third enable signal.

16. A memory, characterized in that: including: a storage array for storing data; and a peripheral circuit coupled to the memory array and configured to control the memory array; wherein the peripheral circuit comprises: the discharge circuit according to any one of claims 1 to 12; or, the discharge system according to claim 14.

17. A storage system, characterized in that: include: One or more memories according to claim 14; and a memory controller coupled to the one or more memories; The memory controller is configured to control various operations of the one or more memories.

18. The storage system according to claim 17, wherein: The storage system is a solid state drive (SSD) or a memory card.

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