A broadband tunable receiver
By using embedded Barron's low noise amplifier, N-channel filtering structure and active low-pass filter in the receiver, a multi-stage active structure is formed, and the existing receivers are solved in the multi-mode and multi-frequency system broadband tunable. and the problem of high in-band gain, achieving the effects of high gain, low noise and low power consumption.
Patent Information
- Application Number
- CN202211229211.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-09
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2042-10-09
AI Technical Summary
It is difficult for existing receivers to achieve broadband tunable and high in-band gain in multi-mode and multi-frequency radio communication systems, and there are problems of power consumption and area occupancy.
Using embedded Barron's low noise amplifier as the input stage, combined with an N-channel filtering structure as the mixer, and using an active low-pass filter at the output stage, a multi-stage active structure is formed to achieve high gain and broadband signal. Tune.
It realizes high gain, low noise and high in-band gain of broadband tunable receivers, reduces power consumption and area occupation, and is suitable for multimode and multi-frequency radio communication systems.
Smart Images
Figure CN115603767B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of electronic information and relates to a receiver, in particular to a broadband tunable receiver. Background Art
[0002] With the development of wireless communication technology, the widespread coexistence of multi-band, multi-mode, and multi-standard wireless communication applications will become an important trend. Integrating systems that support multiple communication standards on a single chip at low cost has become a current research hotspot.
[0003] The receiver structure using an integrated N-channel filter can adjust the position of the passband by accurately controlling the center frequency through a digital switch, and has the advantages of good frequency selectivity, high linearity, and strong out-of-band suppression capability. Therefore, the receiver with an integrated N-channel filter has broad application prospects in multi-mode and multi-frequency radio communication systems. Summary of the invention
[0004] The purpose of the present invention is to provide a broadband tunable receiver. Compared with a traditional receiver, the receiver adopts a low-noise amplifier with an embedded balun as an input stage, which reduces the additional area required for an external balun and has lower noise; an N-channel filtering structure is adopted as a mixer, which does not consume additional power compared to a traditional mixer, is tunable, and can realize orthogonal modulation signals relying on a single clock source; an active low-pass filter structure is adopted at the output stage, which further enhances the out-of-band suppression capability of the receiver, and has a very high in-band gain compared to a traditional passive mixing receiver.
[0005] The objective of the present invention is achieved through the following technical solutions:
[0006] A broadband tunable receiver comprises a low noise amplifier unit, a mixer unit, and an active low pass filter unit, wherein:
[0007] The low noise amplifier unit is a low noise amplifier with single-ended input and differential output;
[0008] The mixer unit includes a mixer 1 and a mixer 2 with the same structure, each mixer is driven by a set of clock signals with the same frequency and a phase difference of 180°, and mixers of different channels are driven by clock signals with the same frequency and a phase difference of 90°;
[0009] The active low-pass filter unit comprises an active low-pass filter 1 and an active low-pass filter 2 having the same structure;
[0010] The positive output terminal of the low noise amplifier is connected to the positive input terminal of mixer 1 and the positive input terminal of mixer 2 at the same time, and the negative output terminal of the low noise amplifier is connected to the negative input terminal of mixer 1 and the negative input terminal of mixer 2 at the same time;
[0011] The negative output terminal of the mixer 1 is connected to the positive input terminal of the active low-pass filter 1, the positive output terminal of the mixer 1 is connected to the negative input terminal of the active low-pass filter 1, and the active low-pass filter 1 outputs fully differential signals I+ and I-;
[0012] The negative output terminal of the mixer 2 is connected to the positive input terminal of the active low-pass filter 2, and the positive output terminal of the mixer 2 is connected to the negative input terminal of the active low-pass filter 2. The active low-pass filter 2 outputs fully differential signals Q+ and Q-.
[0013] In the present invention, one input signal is converted into two fully differential signals through a low-noise amplifier unit, the two fully differential signals are simultaneously input into two mixer units, four low-pass filter channels are formed by connecting active low-pass filter units, and four output signals are formed through the active low-pass filter units, wherein the signal output by a single active low-pass filter unit is a differential signal, and the signals output by different active low-pass filter units are orthogonal to each other.
[0014] In the present invention, mixer 1 and mixer 2 are both implemented by switches composed of NMOS transistors.
[0015] In the present invention, mixer 1 and mixer 2 are both driven by a square wave clock signal, thereby realizing a frequency modulation function.
[0016] In the present invention, mixer 1 is driven by square wave clock signals with a frequency of flo and an initial phase of 0° and a frequency of flo and an initial phase of 180°, and mixer 2 is driven by square wave clock signals with a frequency of flo and an initial phase of 90° and a frequency of flo and an initial phase of 270°.
[0017] In the present invention, the active low-pass filter unit adopts a parallel resistor-capacitor network as a feedback form of a transimpedance amplifier to form a first-order filter, and a passive resistor-capacitor network forms a second-order filter. The active low-pass filter unit is a second-order filter.
[0018] Compared with the prior art, the present invention has the following advantages:
[0019] 1. Compared with the traditional radio frequency receiver, the present invention has the advantage of being tunable and can receive signals within a wide bandwidth.
[0020] 2. Compared with the traditional RF receiver, the present invention adopts a multi-stage active structure and has the characteristics of high gain.
[0021] 3. Compared with a receiver with an integrated Gilbert mixer unit, the present invention uses an N-channel mixer with higher linearity, simpler structure, smaller area, and no need to consume additional power.
[0022] 4. Compared with the low noise amplifier of the traditional RF receiver front end, the low noise amplifier of the present invention has the characteristics of an embedded balun, avoiding the extra area of the on-chip balun, and has the characteristics of high gain, large bandwidth and high linearity. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is the structural diagram of a broadband tunable receiver.
[0024] Figure 2 This is the circuit diagram of a low-noise amplifier unit with an embedded balun.
[0025] Figure 3 The circuit diagram of the mixer.
[0026] Figure 4 This is the circuit diagram of an active low-pass filter.
[0027] Figure 5 This is the circuit diagram of a transimpedance amplifier.
[0028] Figure 6 This is the transient simulation diagram of the receiver.
[0029] Figure 7 This is the receiver noise figure simulation diagram.
[0030] Figure 8 This is the receiver linearity simulation diagram. DETAILED DESCRIPTION
[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings, but is not limited thereto. Any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention should be included in the protection scope of the present invention.
[0032] The present invention provides a broadband tunable receiver, such as Figure 1 As shown, the receiver includes a low noise amplifier unit, a mixer unit, and an active low pass filter unit, wherein:
[0033] The low noise amplifier unit is a low noise amplifier with single-ended input and differential output;
[0034] The mixer unit includes a mixer 1 and a mixer 2 with the same structure, each mixer is driven by a set of clock signals with the same frequency and a phase difference of 180°, and mixers of different channels are driven by clock signals with the same frequency and a phase difference of 90°;
[0035] The active low-pass filter unit comprises an active low-pass filter 1 and an active low-pass filter 2 having the same structure;
[0036] The positive output terminal of the low noise amplifier is connected to the positive input terminal of mixer 1 and the positive input terminal of mixer 2 at the same time, and the negative output terminal of the low noise amplifier is connected to the negative input terminal of mixer 1 and the negative input terminal of mixer 2 at the same time;
[0037] The negative output terminal of the mixer 1 is connected to the positive input terminal of the active low-pass filter 1, and the positive output terminal of the mixer 1 is connected to the negative input terminal of the active low-pass filter 1;
[0038] The negative output terminal of the mixer 2 is connected to the positive input terminal of the active low-pass filter 2 , and the positive output terminal of the mixer 2 is connected to the negative input terminal of the active low-pass filter 2 .
[0039] like Figure 2 As shown, the low noise amplifier unit includes four NMOS transistors NM1 to NM4, two PMOS transistors PM1 and PM2, and three resistors R1, R2, and Rf, wherein:
[0040] The source of the NMOS transistor NM1, the source of the NMOS transistor NM2, and the source of the NMOS transistor NM3 are connected to VSS at the same time;
[0041] The source of the PMOS transistor PM1, the source of the PMOS transistor PM2, one end of the resistor R1, and one end of the resistor R2 are simultaneously connected to VDD;
[0042] The drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are simultaneously connected to the source of the NMOS transistor NM4;
[0043] The drain of the NMOS transistor NM2 and the drain of the PMOS transistor PM2 are simultaneously connected to the gate of the transistor NM3;
[0044] The gate of the NMOS transistor NM1, the gate of the PMOS transistor PM1, the gate of the NMOS transistor NM2, and the gate of the PMOS transistor PM2 are connected to each other and used as a low noise amplifier input terminal VIN;
[0045] The drain of the NMOS transistor NM3 is connected to the other end of the resistor R1 and serves as the positive output terminal VO+ of the low noise amplifier;
[0046] The drain of the NMOS transistor NM4 is connected to the other end of the resistor R2 and serves as the negative output terminal VO- of the low noise amplifier;
[0047] The gate of the NMOS transistor NM4 is connected to a bias voltage VB;
[0048] One end of the resistor Rf is connected to the low noise amplifier input terminal VIN, and the other end is connected to the gate of the NMOS transistor NM3.
[0049] like Figure 3 As shown, the mixer 1 and the mixer 2 are both composed of four NMOS transistors NM5 to NM8, wherein:
[0050] The source of the NMOS transistor NM5 is connected to the source of the NMOS transistor NM7 and serves as the positive input terminal RF+ of the mixer;
[0051] The source of the NMOS transistor NM6 is connected to the source of the NMOS transistor NM8 and serves as the negative input terminal RF- of the mixer;
[0052] The drain of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM8 and serves as the positive output terminal VO+ of the mixer;
[0053] The drain of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7 and serves as the negative output terminal VO- of the mixer;
[0054] The gates of the NMOS transistor NM5 and the NMOS transistor NM8 are connected to the digital clock CLK1;
[0055] The gates of the NMOS transistor NM6 and the NMOS transistor NM7 are connected to the digital clock CLK2 .
[0056] like Figure 4 As shown, the active low-pass filter 1 and the active low-pass filter 2 are both composed of four resistors R3-R6, four capacitors C1-C3, CL and a transimpedance amplifier TIA, wherein:
[0057] One end of the capacitor CL, one end of the capacitor C2, and one end of the resistor R4 are connected to the positive input end of the transimpedance amplifier TIA as the positive input end VI+ of the active low-pass filter;
[0058] The other end of the capacitor CL, one end of the capacitor C1, and one end of the resistor R3 are connected to the negative input end of the transimpedance amplifier TIA as the negative input end VI- of the active low-pass filter;
[0059] The other end of the capacitor C1, the other end of the resistor R3 and the negative output end of the transimpedance amplifier TIA are connected to one end of the resistor R6;
[0060] The other end of the capacitor C2, the other end of the resistor R4 and the positive output end of the transimpedance amplifier TIA are connected to one end of the resistor R5;
[0061] The other end of the resistor R5 is connected to one end of the capacitor C3 as a negative output terminal VO- of the active low-pass filter;
[0062] The other end of the resistor R6 is connected to the other end of the capacitor C3 to serve as the positive output terminal VO+ of the active low-pass filter.
[0063] like Figure 5 As shown, the transimpedance amplifier includes two NMOS transistors NM9 and NM10, two PMOS transistors PM3 and PM4, two resistors R7 and R8, and an operational amplifier with dual-input and dual-output terminals, wherein:
[0064] The source of the NMOS transistor NM9 and the source of the NMOS transistor NM10 are connected to VSS;
[0065] The source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are connected to VDD;
[0066] The gate of the NMOS transistor NM9 is connected to the gate of the PMOS transistor PM3 to serve as the positive input terminal IP of the transimpedance amplifier;
[0067] The gate of the NMOS transistor NM10 is connected to the gate of the PMOS transistor PM4 to serve as a negative input terminal IN of the transimpedance amplifier;
[0068] The drain of the NMOS transistor NM9 and the drain of the PMOS transistor PM3 are connected to one end of R7 to serve as the negative output terminal ON of the transimpedance amplifier;
[0069] The drain of the NMOS transistor NM10 and the drain of the PMOS transistor PM4 are connected to one end of R8 as the positive output end OP of the transimpedance amplifier;
[0070] The other end of R7 and the other end of R8 are connected to the positive input of the operational amplifier, the negative input of the operational amplifier is connected to the common mode level Vcm, the negative output of the operational amplifier is connected to the drain of the NMOS transistor NM9 and the drain of the PMOS transistor PM3, and the positive output of the operational amplifier is connected to the drain of the NMOS transistor NM10 and the drain of the PMOS transistor PM4.
[0071] Here’s how it works:
[0072] like Figure 1As shown, the input signal enters the low noise amplifier unit and is output as two differential signals, which enter the positive and negative input terminals of mixer 1 and mixer 2 respectively. Since each mixer is driven by a set of clock signals with the same frequency and a phase difference of 180°, and the mixers of different channels are driven by clock signals with the same frequency and a phase difference of 90°, the phase difference of the signal output by a single mixer is 180°, and the down-converted signals of the four signal paths are orthogonal to each other with a phase difference of 90°. After that, two fully differential active low-pass filters respectively perform low-pass filtering on the four down-converted signals. The fully differential signals output by active low-pass filter 1 are I+ and I-, belonging to the I branch, and the fully differential signals output by active low-pass filter 2 are Q+ and Q-, belonging to the Q branch. The I and Q branch signals are orthogonal to each other.
[0073] like Figure 2 As shown, the function of the balun is to convert a single-ended input signal into two fully differential signals, positive and negative. The most basic class AB amplifier is formed by connecting the gate and drain of the NMOS tube to the PMOS tube, and the positive power supply voltage VDD is directly added to the source of the PMOS tube, and the negative power supply voltage VSS is directly added to the source of the NMOS tube. In this way, the maximum transconductance value is achieved, so that the amplifier has the characteristics of high gain and large bandwidth. The left half branch is connected to the common source and common gate tube on the basis of the class AB amplifier to maintain the characteristics of signal inversion while increasing the gain. The right half branch adds a common source amplifier on the basis of the class AB amplifier. While increasing the gain, the signal inverted by the class AB amplifier is inverted again and becomes a common phase signal, thereby realizing the characteristic of converting a single-ended input signal into two fully differential signals, positive and negative. By introducing the feedback resistor Rf, the equivalent noise at the input end is inverted after passing through the right half branch, and the noise is still inverted after passing through the left half branch. Therefore, the purpose of noise elimination is achieved in the differential operation of the input end, and the characteristic of low noise is achieved.
[0074] like Figure 3 As shown, the mixer in the present invention is composed of NMOS transistors. When the driving signal is at a low level, the NMOS transistor works in the cut-off region and presents a high impedance, that is, the switch is disconnected and the frequency is cut off; when the driving signal is at a high level, the NMOS transistor works in the deep triode region. Reasonable selection of the W / L value of the NMOS transistor can make the on-resistance of the NMOS transistor smaller, presenting a low impedance, the switch is turned on, and the frequency passes. The mixer formed by using the NMOS transistor switch has the characteristics of simple structure and low power consumption.
[0075] like Figure 3As shown, when the NMOS transistor is connected as shown, it has a smaller on-resistance than directly using the NMOS tube as a switch. At the same time, due to the non-ideal factors of the switch, the high-frequency clock signal may be coupled in the signal path. Since the mixer adopts cross-coupling, the two pairs of anti-phase clocks are superimposed at the input end and then eliminated, which has an inhibitory effect on clock feedthrough.
[0076] like Figure 4 As shown, the down-converted signal after mixing is affected by out-of-band interference, clock feedthrough and harmonic components, so it is necessary to use low-pass filtering to suppress out-of-band factors. The present invention adopts an active low-pass filter structure based on a transimpedance amplifier TIA. The load capacitor CL first eliminates the high-frequency clock feedthrough signal; the parallel resistor-capacitor network serves as the feedback network of the transimpedance amplifier, determines the main pole of the low-pass filter, reduces the input impedance of the amplifier, and matches the low-impedance passive mixer structure. The second stage uses a resistor-capacitor low-pass filter structure to increase the out-of-band suppression capability.
[0077] like Figure 5 As shown in the figure, the main body of the transimpedance amplifier is a class AB amplifier, which has the characteristics of high gain and large bandwidth. In order to stabilize the output common mode point, a common mode feedback structure is formed by a common mode detection resistor and an operational amplifier.
[0078] The present invention adopts an amplifier with high gain as the input stage, and adopts a transimpedance amplifier at the output stage to further improve the gain. The whole receiver has the characteristics of high gain. The input high-frequency signal, the noise-containing down-converted signal through the passive mixer and the output signal after the two-stage low-pass filter are as follows. Figure 6 shown.
[0079] The present invention adopts Figure 1 The connection method is as follows, so the noise is mainly concentrated in the input stage. Due to the use of low noise amplifier, the overall noise is very low, such as Figure 7 shown.
[0080] The present invention realizes a receiver with single-ended input and IQ branch output through a passive mixing channel composed of 4 NMOS transistors, improves the overall gain and reduces input noise through a low-noise amplifier and a transimpedance amplifier, and improves the out-of-band suppression capability and linearity by using an active low-pass filter. The out-of-band linearity is relatively high. Figure 8 shown.
[0081] It can be seen from the above implementation scheme that the present invention not only realizes signal reception, down-conversion and clutter suppression, but also has the characteristics of high gain, high bandwidth, high linearity and low noise, thereby meeting the use requirements of multi-mode and multi-frequency radio communication systems.
Claims
1. A broadband tunable receiver, characterized in that The receiver comprises a low noise amplifier unit, a mixer unit, and an active low pass filter unit, wherein: The low noise amplifier unit is a low noise amplifier with single-ended input and differential output; The mixer unit includes a mixer 1 and a mixer 2 with the same structure, each mixer is driven by a set of clock signals with the same frequency and a phase difference of 180°, and mixers of different channels are driven by clock signals with the same frequency and a phase difference of 90°; The active low-pass filter unit comprises an active low-pass filter 1 and an active low-pass filter 2 having the same structure; The positive output terminal of the low noise amplifier is connected to the positive input terminal of mixer 1 and the positive input terminal of mixer 2 at the same time, and the negative output terminal of the low noise amplifier is connected to the negative input terminal of mixer 1 and the negative input terminal of mixer 2 at the same time; The negative output terminal of the mixer 1 is connected to the positive input terminal of the active low-pass filter 1, the positive output terminal of the mixer 1 is connected to the negative input terminal of the active low-pass filter 1, and the active low-pass filter 1 outputs fully differential signals I+ and I-; The negative output terminal of the mixer 2 is connected to the positive input terminal of the active low-pass filter 2, the positive output terminal of the mixer 2 is connected to the negative input terminal of the active low-pass filter 2, and the active low-pass filter 2 outputs fully differential signals Q+ and Q-; The low noise amplifier unit includes four NMOS transistors NM1-NM4, two PMOS transistors PM1 and PM2, and three resistors R1, R2, and Rf, wherein: The source of the NMOS transistor NM1, the source of the NMOS transistor NM2, and the source of the NMOS transistor NM3 are connected to VSS at the same time; The source of the PMOS transistor PM1, the source of the PMOS transistor PM2, one end of the resistor R1, and one end of the resistor R2 are simultaneously connected to VDD; The drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are simultaneously connected to the source of the NMOS transistor NM4; The drain of the NMOS transistor NM2 and the drain of the PMOS transistor PM2 are simultaneously connected to the gate of the transistor NM3; The gate of the NMOS transistor NM1, the gate of the PMOS transistor PM1, the gate of the NMOS transistor NM2, and the gate of the PMOS transistor PM2 are connected to each other and used as a low noise amplifier input terminal VIN; The drain of the NMOS transistor NM3 is connected to the other end of the resistor R1 and serves as the positive output terminal VO+ of the low noise amplifier; The drain of the NMOS transistor NM4 is connected to the other end of the resistor R2 and serves as the negative output terminal VO- of the low noise amplifier; The gate of the NMOS transistor NM4 is connected to a bias voltage VB; One end of the resistor Rf is connected to the input terminal VIN of the low noise amplifier, and the other end is connected to the gate of the NMOS transistor NM3; The mixer 1 and the mixer 2 are both composed of four NMOS transistors NM5-NM8, where: The source of the NMOS transistor NM5 is connected to the source of the NMOS transistor NM7 and serves as the positive input terminal RF+ of the mixer; The source of the NMOS transistor NM6 is connected to the source of the NMOS transistor NM8 and serves as the negative input terminal RF- of the mixer; The drain of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM8 and serves as the positive output terminal VO+ of the mixer; The drain of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7 and serves as the negative output terminal VO- of the mixer; The gates of the NMOS transistor NM5 and the NMOS transistor NM8 are connected to the digital clock CLK1; The gates of the NMOS transistor NM6 and the NMOS transistor NM7 are connected to the digital clock CLK2; The active low-pass filter 1 and the active low-pass filter 2 are both composed of four resistors R3-R6, four capacitors C1-C3, CL and a transimpedance amplifier TIA, wherein: One end of the capacitor CL, one end of the capacitor C2, and one end of the resistor R4 are connected to the positive input end of the transimpedance amplifier TIA as the positive input end VI+ of the active low-pass filter; The other end of the capacitor CL, one end of the capacitor C1, and one end of the resistor R3 are connected to the negative input end of the transimpedance amplifier TIA as the negative input end VI- of the active low-pass filter; The other end of the capacitor C1, the other end of the resistor R3 and the negative output end of the transimpedance amplifier TIA are connected to one end of the resistor R6; The other end of the capacitor C2, the other end of the resistor R4 and the positive output end of the transimpedance amplifier TIA are connected to one end of the resistor R5; The other end of the resistor R5 is connected to one end of the capacitor C3 as a negative output terminal VO- of the active low-pass filter; The other end of the resistor R6 is connected to the other end of the capacitor C3 to serve as the positive output terminal VO+ of the active low-pass filter.
2. The broadband tunable receiver according to claim 1, characterized in that The mixer 1 and the mixer 2 are both driven by a square wave clock signal to achieve a frequency modulation function.
3. The broadband tunable receiver according to claim 1, characterized in that The mixer 1 is driven by square wave clock signals with a frequency of flo and an initial phase of 0° and a frequency of flo and an initial phase of 180°, and the mixer 2 is driven by square wave clock signals with a frequency of flo and an initial phase of 90° and a frequency of flo and an initial phase of 270°.
4. The broadband tunable receiver according to claim 1, characterized in that The transimpedance amplifier includes two NMOS transistors NM9 and NM10, two PMOS transistors PM3 and PM4, two resistors R7 and R8, and an operational amplifier with dual-input and dual-output terminals, wherein: The source of the NMOS transistor NM9 and the source of the NMOS transistor NM10 are connected to VSS; The source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are connected to VDD; The gate of the NMOS transistor NM9 is connected to the gate of the PMOS transistor PM3 to serve as the positive input terminal IP of the transimpedance amplifier; The gate of the NMOS transistor NM10 is connected to the gate of the PMOS transistor PM4 to serve as a negative input terminal IN of the transimpedance amplifier; The drain of the NMOS transistor NM9 and the drain of the PMOS transistor PM3 are connected to one end of R7 to serve as the negative output terminal ON of the transimpedance amplifier; The drain of the NMOS transistor NM10 and the drain of the PMOS transistor PM4 are connected to one end of R8 as the positive output end OP of the transimpedance amplifier; The other end of R7 and the other end of R8 are connected to the positive input of the operational amplifier, the negative input of the operational amplifier is connected to the common mode level Vcm, the negative output of the operational amplifier is connected to the drain of the NMOS transistor NM9 and the drain of the PMOS transistor PM3, and the positive output of the operational amplifier is connected to the drain of the NMOS transistor NM10 and the drain of the PMOS transistor PM4.
Citation Information
Patent Citations
Low noise amplifier circuit
US20170070197A1