Timing system including a master device and at least one slave device that are synchronized with each other and a related synchronization method

Abstract

An embodiment of the present disclosure relates to a timing system, which includes: a master timing device and a slave timing device. The master timing device includes: a master oscillator stage, configured to receive a reference signal and generate a first master clock signal that is frequency-locked with the reference signal; a master timing stage, including a master counter configured to update a value depending on the timing of the first master clock signal, the master timing stage is configured to generate a first local clock signal of a pulse type, the timing of the pulses of the first local clock signal can be controlled by the master counter; and a master synchronization stage, configured to generate a synchronization signal synchronized with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each continuous pulse group formed by a plurality of (N) pulses of the first local clock signal. The slave timing device includes: a slave oscillator stage, configured to receive a reference signal and generate a second master clock signal that is frequency-locked with the reference signal; a slave timing stage; and a slave synchronization stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102021000016841 filed on June 28, 2021, which is incorporated herein by reference. Technical Field

[0003] The invention relates to a timing system comprising a master device and at least one slave device which are synchronized with each other and a corresponding method for synchronizing the master device and the slave device. Background Art

[0004] As is known, timing systems are currently available, each of which includes at least one pair of integrated electronic devices, which are installed in the same electronic control unit (ECU) and have a local oscillator, on which these integrated electronic devices generate a corresponding timing signal (also called a clock signal) group, which is then supplied to an external electronic device. For example, such a timing system is often used in the automotive field, where the clock signal generated by each integrated electronic device is supplied to a corresponding switching regulator, which in turn generates a voltage, which is then used in an airbag actuation system equipped in the vehicle.

[0005] In more detail, each integrated electronic device is capable of generating a corresponding set of clock signals such that they satisfy a predetermined phase relationship, for example to prevent power dissipation peaks due to simultaneous actuation of corresponding switching regulators, thereby facilitating control of power consumption. However, the lack of control over the temporal relationship between the clock signals generated by two different integrated electronic devices limits the ability to control the total dissipated power. Summary of the invention

[0006] Embodiments provide a timing system that allows the disadvantages of the prior art to be at least partially overcome.

[0007] Other embodiments provide improved timing systems and related methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a better understanding of the invention, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a block diagram of an electronic control unit including a timing system;

[0010] Figure 2 , 4 and 5 show timing diagrams of signals generated by the integrated electronics;

[0011] Figure 6 shows a block diagram associated with operations performed by the present timing system;

[0012] Figure 3 , 7 and 8 show timing diagrams of signals from the present timing system; and

[0013] Fig. 9 A block diagram of a timing system coupled to a switching regulator is shown. DETAILED DESCRIPTION

[0014] Figure 1 A timing system 1 is shown, comprising a first integrated electronic device 2 and a second integrated electronic device 4 forming an electronic control unit 5. The electronic control unit 5 further comprises a microcontroller unit 6, which generates a signal CLKIN on a corresponding pin 19, for example a square wave signal with a duty cycle equal to 50% and a nominal frequency equal to 4 MHz; the frequency accuracy of the signal CLKIN is for example equal to ±1%.

[0015] The first integrated electronic device 2 comprises a corresponding local oscillator 21 , a corresponding comparison stage 22 , a corresponding output stage 23 and a master synchronization stage 24 .

[0016] In more detail, the local oscillator 21 is, for example, a voltage-controlled variable oscillator, which generates a local signal LOC1, for example, a square wave signal with a duty cycle of 50% and a nominal frequency of, for example, 16 MHz; the frequency accuracy of the local signal LOC1 is, for example, ±5%.

[0017] The comparison stage 22 is connected to the local oscillator 21 and the pin 19 to receive the local signal LOC1 and the signal CLKIN. In addition, the comparison stage 22 controls the local oscillator 21 via a corresponding first output and generates a signal MAIN_CLK_MASTER (eg, Figure 3 As shown), for example, the signal MAIN_CLK_MASTER is a square wave signal with a duty cycle of 50% and a nominal frequency equal to the nominal frequency of the local signal LOC1 (thus, for example, equal to 16 MHz), and the frequency accuracy of the signal MAIN_CLK_MASTER is equal to the frequency accuracy of the signal CLKIN (thus, for example, equal to ±1%).

[0018] Although not shown, in a manner known per se, the comparison stage 22 may comprise a frequency divider for generating a reference signal from the signal CLKIN, wherein the frequency division factor is equal to 4, such that the reference signal has the same nominal frequency as the local signal LOC1 and the same frequency accuracy as the signal CLKIN. Furthermore, the comparison stage 22 generates a comparison signal (not shown) indicating the difference between the frequency of the local signal LOC1 and the frequency of the reference signal; this comparison signal is generated on a first output of the comparison stage 22 such that it controls the local oscillator 21.

[0019] In practice, the local oscillator 21 and the comparison stage 22 form a frequency-locked loop; the frequency of the signal MAIN_CLK_MASTER is then locked to the frequency of the signal CLKIN.

[0020] Hereinafter, the frequency of the signal MAIN_CLK_MASTER is referred to as frequency f0.

[0021] The output stage 23 receives the signal MAIN_CLK_MASTER and generates a signal TIMEBASE_MASTER, an example of which is Figure 2 In addition, the output stage 23 generates a plurality of corresponding clock signals; for example, the output stage 23 generates three clock signals, which are indicated by REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER respectively (for example, Figure 2 signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER are supplied to corresponding pins (not shown) of the first integrated electronic device 2.

[0022] Specifically, the signal TIMEBASE_MASTER has a frequency f SW , the frequency f SW = equal to the frequency f0 divided by the integer K; for example, in this description, it is assumed that K=8, so the frequency f of the signal TIMEBASE_MASTER SW In addition, the signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER have the same frequency f as the signal TIMEBASE_MASTER. SW , and are offset in time relative to TIMEBASE_MASTER by a phase shift equal to a multiple of the period 1 / f0.

[0023] By way of example only, Figure 2In the example shown, the signal REG1_CLK_MASTER is aligned in time with the signal TIMEBASE_MASTER, while the signals REG2_CLK_MASTER and REG3_CLK_MASTER are delayed relative to the signal TIMEBASE_MASTER by a delay equal to 1 / f0 and 2 / f0; furthermore, again by way of example, assume that the signals REG1_CLK_MASTER, REG2_CLK_MASTER, and REG3_CLK_MASTER have a duty cycle equal to 50%, and the signal TIMEBASE_MASTER has a duty cycle equal to 87.5%.

[0024] In more detail, in order to generate the signal TIMEBASE_MASTER and the signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER, the output stage 23 implements a reading stage 98 and a counter 99 whose (integer) value is comprised between 0 and K-1 and which is increased by one unit at each rising edge of the signal MAIN_CLK_MASTER (the count restarts from zero as soon as the value K-1 is reached); moreover, the output stage 23 generates the signal COUNT_MASTER (e.g. Figure 3 ), which signal indicates the value of counter 99 at any time.

[0025] In use, the reading stage 98 reads the counter 99 at each rising edge of the signal MAIN_CLK_MASTER. In addition, for example, whenever the reading stage 98 reads that the counter 99 has assumed the value 1, the rising edge of the signal TIMEBASE_MASTER (for reasons explained below, this rising edge is denoted by F UP This reading occurs relative to the moment when the counter 99 has actually assumed the value 1, with a lag equal to the pulse of the signal MAIN_CLK_MASTER, so that the rising edge of the signal TIMEBASE_MASTER occurs at the moment when the counter 99 becomes equal to 2. In other words, with reference to the event indicating the time when the counter 99 assumes the value 2, each rising edge of the signal TIMEBASE_MASTER occurs when the corresponding event occurs.

[0026] Similarly, whenever the reading stage 98 reads that the counter 99 has assumed the value 0, for example, F DOWN The falling edge of the signal TIMEBASE_MASTER indicated is generated; this reading occurs relative to the moment when the counter 99 actually assumes the value 0, with a lag equal to a pulse of the signal MAIN_CLK_MASTER, so the falling edge of the signal TIMEBASE_MASTER occurs at the moment when the counter 99 becomes equal to 0.

[0027] The same considerations apply to the generation of rising and falling edges of signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER. In other words, considering any signal between signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER, a corresponding rising edge and a corresponding falling edge are associated with a corresponding first threshold and a corresponding second threshold; when the value of counter 99 read by reading stage 98 is equal to the first threshold, the corresponding rising edge of the signal is generated, and when the value of counter 99 read by reading stage 98 is equal to the second threshold, the corresponding falling edge of the signal is generated. Therefore, signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER are synchronized with respect to signal TIMEBASE_MASTER, and each of them is phase-shifted with respect to signal TIMEBASE_MASTER by a corresponding number of pulses (possibly null) of signal MAIN_CLK_MASTER.

[0028] The signals MAIN_CLK_MASTER, TIMEBASE_MASTER and COUNT_MASTER are supplied to a master synchronization stage 24 (master CLKSW), which also receives the signals CLKSW_ENABLE, CLKSW_PERIOD and CLKSW_PHASE generated by the microcontroller unit 6 and generates a synchronization signal CLKSW which is available on a corresponding pin 29 of the first integrated electronic device 2 .

[0029] In more detail, the signal CLKSW_PERIOD indicates an integer number N (eg, included between 1 and 31). The signal CLKSW_PHASE indicates a hysteresis The hysteresis is equal to an integer, for example, included between 0 and K-1; in the remainder of this description, it is assumed For example, it is equal to 2. In addition, the signal CLKSW_ENABLE enables the execution of the phase alignment operation described later; hereinafter, unless otherwise specified, it is assumed that the signal CLKSW_ENABLE is equal to a logic value '1'.

[0030] This has already been said, Figure 4 As shown qualitatively in the figure, for N (in Figure 4 In each group formed by N=3 consecutive pulses (equivalently, rising edges), the synchronization signal CLKSW includes a corresponding pulse, the rising edge of which is indicated by UP CLKSWIndication) satisfies a predetermined time relationship with the group of N pulses, and thus satisfies a predetermined time relationship with the signal COUNT_MASTER, such as Figure 3 In this regard, Figure 3 and 4 In the example, the rising edges of the first pulse, the second pulse, and the third pulse in each group of three consecutive pulses of the signal TIMEBASE_MASTER are represented by F up '、F up ' and F up "'instruct.

[0031] In more detail, Figure 3 As can be seen, the rising edge UP of the synchronization signal CLKSW CLKSW With respect to the above rising edge F of the first pulse in the corresponding group of N pulses of the signal TIMEBASE_MASTER up 'The advance signal MAIN_CLK_MASTER is equal to (hence equal to 3) pulse number. In other words, in this example, when the signal COUNT_MASTER and therefore the counter 99 is at the above rising edge F up 'When the last time it became equal to 7 before it appeared, the rising edge UP CLKSW To this end, the master synchronization stage 24 can be configured to generate a rising edge UP after reading the signal COUNT_MASTER has assumed the value 6 CLKSW .

[0032] In addition, the synchronization signal CLKSW has a corresponding falling edge (with DOWN CLKSW Indication), the falling edge is relative to the rising edge UP CLKSW occurs with a delay equal to, for example, four cycles of the signal MAIN_CLK_MASTER; in other words, in this example, when the signal COUNT_MASTER is at the above rising edge F up 'After it has appeared, it becomes equal to 3 for the first time, the falling edge DOWN CLKSW Appear.

[0033] In practice, the period of the synchronization signal CLKSW is equal to T SYNC =N*(1 / f SW ); Furthermore, as explained below, the synchronization signal CLKSW allows the first integrated electronic device 2 and the second integrated electronic device 4 to be synchronized.

[0034] The second integrated electronic device 4 includes a corresponding local oscillator 41, a corresponding comparison stage 42, a corresponding output stage 43 and a slave synchronization stage (slave CLKSW) 44; in addition, the second integrated electronic device 4 includes a synchronous acquisition circuit 45, which includes a first trigger 46 and a second trigger 47, such as a clock type on a rising edge.

[0035] The local oscillator 41 is, for example, a voltage-controlled variable oscillator that generates a local signal LOC2, which is, for example, a square wave signal with a duty cycle of 50% and a nominal frequency of, for example, 16 MHz; the frequency accuracy of the local signal LOC2 is, for example, ±5%.

[0036] The comparison stage 42 is connected to the local oscillator 41 and the pin 19 to receive the local signal LOC2 and the signal CLKIN. In addition, the comparison stage 42 controls the local oscillator 41 via the corresponding first output and generates the signal MAIN_CLK_SLAVE (eg, Figure 3 As shown), the signal MAIN_CLK_SLAVE is, for example, a square wave signal having a duty cycle of 50% and a nominal frequency equal to the nominal frequency of the local signal LOC2, and the frequency accuracy of the signal MAIN_CLK_SLAVE is equal to the frequency accuracy of the signal CLKIN.

[0037] Although not shown, the comparison stage 42 of the second integrated electronic device 4 may operate in the same manner as described with reference to the comparison stage 22 of the first integrated electronic device 2 .

[0038] In practice, the local oscillator 41 and the comparison stage 42 of the second integrated electronic device 4 form a frequency-locked loop so that the frequency of the signal MAIN_CLK_SLAVE is locked to the frequency of the signal CLKIN. In addition, hereinafter, the frequency of the signal MAIN_CLK_SLAVE is referred to as the frequency f0'; since the frequency is locked to the frequency of the signal CLKIN, the frequencies f0' and f0 are locked to each other.

[0039] The first flip-flop 46 and the second flip-flop 47 are timed by the signal MAIN_CLK_SLAVE, i.e., although not shown, they receive the latter signal on the respective clock inputs. In addition, the input terminal of the first flip-flop 46 is connected to the pin 39 of the second integrated electronic device 4, which in turn is connected to the pin 29 of the first integrated electronic device 2 to receive the synchronization signal CLKSW. The input terminal of the second flip-flop 47 is connected to the output terminal of the first flip-flop 46, so that the resynchronization signal CLKSW_SYNC_SLAVE appears at the output terminal of the second flip-flop 47.

[0040] Specifically, Figure 3 As shown, any transition of the given synchronization signal CLKSW, that is, any rising edge UP CLKSW Or falling edge DOWN CLKSW , the resynchronization signal CLKSW_SYNC_SLAVE replicates the above transition of the synchronization signal CLKSW after the two rising edges of the signal MAIN_CLK_SLAVE have occurred. In other words, for example, with reference to any rising edge UP of the synchronization signal CLKSW CLKSW , the resynchronization signal CLKSW_SYNC_SLAVE has a corresponding rising edge (with UP CLKSW_SYNC Indication), the rising edge appears at the second rising edge of the signal MAIN_CLK_SLAVE, and the second rising edge appears at the rising edge UP CLKSW After that; therefore, the rising edge UP CLKSW_SYNC Relative to the rising edge UP CLKSW The hysteresis is at most equal to a time of 2*(1 / f0'). The same considerations apply to any falling edge DOWN of the synchronization signal CLKSW. CLKSW、 and the corresponding falling edge of the resynchronization signal CLKSW_SYNC_SLAVE (with DOWN CLKSW_SYNC instruct).

[0041] The resynchronization signal CLKSW_SYNC_SLAVE is supplied to the slave synchronization stage 44 along with the signal MAIN_CLK_SLAVE and the signals CLKSW_ENABLE and CLKSW_PERIOD so that the slave synchronization stage 44 can generate the signal SYNC_RST, as described below.

[0042] The output stage 43 receives the signal MAIN_CLK_SLAVE and the signal SYNC_RST, and generates a signal TIMEBASE_SLAVE, an example of which is shown in FIG. Figure 5 In addition, the output stage 43 generates a plurality of corresponding clock signals; for example, the output stage 43 generates three clock signals, Figure 5 The signals REG1_CLK_SLAVE, REG2_CLK_SLAVE and REG3_CLK_SLAVE are provided on corresponding pins (not shown) of the second integrated electronic device 4 and are synchronous with respect to TIMEBASE_SLAVE, but offset in time. By way of example only, in Figure 5In the example shown, signal REG1_CLK_SLAVE is aligned in time with signal TIMEBASE_SLAVE, while signals REG2_CLK_SLAVE and REG3_CLK_SLAVE lag behind signal MAIN_CLK_SLAVE_CLAVE by one pulse and three pulses of signal MAIN_CLAVE_SLAVE, respectively, relative to signal TIMEBASE_SLAVE; furthermore, again by way of example, it is assumed that signals REG1_CLK_SLAVE, REG2_CLK_SLAVE, and REG3_CLK_SLAVE have a duty cycle equal to 50%.

[0043] In more detail, in order to generate the signal TIMEBASE_SLAVE and the signals REG1_CLK_SLAVE, REG2_CLK_SLAVE and REG3_CLK_SLAVE, the output stage 43 cooperates with the slave synchronization stage 44 and implements a corresponding reading stage 198 and a corresponding counter 199, the (integer) value of which is comprised between 0 and K-1 and is increased by one unit at each rising edge of the signal MAIN_CLK_SLAVE (the count restarts from zero once the value K-1 is reached), with the exceptions described below. Furthermore, the output stage 43 generates the signal COUNT_SLAVE (as Figure 3 ), which signal indicates the value of counter 199 at any time.

[0044] In use, the reading stage 198 reads the counter 199 at each rising edge of the signal MAIN_CLK_SLAVE. In addition, for example, whenever the reading stage 198 reads that the counter 199 has assumed the value 1, the rising edge of the signal TIMEBASE_SLAVE (denoted by F UP_SLAVE indication) is generated; this reading occurs relative to the moment when counter 199 has actually assumed the value 1, with a lag equal to a pulse of signal MAIN_CLK_SLAVE, so that the rising edge of signal TIMEBASE_SLAVE occurs at the moment when counter 199 and therefore signal COUNT_SLAVE become equal to 2.

[0045] Furthermore, whenever the reading stage 198 reads that the counter 199 has assumed the value 0, for example, the falling edge (with F DOWN_SLAVE This reading occurs relative to the moment when counter 199 actually assumes the value 0, with a lag equal to a pulse of signal MAIN_CLK_SLAVE.

[0046] Although not shown in detail, the same considerations apply to the generation of rising and falling edges of signals REG1_CLK_SLAVE, REG2_CLK_SLAVE, and REG3_CLK_SLAVE. In other words, considering any signal between signals REG1_CLK_SLAVE, REG2_CLK_SLAVE, and REG3_CLK_SLAVE, a corresponding rising edge and a corresponding falling edge are associated with a corresponding first threshold and a corresponding second threshold; when the value of counter 199 read by read stage 198 is equal to the first threshold, the corresponding rising edge of the signal is generated, and when the value of counter 199 read by read stage 198 is equal to the second threshold, the corresponding falling edge of the signal is generated. Therefore, as previously mentioned, signals REG1_CLK_SLAVE, REG2_CLK_SLAVE, and REG3_CLK_SLAVE are synchronized with respect to signal TIMEBASE_SLAVE, and each of them is phase-shifted with respect to signal TIMEBASE_SLAVE by a corresponding number of pulses of signal MAIN_CLK_SLAVE.

[0047] The output stage 43 supplies the signal COUNT_SLAVE to the slave synchronization stage 44, which is synchronized at each rising edge UP of the resynchronization signal CLKSW_SYNC_SLAVE. CLKSW_SYNC implement Figure 6 The operation shown.

[0048] Specifically, the value of the signal COUNT_SLAVE is read (block 100) from the synchronization stage 44, and thus the value of the counter 199 is read, and it is detected (block 110) whether the read value is greater than, less than or equal to an expected value (which is, for example, equal to K-1) (it should be remembered that, in this description, it has been assumed that, for example, K=8). For example, with respect to the rising edge UP of the resynchronization signal CLKSW_SYNC_SLAVE CLKSW_SYNC , the value of the signal COUNT_SLAVE and therefore the reading of the value of the counter 199 is delayed by a delay equal to one pulse of the signal MAIN_CLOCK_SLAVE.

[0049] If the read value is equal to K-1 (output indicated by '=' of block 110), the slave synchronization stage 44 avoids interfering with the updating of the counter 199 of the second integrated electronic device 4; in other words, the output stage 43 continues to continuously update (block 115) the value of the counter 199 according to the pulses of the signal MAIN_CLK_SLAVE.

[0050] This is the case, for example, in Figure 3 As shown in the figure, when the rising edge UP CLKSW_SYNCoccurs, signal COUNT_SLAVE (and therefore counter 199) assumes the value 7, which is then reset at the next rising edge of signal MAIN_CLK_SLAVE (with F read Indication) is read from the synchronization stage 44. In this case, the slave synchronization stage 44 assigns the corresponding first information value to the signal SYNC_RST; the output stage 43 reads the first information value of the signal SYNC_RST and thus continues to update the value of the counter 199 at each rising edge of the signal MAIN_CLOCK_SLAVE; therefore, at the above rising edge F read And then at the rising edge F read After the first rising edge of the signal MAIN_CLOCK_SLAVE, the counter 199 assumes the value 0 and the value 1, respectively; these values ​​are read by the reading stage 198 of the second integrated electronic device 4, wherein the hysteresis is one pulse of the signal MAIN_CLK_MASTER. When the counter 199 (and therefore the signal COUNT_SLAVE) assumes the value 1, a falling edge F of the signal TIMEBASE_SLAVE is generated accordingly. DOWN_SLAVE , then when counter 199 (and therefore signal COUNT_SLAVE) assumes the value 2, a rising edge F of signal TIMEBASE_SLAVE is generated UP_SLAVE Therefore, the rising edge of the signal TIMEBASE_SLAVE F UP_SLAVE Appears on the rising edge of the TIMEBASE_MASTER signal F UP 'After that, and when the signal MAIN_CLOCK_SLAVE is equal to the hysteresis After a number of rising edges (ie, equal to 2 in this example) have occurred.

[0051] In practice, if the read value is equal to K-1, it means: the rising edge F of the signal TIMEBASE_SLAVE UP_SLAVE Relative to the rising edge of the signal TIMEBASE_MASTER F UP 'The phase shifted signal MAIN_CLOCK_SLAVE is equal to In this way, the counter 199 of the second integrated electronic device 4 is phase-shifted relative to the counter 99 of the first integrated electronic device 2 without any tuning (phase resynchronization) of the counter 199 of the second integrated electronic device 4. The phase shift between the signals TIMEBASE_SLAVE and TIMEBASE_MASTER is thus approximately equal to the number of pulses of the signal MAIN_CLK_SLAVE (equivalently, the signal MAIN_CLK_MASTER) (equal to ), so it is equal to the desired phase shift.

[0052] Refer again Figure 6 If the read value is changed to be equal to K-1-1 (output '<' of block 110), this means that the counter 199 of the second integrated electronic device 4 is lagging behind the above value, and it must ensure that the rising edge F of the signal TIMEBASE_SLAVE UP_SLAVE With the rising edge of the signal TIMEBASE_MASTER F UP 'The desired phase shift between .

[0053] Therefore, the second information value is assigned to the signal SYNC_RST from the synchronization stage 44 to control the output stage 43 to skip a number when updating the counter 199 of the second integrated electronic device 4, such as Figure 7 In other words, by assigning the second information value to the signal SYNC_RST, the slave synchronization stage 44 controls the output stage 43 so that the output stage 43 is at the rising edge F of the signal MAIN_CLK_SLAVE. read Force (block 120) counter 199 to zero prematurely, rather than allowing counter 199 to assume value K-1 (which is 7 in the example); thus, on the rising edge F of signal MAIN_CLOCK_SLAVE read After the first rising edge of , counter 199 then assumes the value 1. When counter 199 (and thus signal COUNT_SLAVE) assumes the values ​​1 and 2, respectively, the falling edge F of signal TIMEBASE_SLAVE DOWN_SLAVE and rising edge F UP_SLAVE is generated again. Similar to reference Figure 3 Therefore, the rising edge of the TIMEBASE_SLAVE signal F UP_SLAVE Appears on the rising edge of the TIMEBASE_MASTER signal F UP 'After that, and when the signal MAIN_CLOCK_SLAVE is equal to the hysteresis After a number of rising edges (ie, equal to 2 in this example) have occurred.

[0054] In practice, if the read value is equal to K-1-1, the counter 199 of the second integrated electronic device 4 is forced to reset to zero in advance, that is, one digit is skipped, in order to temporarily speed up the updating of the counter 199 and eliminate (as a first approximation) the lag relative to the counter 99 of the first integrated electronic device 2; in this way, at the rising edge F of the signal TIMEBASE_SLAVE UP_SLAVE With the rising edge of the signal TIMEBASE_MASTER F UP ' to obtain the desired phase shift.

[0055] Refer again Figure 6If the read value is changed to be equal to 0 (output '>' of block 110), this means that the counter 199 of the second integrated electronic device 4 is advanced relative to the above value and it must ensure that the rising edge F of the signal TIMEBASE_SLAVE UP_SLAVE With the rising edge of the signal TIMEBASE_MASTER F UP 'The desired phase shift between .

[0056] Therefore, if Figure 8 As shown, the slave synchronization stage 44 assigns the third information value to the signal SYNC_RST to control the output stage 43 to keep the value of the counter 199 of the second integrated electronic device 4 fixed for another pulse of the signal MAIN_CLK_SLAVE (block 125). In other words, at the rising edge F of the signal MAIN_CLK_SLAVE read , the output stage 43 fixes the value of the counter 199 of the second integrated electronic device 4 to zero, and the counter 199 will start to be updated again at the subsequent rising edge of the signal MAIN_CLK_SLAVE. In addition, since at the rising edge F of the signal MAIN_CLK_SLAVE read , the reading stage 198 reads the value 0 of the counter 199, so the output stage 43 generates a falling edge F of the signal TIMEBASE_SLAVE DOWN_SLAVE , the subsequent rising edge F of the signal TIMEBASE_SLAVE is generated when the output stage 43 reads the value 1 of the counter 199 UP_SLAVE (That is, at the rising edge F read In this way, even if Figure 8 In the scenario shown, the rising edge F of the TIMEBASE_SLAVE signal UP_SLAVE Also appears on the rising edge of the TIMEBASE_MASTER signal F UP 'After that, and when the signal MAIN_CLOCK_SLAVE is equal to the hysteresis After a number of rising edges (ie, equal to 2 in this example) have occurred.

[0057] In practice, if the read value is equal to 0, the updating of the counter 199 of the second device is disabled for a pulse of the signal MAIN_CLK_SLAVE, thereby temporarily slowing down the updating of the counter 199 of the second integrated electronic device 4 relative to the updating of the counter 99 of the first integrated electronic device 2, and obtaining a rising edge F of the signal TIMEBASE_SLAVE. UP_SLAVE With the rising edge of the signal TIMEBASE_MASTER F UP 'The desired phase shift between .

[0058] Typically, the second integrated electronic device 4 performs a read of the counter 199 and compares the read value with an expected value and then tunes the value of the counter 199 to maintain a phase lock with the counter 99 of the first integrated electronic device 4 .

[0059] Furthermore, in case the signal CLKSW_ENABLE is set equal to the logic value '0' by the microcontroller unit 6, the phase locking of the signals TIMEBASE_MASTER and TIMEBASE_SLAVE and thus of the signals REG1_CLK_MASTER-REG3_CLK_MASTER and REG1_CLK_SLAVE-REG3_CLK_SLAVE is disabled and the counters 99, 199 of the first integrated electronic device 2 and the second integrated electronic device 4 are incremented only based on the signals MAIN_CLK_MASTER and MAIN_CLK_SLAVE, respectively.

[0060] In contrast, with respect to the optional use of the signal CLKSW_PERIOD from the synchronization stage 44, in performing Figure 6 Prior to the operation shown, the slave synchronization stage 44 can use information related to the number of pulses N present in each consecutive pulse group of the signal TIMEBASE_MASTER to implement preliminary control. Specifically, since the number N is known, when the slave synchronization stage 44 receives the rising edge UP of the resynchronization signal CLKSW_SYNC_SLAVE CLKSW_SYNC When the slave synchronization stage 44 can verify the rising edge UP CLKSW_SYNC Does it actually correspond to the rising edge F of TIMEBASE_MASTER? up ', in which case it executes Figure 6 The operation shown, or it has been generated as an error, in which case execution is avoided from the synchronization stage 44 Figure 6 More generally, based on information related to the number N and received pulses of the resynchronization signal CLKSW_SYNC_SLAVE, the slave synchronization stage 44 can detect the presence of an anomaly.

[0061] The advantages of the present solution are apparent from the foregoing description.

[0062] In practice, the synchronization signal CLKSW allows to ensure that there is a controlled phase shift between the signal TIMEBASE_MASTER and the signal TIMEBASE_SLAVE. Between two subsequent pulses of the synchronization signal CLKSW, the timing is controlled by the signals MAIN_CLK_MASTER and MAIN_CLK_SLAVE, which are frequency-locked in any case. Furthermore, by means of the signal CLKSW_PERIOD, the number N of pulses present in each consecutive group of pulses of the signal TIMEBASE_MASTER can be selected, thereby controlling the periodicity with which the pulses of the synchronization signal CLKSW are generated, and thus the periodicity of the possible phase resynchronization of the signal TIMEBASE_SLAVE performed relative to the signal TIMEBASE_MASTER. The above number N can be selected according to the uncertainty existing between the signals MAIN_CLK_MASTER and MAIN_CLK_SLAVE; the smaller this uncertainty is, the larger the number N can be, so that the phase resynchronization of the signal TIMEBASE_SLAVE is performed only at the appropriate time.

[0063] Thus, the master-slave configuration herein allows (at least) doubling the power drive capability without losing the ability to properly balance power dissipation. Furthermore, in the case where a clock signal is supplied to, for example, corresponding switching regulators, the switching regulators operate synchronously, thereby reducing overall electromagnetic emissions.

[0064] In addition, if for any reason the signal CLKIN is not present on pin 19, the first integrated electronic device 2 and the second integrated electronic device 4 may still continue to operate, thanks to the timing provided by the respective local oscillators 21, 41; in this case, the signals MAIN_CLK_MASTER and MAIN_CLK_SLAVE will be equal to the local signals LOC1 and LOC2, respectively. This configuration, although losing the advantages of synchronization described previously, still allows the generation of clock signals, thereby facilitating the safety of the system arranged downstream of the timing system 1. Similarly, if a failure (or reset) of the first integrated electronic device 2 and / or an interruption of the synchronization signal CLKSW occurs, the second integrated electronic device 4 also continues to operate.

[0065] Finally, it is evident that modifications and variations may be made to what has been described and illustrated, without departing from the scope of the present invention, as defined in the appended claims.

[0066] For example, one or more operations previously described as being performed at the rising edge of a signal may be performed at the falling edge of the signal. Similarly, the operation of reading a counter may occur at a timing different from that which has been described.

[0067] The synchronization acquisition circuit 45 may be different from what has been described; for example it may include a different number of flip-flops. The synchronization acquisition circuit 45 may also not be present, in which case the second integrated electronic device 4 does not perform a resynchronization of the synchronization signal CLKSW. Therefore, the slave synchronization stage 44 uses the synchronization signal CLKSW instead of the resynchronization signal CLKSW_SYNC_SLAVE.

[0068] Furthermore, the signals CLK_PERIOD and CLK_ENABLE may not be generated, in which case the number N is fixed and synchronization is permanently enabled, so that system configurability is reduced. More generally, a pulse of the signal CLKSW may be generated whenever the counter 99 of the first integrated electronic device 2 becomes equal to the corresponding threshold. Furthermore, the synchronization signal CLKSW may coincide with the signal TIMEBASE_MASTER, in which case for each pulse of the signal TIMEBASE_MASTER, a Figure 6 The operation shown.

[0069] The signal CLKSW_PHASE may not be present, in which case the hysteresis is fixed.

[0070] The generation of rising and falling edges of signal TIMEBASE_MASTER may occur when read stage 98 reads that counter 99 assumes values ​​other than 1 and 0, respectively. Similarly, the generation of rising and falling edges of signal TIMEBASE_SLAVE may also occur when read stage 198 reads that counter 199 assumes values ​​other than 1 and 0, respectively.

[0071] Furthermore, all of the signals previously described may have a different duty cycle than that already described.

[0072] Each rising edge of the synchronization signal CLKSW CLKSW may have a corresponding rising edge F relative to the signal TIMEBASE_MASTER up ', which is different from the timing already described, in which case the hysteresis imposed by the microcontroller unit 6 With the rising edge of the signal TIMEBASE_SLAVE F UP_SLAVE and the rising edge of the signal TIMEBASE_MASTER F up The relationship between the phase shifts between ' can also be different from the relationship already described. In this respect, the rising edge F of the signal TIMEBASE_SLAVE UP_SLAVE and the rising edge of the signal TIMEBASE_MASTER F upThe phase shift between ' is usually determined by the number of flip-flops of the synchronous acquisition circuit 45 and by the number of counters 99 that must be read by the reading stage 98 to cause the generation of a rising edge F UP ', depends on the falling edge F of the counter 199 which must be read by the reading stage 198 to cause the generation of the signal TIMEBASE_SLAVE DOWN_SLAVE and the subsequent rising edge F UP_SLAVE The value of the synchronization signal CLKSW depends on the rising edge UP CLKSW The corresponding rising edge F of the signal TIMEBASE_MASTER UP 'There is a phase shift between them, so the amount of the latter can be determined based on the previous amount and the desired hysteresis The following embodiment is possible: In this embodiment, the rising edge UP of the synchronization signal CLKSW CLKSW Corresponding to the rising edge F of the signal TIMEBASE_MASTER, for example up 'The phase shift and hysteresis between irrelevant, and the rising edge of the COUNT_MASTER signal is read read Relative to the rising edge UP CLKSW_SYNC Being lagged depends on the lag The amount.

[0073] The time distance between each pulse of the synchronization signal CLKSW and the corresponding pulse group of the signal TIMEBASE_MASTER may also be different from what has been described. In other words, the time relationship between each pulse of the synchronization signal CLKSW and the corresponding pulse group of the signal may be different from what has been described, and may result in a corresponding change in the above-mentioned expected value of the counter 199, as shown in reference to Figure 6 mentioned.

[0074] In general, the operations mentioned in blocks 110, 115, 120 and 125 may be performed regardless of the temporal relationship between pulses of synchronization signal CLKSW and corresponding sets of pulses of signal TIMEBASE_MASTER to compare the read value of counter 199 with an expected value other than K-1.

[0075] Finally, as mentioned previously and Fig. 9 As shown, the timing system 1 may include more than one slave device; in particular, Fig. 9 In the example shown, there is a third integrated electronic device 104 which is identical to the second integrated electronic device 4 and which receives at input the signal CLKIN and the synchronization signal CLKSW. Fig. 9It shows how the signals REG1_CLK_MASTER, REG2_CLK_MASTER and REG3_CLK_MASTER are respectively supplied to the first switching regulator 201, the second switching regulator 202 and the third switching regulator 203, which generate voltages V1, V2 and V3 respectively; how the signals REG1_CLK_SLAVE, REG2_CLK_SLAVE and REG3_CLK_SLAVE are respectively supplied to the fourth switching regulator 204, the fifth switching regulator 205 and the sixth switching regulator 206, which generate voltages V4, V5 and V6 respectively. In addition, the third integrated electronic device 104 generates signals REG1_CLK_SLAVE', REG2_CLK_SLAVE' and REG3_CLK_SLAVE', which are respectively supplied to the seventh switching regulator 207, the eighth switching regulator 208 and the ninth switching regulator 209, which generate voltages V7, V8 and V9 respectively. The voltages V1 to V9 may be used as power sources for corresponding devices (eg, actuators) not shown.

[0076] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A timing system, comprising: Master timing equipment, including: The main oscillator stage is configured as: receiving a reference signal; and generating a first master clock signal frequency-locked with the reference signal; a master timing stage, comprising a master counter, the master counter being configured to update a value with a timing dependent on the first master clock signal, the master timing stage being configured to generate a first local clock signal of a pulse type, the timing of the pulses of the first local clock signal being controllable by the master counter; and a master synchronization stage configured to generate a synchronization signal synchronized with the first local clock signal, wherein the synchronization signal comprises a corresponding pulse for each consecutive pulse group formed by a plurality (N) of pulses of the first local clock signal; and From timing devices, including: The slave oscillator stage is configured as: receiving the reference signal; and generating a second master clock signal frequency-locked with the reference signal; a slave timing stage comprising a slave counter configured to update a value with a timing dependent on the second master clock signal, the slave timing stage configured to generate a second local clock signal of pulse type, the timing of the pulses of the second local clock signal being controllable by the slave counter; and From the synchronization level, it is configured as: reading the value of the slave counter at a timing dependent on the synchronization signal; comparing the read value with an expected value; According to the comparison result, the value of the slave counter is tuned to phase lock the first local clock signal and the second local clock signal.

2. The timing system according to claim 1, wherein the first master clock signal and the second master clock signal are of pulse type, wherein the master timing stage is configured to update the value of the master counter at each pulse of the first master clock signal, wherein the slave timing stage is configured to update the value of the slave counter at each pulse of the second master clock signal, and The slave synchronization stage is further configured to detect, based on the result of the comparison, whether the slave counter is behind or ahead of the expected value, or whether the slave counter has a value equal to the expected value.

3. The timing system of claim 2, wherein the slave synchronization stage is further configured to: controlling the slave timing stage to temporarily speed up the updating of the slave counter when the slave counter lags behind; controlling the slave timing stage to temporarily slow down the updating of the slave counter when the slave counter is advanced; and The slave timing stage is controlled such that when the slave counter has a value equal to the expected value, the slave timing stage continues to update the value of the slave counter at each pulse of the second master clock signal.

4. The timing system according to claim 2, wherein the slave timing stage is configured to update the slave counter such that the slave counter iteratively assumes a series of predetermined number of values, and Wherein the slave synchronization stage is configured as: controlling the slave timing stage so that the updating of the slave counter skips a value in a range of values ​​when the slave counter lags behind; and The slave timing stage is controlled to disable the updating of the slave counter for pulses of the second master clock signal when the slave counter is advanced.

5. The timing system according to claim 1, wherein the master timing stage is configured to generate a rising edge and a falling edge of the first local clock signal when the master counter assumes a first threshold and a second threshold, respectively, The master synchronization stage is configured to generate each pulse of the synchronization signal such that each pulse of the synchronization signal is temporally spaced an integer number of pulses of the first master clock signal from a corresponding edge of a pulse in a corresponding consecutive pulse group of the first local clock signal.

6. The timing system according to claim 5, wherein the master synchronization stage is configured to receive a first configuration signal indicating a desired hysteresis between the first local clock signal and the second local clock signal, and Wherein the integer number of pulses of the first master clock signal is a function of the desired hysteresis.

7. The timing system according to claim 1, wherein the slave timing device further comprises a resynchronization stage configured to generate a resynchronization signal having an edge synchronized with the second master clock signal from the synchronization signal, and Wherein the slave synchronization stage is configured such that the timing of the reading of the slave counter depends on the resynchronization signal.

8. The timing system of claim 7, wherein the resynchronization stage comprises a plurality of flip-flops connected in series and clocked by the second master clock signal.

9. The timing system of claim 1, wherein the master synchronization stage is configured to receive a second configuration signal indicating a number (N) of pulses of the group of consecutive pulses forming the first local clock signal.

10. The timing system of claim 1, further comprising a microcontroller configured to generate the reference signal.

11. The timing system according to claim 1, wherein the master timing stage is further configured to generate a plurality of master drive signals, each of the plurality of master drive signals being synchronized with the first local clock signal and phase-shifted relative to the first local clock signal by a corresponding number of pulses of the first master clock signal, and The slave timing stage is further configured to generate a plurality of slave drive signals, each of which is synchronized with the second local clock signal and phase-shifted by a corresponding number of pulses of the second master clock signal relative to the second local clock signal.

12. A system comprising: The timing system according to claim 11; as well as Multiple switching regulators, Each switching regulator is coupled to the timing system to receive corresponding signals of the master drive signal and the slave drive signal.

13. A method for synchronizing a master timing device and a slave timing device of a timing system, wherein the master timing device comprises a master oscillator stage, a master timing stage and a master synchronization stage, wherein the slave timing device comprises a slave oscillator stage, a slave timing stage and a slave synchronization stage, the method comprising: The master oscillator stage generates a first master clock signal frequency-locked with a reference signal; generating, by the master timing stage, a first local clock signal of the pulse type, the timing of the pulses of the first local clock signal being controlled by a master counter, the value of the master counter being updated in a timing dependent on the first master clock signal; as well as generating, by the master synchronization stage, a synchronization signal synchronized with the first local clock signal, the synchronization signal comprising a corresponding pulse for each consecutive pulse group formed by a plurality (N) of pulses of the first local clock signal; generating, by the slave oscillator stage, a second master clock signal frequency-locked with the reference signal; generating, by the slave oscillator stage, a second local clock signal of pulse type, the timing of the pulses of the second local clock signal being controlled by a slave counter, the value of the slave counter being updated with a timing dependent on the second master clock signal; reading, by the slave synchronization stage, the value of the slave counter with a timing dependent on the synchronization signal; By said slave synchronization stage, comparing said value read with an expected value; as well as The slave synchronization stage adjusts the value of the slave counter according to the comparison result to phase-lock the first local signal and the second local clock signal.

14. The method according to claim 13, wherein the first master clock signal and the second master clock signal are of pulse type, and The method further comprises: updating, by the master timing stage, the value of the master counter at each pulse of the first master clock signal, updating, by the slave timing stage, the value of the slave counter at each pulse of the second master clock signal, and By the slave synchronization stage, it is detected based on the result of the comparison whether the slave counter is behind or ahead with respect to the expected value, or whether the slave counter has a value equal to the expected value.

15. The method according to claim 14, further comprising: controlling the slave timing stage to temporarily speed up the updating of the slave counter when the slave counter lags behind; controlling the slave timing stage to temporarily slow down the updating of the slave counter when the slave counter is advanced; as well as The slave timing stage is controlled such that when the slave counter has a value equal to the expected value, the slave timing stage continues to update the value of the slave counter at each pulse of the second master clock signal.

16. The method according to claim 14, further comprising: updating, by the slave timing stage, the slave counter so that the slave counter iteratively assumes a series of predetermined number of values; controlling, by the slave synchronization stage, the slave timing stage such that the updating of the slave counter skips a value in the series of values ​​when the slave counter lags behind; as well as The slave timing stage is controlled by the slave synchronization stage to inhibit the updating of the slave counter for pulses of the second master clock signal when the slave counter is advanced.

17. The method according to claim 13, further comprising: When the master counter assumes a first threshold and a second threshold, respectively, the master timing stage generates a rising edge and a falling edge of the first local clock signal; as well as Each pulse of the synchronization signal is generated by the master synchronization stage such that each pulse of the synchronization signal is temporally spaced an integer number of pulses of the first master clock signal from a corresponding edge of a pulse in a corresponding group of consecutive pulses of the first local clock signal.

18. The method according to claim 17, further comprising: A configuration signal is received by the master synchronization stage, the configuration signal indicating a desired lag between the first local clock signal and the second local clock signal, wherein the integer number of pulses of the first master clock signal is a function of the desired lag.

19. The method according to claim 13, further comprising: generating, by a resynchronization stage of the slave timing device, from the synchronization signal a resynchronization signal having edges synchronized with the second master clock signal; as well as The value of the slave counter is read by the slave synchronization stage with a timing dependent on the resynchronization signal.

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