A low-power low-dropout voltage regulator
By using reference circuits and cross-coupled LDO circuits in low dropout regulators, the problem of difficult to get both low power consumption and small layout in traditional structures is solved, and the balance of low power consumption and small layout is achieved.
Patent Information
- Application Number
- CN202211339687.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-28
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2042-10-28
AI Technical Summary
Traditional low dropout regulators are difficult to achieve both low power consumption and small layout, with large static current and large layout area consumption.
The reference circuit and the cross-coupled LDO circuit are adopted. The reference circuit provides nA level quiescent current and reference voltage. The cross-coupled LDO circuit uses the cross-coupled structure to stably output the voltage input by the reference circuit without using a resistor.
A low-power low dropout regulator is realized, reducing quiescent current, reducing layout area, and avoiding the use of large resistors.
Smart Images
Figure CN115617109B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a low-power low-voltage difference regulator. Background Art
[0002] Low voltage dropout regulators are extremely important in various systems and are usually used to generate stable voltages to power the system. Low voltage dropout regulators implemented using CMOS technology have been continuously optimized for power supply efficiency.
[0003] Conventional low dropout regulators such as Figure 1 As shown in the figure, the function of the op amp structure and the resistor network in the circuit makes the output voltage proportional to the input voltage, and obtains a stable output voltage VOUT. C1 is used to adjust the phase margin of the circuit. However, this circuit structure has a disadvantage. The value of VOUT is usually above 1V. If the static current of the overall circuit is to be small, the resistance value of the resistor used must be very large. If a current of several nA is to be achieved, a resistor of several hundred MΩ is required, and a considerable area is consumed on the layout. Considering the cost of wafer production, if the layout area is to be kept small, the resistance value of the resistor used cannot be too large, and the static current will become very large. Summary of the invention
[0004] The present invention provides a low-power low-voltage difference regulator, which solves the problem that small layout and low power consumption cannot be achieved simultaneously in the traditional structure.
[0005] The present invention adopts the following technical solution: a low-power low-dropout voltage regulator, comprising a reference circuit and a cross-coupled LDO circuit, wherein the output end of the reference circuit is connected to the input end of the cross-coupled LDO circuit;
[0006] The reference circuit can provide nA-level quiescent current and reference voltage for the cross-coupled LDO circuit;
[0007] The cross-coupled LDO circuit stably outputs the reference voltage input by the reference circuit to the output end of the cross-coupled LDO circuit through a cross-coupling structure.
[0008] Further, the reference circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a first resistor R1, a second resistor R2, a first triode T1, a second triode T2, and a third triode T3;
[0009] The gate of the fifth MOS transistor M5 is respectively connected to the gate of the sixth MOS transistor M6, the drain of the third MOS transistor M3, the drain of the first MOS transistor M1, the gate of the eighth MOS transistor M8, and the gate of the tenth MOS transistor M10; the source of the fifth MOS transistor M5 is connected to the power supply; the drain of the fifth MOS transistor M5 is connected to the source of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to the source of the second MOS transistor M2; the gate of the first MOS transistor M1 is connected to the gate and drain of the second MOS transistor M2; the source of the first MOS transistor M1 is respectively connected to the gate of the fourth MOS transistor M4, the gate of the seventh MOS transistor M7, the gate of the ninth MOS transistor M9, and one end of the first resistor R1; the other end of the first resistor R1 is connected to the emitter of the first triode T1; the collector of the first triode T1 is connected to the signal ground; the base of the first triode T1 is respectively connected to the base of the second triode T2 and the signal ground;
[0010] The source of the sixth MOS transistor M6 is connected to the power supply, the drain of the sixth MOS transistor M6 is connected to the gate of the fourth MOS transistor M4, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the emitter of the second triode T3, and the collector of the second triode T3 is connected to the signal ground;
[0011] The source of the eighth MOS transistor M8 is connected to the power supply, the drain of the eighth MOS transistor M8 is connected to the source of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the emitter of the third triode T3, and the collector and base of the third triode T3 are both connected to the signal ground;
[0012] The source of the tenth MOS tube M10 is connected to the power supply, the drain of the tenth MOS tube M10 is connected to the source of the ninth MOS tube M9, the drain of the ninth MOS tube M9 is connected to the gate and drain of the eleventh MOS tube M11, and the source of the eleventh MOS tube M11 is connected to the signal ground.
[0013] Further, the cross-coupled LDO circuit includes a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22, a twenty-third MOS tube M23, and a twenty-fourth MOS tube M24;
[0014] The source of the fourteenth MOS tube M14 is respectively connected to the source of the fifteenth MOS tube M15 and the source of the sixteenth MOS tube M16, the gate of the fourteenth MOS tube M14 is respectively connected to the gate and drain of the fifteenth MOS tube M15, the drain of the fourteenth MOS tube M14 is respectively connected to the drain and gate of the eighteenth MOS tube M18, and the source of the eighteenth MOS tube M18 is connected to the signal ground;
[0015] The source of the fifteenth MOS tube M15 is connected to the drain of the twenty-fourth MOS tube M24 and the source of the seventeenth MOS tube M17, the drain of the twelfth MOS tube M12 is connected to the drain of the fifteenth MOS tube M15, the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, and the source of the twelfth MOS tube M12 is connected to the signal ground;
[0016] The gate and drain of the sixteenth MOS tube M16 are both connected to the gate of the seventeenth MOS tube M16, the drain of the thirteenth MOS tube M13 is connected to the drain of the sixteenth MOS tube M16, and the source of the thirteenth MOS tube M13 is connected to the signal ground;
[0017] The source of the twenty-fourth MOS tube M24 is connected to the power supply, the gate of the twenty-fourth MOS tube M24 is connected to the drain of the twenty-second MOS tube M22, the drain of the seventeenth MOS tube M17 is connected to the drain and gate of the twentieth MOS tube M20, and the source of the twentieth MOS tube M20 is connected to the signal ground;
[0018] The source of the twenty-second MOS tube M22 is connected to the power supply, the gate of the twenty-second MOS tube M22 is connected to the gate and drain of the twenty-third MOS tube M23, the drain of the twenty-second MOS tube M22 is connected to the drain of the nineteenth MOS tube M19, the gate of the nineteenth MOS tube M19 is connected to the gate of the eighteenth MOS tube M18, and the source of the nineteenth MOS tube M19 is connected to the signal ground;
[0019] The source of the twenty-third MOS tube M23 is connected to the power supply, the drain of the twenty-third MOS tube M23 is connected to the drain of the twenty-first MOS tube M21, the gate of the twenty-first MOS tube M21 is connected to the gate of the twentieth MOS tube M20, and the source of the twenty-first MOS tube M21 is connected to the signal ground.
[0020] Furthermore, a first capacitor C1 is provided between the drain and the gate of the twenty-fourth MOS transistor M24.
[0021] Beneficial effects of the present invention: The present invention adopts a reference circuit and a cross-coupled LDO circuit. The reference circuit can provide a nA-level quiescent current for the cross-coupled LDO circuit, thereby reducing the quiescent current in the low-voltage difference regulator and achieving low power consumption of the low-voltage difference regulator. The cross-coupled LDO circuit converts the voltage input by the reference circuit to the output end through a cross-coupling structure. No resistors are used in the circuit, thereby achieving a small layout. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a structural diagram of a low voltage dropout regulator in the prior art.
[0023] Figure 2 It is a structural diagram of the low voltage dropout regulator of the present invention. DETAILED DESCRIPTION
[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. The described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.
[0025] In an embodiment of the present invention, Figure 2 FIG. 1 is a schematic diagram of a low-power low-dropout voltage regulator according to the present invention. Figure 2 As shown, the present invention includes a reference circuit 21 and a cross-coupled LDO circuit 22, wherein the output end of the reference circuit is connected to the input end of the cross-coupled LDO circuit;
[0026] The reference circuit 21 can provide nA-level quiescent current and reference voltage for the cross-coupled LDO circuit 22 . The cross-coupled LDO circuit 22 stably outputs the reference voltage input by the reference circuit 21 to the output end of the cross-coupled LDO circuit through a cross-coupling structure.
[0027] The reference circuit provides a mirror current source for the two tail current source tubes of the cross-coupled LDO circuit, and provides a reference voltage for the input end of the cross-coupled LDO circuit 22. The cross-coupled LDO circuit converts the input reference voltage to the output end.
[0028] The present invention adopts a reference circuit and a cross-coupled LDO circuit. The reference circuit can provide a nA-level quiescent current for the cross-coupled LDO circuit, thereby reducing the quiescent current in the low-voltage difference regulator and achieving low power consumption of the low-voltage difference regulator. The cross-coupled LDO circuit converts the voltage input by the reference circuit to the output end through a cross-coupling structure. No resistor is used in the circuit, thereby achieving a small layout.
[0029] In one embodiment of the present invention, the reference circuit 21 generates a PTAT current, controls two tail current source tubes of the cross-coupled LDO circuit, and provides a reference voltage for the input end of the cross-coupled LDO circuit. The specific structure is as follows: it includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, and a third transistor T3;
[0030] The gate of the fifth MOS transistor M5 is respectively connected to the gate of the sixth MOS transistor M6, the drain of the third MOS transistor M3, the drain of the first MOS transistor M1, the gate of the eighth MOS transistor M8, and the gate of the tenth MOS transistor M10; the source of the fifth MOS transistor M5 is connected to the power supply; the drain of the fifth MOS transistor M5 is connected to the source of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to the source of the second MOS transistor M2; the gate of the first MOS transistor M1 is connected to the gate and drain of the second MOS transistor M2; the source of the first MOS transistor M1 is respectively connected to the gate of the fourth MOS transistor M4, the gate of the seventh MOS transistor M7, the gate of the ninth MOS transistor M9, and one end of the first resistor R1; the other end of the first resistor R1 is connected to the emitter of the first triode T1; the collector of the first triode T1 is connected to the signal ground; the base of the first triode T1 is respectively connected to the base of the second triode T2 and the signal ground;
[0031] The source of the sixth MOS transistor M6 is connected to the power supply, the drain of the sixth MOS transistor M6 is connected to the gate of the fourth MOS transistor M4, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the emitter of the second triode T3, and the collector of the second triode T3 is connected to the signal ground;
[0032] The source of the eighth MOS transistor M8 is connected to the power supply, the drain of the eighth MOS transistor M8 is connected to the source of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the emitter of the third triode T3, and the collector and base of the third triode T3 are both connected to the signal ground;
[0033] The source of the tenth MOS tube M10 is connected to the power supply, the drain of the tenth MOS tube M10 is connected to the source of the ninth MOS tube M9, the drain of the ninth MOS tube M9 is connected to the gate and drain of the eleventh MOS tube M11, and the source of the eleventh MOS tube M11 is connected to the signal ground.
[0034] In one embodiment of the present invention, the cross-coupled LDO circuit 22 converts the input reference voltage to the output terminal voltage, and its structure is as follows: it includes a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22, a twenty-third MOS tube M23, and a twenty-fourth MOS tube M24;
[0035] The source of the fourteenth MOS tube M14 is respectively connected to the source of the fifteenth MOS tube M15 and the source of the sixteenth MOS tube M16, the gate of the fourteenth MOS tube M14 is respectively connected to the gate and drain of the fifteenth MOS tube M15, the drain of the fourteenth MOS tube M14 is respectively connected to the drain and gate of the eighteenth MOS tube M18, and the source of the eighteenth MOS tube M18 is connected to the signal ground;
[0036] The source of the fifteenth MOS tube M15 is connected to the drain of the twenty-fourth MOS tube M24 and the source of the seventeenth MOS tube M17, the drain of the twelfth MOS tube M12 is connected to the drain of the fifteenth MOS tube M15, the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, and the source of the twelfth MOS tube M12 is connected to the signal ground;
[0037] The gate and drain of the sixteenth MOS tube M16 are both connected to the gate of the seventeenth MOS tube M16, the drain of the thirteenth MOS tube M13 is connected to the drain of the sixteenth MOS tube M16, and the source of the thirteenth MOS tube M13 is connected to the signal ground;
[0038] The source of the twenty-fourth MOS tube M24 is connected to the power supply, the gate of the twenty-fourth MOS tube M24 is connected to the drain of the twenty-second MOS tube M22, the drain of the seventeenth MOS tube M17 is connected to the drain and gate of the twentieth MOS tube M20, and the source of the twentieth MOS tube M20 is connected to the signal ground;
[0039] The source of the twenty-second MOS tube M22 is connected to the power supply, the gate of the twenty-second MOS tube M22 is connected to the gate and drain of the twenty-third MOS tube M23, the drain of the twenty-second MOS tube M22 is connected to the drain of the nineteenth MOS tube M19, the gate of the nineteenth MOS tube M19 is connected to the gate of the eighteenth MOS tube M18, and the source of the nineteenth MOS tube M19 is connected to the signal ground;
[0040] The source of the 23rd MOS tube M23 is connected to the power supply, the drain of the 23rd MOS tube M23 is connected to the drain of the 21st MOS tube M21, the gate of the 21st MOS tube M21 is connected to the gate of the 20th MOS tube M20, and the source of the 21st MOS tube M21 is connected to the signal ground. A first capacitor C1 is provided between the drain and the gate of the 24th MOS tube M24.
[0041] The structure of the present invention can achieve a quiescent current of nA level without using a large resistor. Among them, the reference circuit can generate a quiescent current of nA level so that the quiescent current in the entire low voltage difference regulator is nA level. At the same time, the reference circuit also provides a reference voltage and a mirror current source for the cross-coupled LDO circuit, and the cross-coupling structure of the cross-coupled LDO circuit is specifically the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14, the fifteenth MOS tube M15, the sixteenth MOS tube M16 and the seventeenth MOS tube M17.
[0042] The cross-coupling structure makes the current in the twelfth MOS tube M12 equal to that in the thirteenth MOS tube M13, and at the same time ensures that the source terminal voltages of the fifteenth MOS tube M15 and the sixteenth MOS tube M16 are equal, thereby realizing the conversion from the reference voltage to the output voltage.
[0043] If the VOUT port changes, the gate end of the fifteenth MOS tube M15 will change in the same way, and the drain end of the fourteenth MOS tube M14 will change in the opposite way, that is, the gate end of the nineteenth MOS tube M19 will change in the opposite way, and the drain end of the nineteenth MOS tube M19 will change in the same way, and the gate end of the twenty-fourth MOS tube M24 will change in the same way, and the drain end of the twenty-fourth MOS tube M24 will change in the opposite way, that is, the VOUT port will change in the opposite way, and negative feedback will be achieved. At the same time, if the VOUT port changes, the source end of the seventeenth MOS tube M17 will change in the same way, and the drain end of the seventeenth MOS tube M17 will change in the same way, and the gate end of the twenty-first MOS tube M21 will change in the same way, and the drain end of the twenty-first MOS tube M21 will change in the opposite way, and the gate end of the twenty-second MOS tube M22 will change in the opposite way, and the drain end of the twenty-second M22 will change in the same way, and the gate end of the twenty-fourth MOS tube M24 will change in the same way, and the drain end of the twenty-fourth MOS tube M24 will change in the opposite way, that is, the VOUT port will change in the opposite way, and negative feedback will be achieved. The negative feedback of the two loops ensures the stability of the VOUT port output.
[0044] The first capacitor C1 is used to adjust the phase margin of the circuit. The static current in the mirror current source flowing through the eleventh MOS tube M11 generated by the reference circuit 21 is very small, so that the static current in the cross-coupled LDO circuit is very small, and specifically can achieve nA level current. The current of each branch in the cross-coupled LDO circuit provides a multiple of the current of the mirror current source, and the specific size depends on the ratio of the tube size in each mirror structure. Compared with the traditional structure, this structure does not use resistors, and ensures a lower static current with a small layout area.
[0045] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.
Claims
1. A low-power low-dropout voltage regulator, characterized in that: It comprises a reference circuit (21) and a cross-coupled LDO circuit (22), wherein the output end of the reference circuit is connected to the input end of the cross-coupled LDO circuit; The reference circuit (21) can provide nA-level static current and reference voltage for the cross-coupled LDO circuit (22); The cross-coupled LDO circuit (22) stably outputs the reference voltage input by the reference circuit (21) to the output end of the cross-coupled LDO circuit through a cross-coupling structure; The cross-coupled LDO circuit (22) comprises a twelfth MOS tube (M12), a thirteenth MOS tube (M13), a fourteenth MOS tube (M14), a fifteenth MOS tube (M15), a sixteenth MOS tube (M16), a seventeenth MOS tube (M17), an eighteenth MOS tube (M18), a nineteenth MOS tube (M19), a twentieth MOS tube (M20), a twenty-first MOS tube (M21), a twenty-second MOS tube (M22), a twenty-third MOS tube (M23), and a twenty-fourth MOS tube (M24); The source of the fourteenth MOS tube (M14) is respectively connected to the source of the fifteenth MOS tube (M15), the source of the sixteenth MOS tube (M16) and the reference circuit (21); the gate of the fourteenth MOS tube (M14) is respectively connected to the gate and drain of the fifteenth MOS tube (M15); the drain of the fourteenth MOS tube (M14) is respectively connected to the drain and gate of the eighteenth MOS tube (M18); and the source of the eighteenth MOS tube (M18) is connected to the signal ground; The source of the fifteenth MOS tube (M15) is respectively connected to the drain of the twenty-fourth MOS tube (M24) and the source of the seventeenth MOS tube (M17) and serves as the output end of the cross-coupled LDO circuit; the drain of the twelfth MOS tube (M12) is connected to the drain of the fifteenth MOS tube (M15); the gate of the twelfth MOS tube (M12) is connected to the gate of the thirteenth MOS tube (M13) and the reference circuit (21); and the source of the twelfth MOS tube (M12) is connected to the signal ground; The gate and drain of the sixteenth MOS tube (M16) are both connected to the gate of the seventeenth MOS tube (M17), the drain of the thirteenth MOS tube (M13) is connected to the drain of the sixteenth MOS tube (M16), and the source of the thirteenth MOS tube (M13) is connected to the signal ground; The source of the twenty-fourth MOS tube (M24) is connected to the power supply, the gate of the twenty-fourth MOS tube (M24) is connected to the drain of the twenty-second MOS tube (M22), the drain of the seventeenth MOS tube (M17) is connected to the drain and gate of the twentieth MOS tube (M20), and the source of the twentieth MOS tube (M20) is connected to the signal ground; The source of the twenty-second MOS tube (M22) is connected to the power supply, the gate of the twenty-second MOS tube (M22) is connected to the gate and drain of the twenty-third MOS tube (M23), the drain of the twenty-second MOS tube (M22) is connected to the drain of the nineteenth MOS tube (M19), the gate of the nineteenth MOS tube (M19) is connected to the gate of the eighteenth MOS tube (M18), and the source of the nineteenth MOS tube (M19) is connected to the signal ground; The source of the twenty-third MOS tube (M23) is connected to the power supply, the drain of the twenty-third MOS tube (M23) is connected to the drain of the twenty-first MOS tube (M21), the gate of the twenty-first MOS tube (M21) is connected to the gate of the twentieth MOS tube (M20), and the source of the twenty-first MOS tube (M21) is connected to the signal ground.
2. The low-power low-dropout voltage regulator according to claim 1, characterized in that: The reference circuit (21) comprises a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), a seventh MOS tube (M7), an eighth MOS tube (M8), a ninth MOS tube (M9), a tenth MOS tube (M10), an eleventh MOS tube (M11), a first resistor (R1), a second resistor (R2), a first triode (T1), a second triode (T2), and a third triode (T3); The gate of the fifth MOS tube (M5) is respectively connected to the gate of the sixth MOS tube (M6), the drain of the third MOS tube (M3), the drain of the first MOS tube (M1), the gate of the eighth MOS tube (M8), and the gate of the tenth MOS tube (M10); the source of the fifth MOS tube (M5) is connected to the power supply; the drain of the fifth MOS tube (M5) is connected to the source of the third MOS tube (M3); the gate of the third MOS tube (M3) is connected to the source of the second MOS tube (M2); the first MOS tube (M10) is connected to the gate of the eighth MOS tube (M8), and the gate of the tenth MOS tube (M10) is connected to the gate of the sixth MOS tube (M6), the drain of the third MOS tube (M3), the gate of the eighth MOS tube (M8), and the gate of the tenth MOS tube (M10); 1) is connected to the gate and drain of the second MOS tube (M2), the source of the first MOS tube (M1) is respectively connected to the gate of the fourth MOS tube (M4), the gate of the seventh MOS tube (M7), the gate of the ninth MOS tube (M9) and one end of the first resistor (R1), the other end of the first resistor (R1) is connected to the emitter of the first triode (T1), the collector of the first triode (T1) is connected to the signal ground, and the base of the first triode (T1) is respectively connected to the base of the second triode (T2) and the signal ground; The source of the sixth MOS tube (M6) is connected to the power supply, the drain of the sixth MOS tube (M6) is connected to the source of the fourth MOS tube (M4), the drain of the fourth MOS tube (M4) is connected to the drain of the second MOS tube (M2), the source of the second MOS tube (M2) is connected to the emitter of the second triode (T3), and the collector of the second triode (T3) is connected to the signal ground; The source of the eighth MOS tube (M8) is connected to a power supply, the drain of the eighth MOS tube (M8) is connected to the source of the seventh MOS tube (M7), the drain of the seventh MOS tube (M7) is connected to one end of the second resistor (R2) and the source of the fourteenth MOS tube (M14), the other end of the second resistor (R2) is connected to the emitter of the third triode (T3), and the collector and base of the third triode (T3) are both connected to a signal ground; The source of the tenth MOS tube (M10) is connected to a power supply, the drain of the tenth MOS tube (M10) is connected to the source of the ninth MOS tube (M9), the drain of the ninth MOS tube (M9) is connected to the gate and drain of the eleventh MOS tube (M11) and the gate of the twelfth MOS tube (M12), and the source of the eleventh MOS tube (M11) is connected to a signal ground.
3. The low-power low-dropout voltage regulator according to claim 1, characterized in that: A first capacitor (C1) is provided between the drain and the gate of the twenty-fourth MOS tube (M24).
Citation Information
Patent Citations
Low dropout regulator with low power consumption
CN218446499U