Wafer defect detection optimization method and device

Abstract

An embodiment of the present application discloses a wafer defect detection optimization method and device, which relate to the field of semiconductor technology. The method includes: receiving a target wafer box and obtaining corresponding tail number information, the tail number information is used to distinguish detection batches, and the target wafer box contains wafers to be tested produced by various cavities; determining the target detection items of the target wafer box, and sampling target wafers with corresponding numbers from the target wafer box according to the target detection items, the corresponding wafer sampling mechanism and the tail number information; wherein different detection items correspond to different wafer sampling mechanisms, and the wafer sampling mechanism is used to determine and calculate the number and number of wafers to be sampled; and performing defect detection on the selected target wafers.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a wafer defect detection optimization method and device. Background Art

[0002] In the integrated circuit process, after the wafer is produced in the inner cavity of the machine, it needs to be inspected for defects. Defect inspection is an optical and electronic inspection to promptly detect problems with wafers in the production batch.

[0003] In the prior art, wafer defect detection is performed by randomly inspecting wafer cassettes for transit inspection, or by randomly inspecting wafers with fixed numbers within a cassette. This method of inspecting wafer cassettes fails to account for defects within the machine cavity, and its low inspection coverage makes it prone to hidden defects. Summary of the Invention

[0004] The present invention provides a method and device for optimizing wafer defect detection. The technical solution is as follows:

[0005] In one aspect, a wafer defect detection optimization method is provided, the method comprising:

[0006] Receive a target wafer box and obtain corresponding tail number information, where the tail number information is used to distinguish test batches, and the target wafer box contains wafers to be tested produced by various cavities;

[0007] Determining a target inspection item for the target wafer box, and spot-checking target wafers with corresponding numbers from the target wafer box according to the target inspection item, the corresponding wafer spot-checking mechanism, and the tail digit information; wherein different inspection items correspond to different wafer spot-checking mechanisms, and the wafer spot-checking mechanism is used to determine and calculate the number and number of wafers to be spot-checked;

[0008] Defect detection is performed on the selected target wafer.

[0009] On the other hand, a wafer defect detection optimization device is provided, which is used for wafer defect detection. The device includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the above-mentioned wafer defect detection optimization method.

[0010] The beneficial effects brought about by the above technical solution include at least: sorting and numbering the wafers in the wafer box according to the order of the cavities. During the extraction process, the corresponding sampling mechanism is determined according to the bit information of the target wafer box and the sampling items, and the target wafer is selected according to the corresponding first sampling mechanism or the second sampling mechanism. During the sampling process, whether it is bright field sampling or dark field sampling, the wafer number corresponding to the different cavities can be selected according to its reaction speed; in addition, by recording the number of rounds for cyclic sampling, the detection coverage of bright field detection can be increased to 80%, and dark field detection can achieve full coverage. Compared with the fixed number sampling and random sampling of wafer boxes in the related art, the sampling coverage and efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is the defect detection method in the related art provided by this application;

[0012] Figure 2 is a flow chart of a wafer defect detection optimization method provided by an embodiment of the present application;

[0013] Figure 3 Schematic diagram of the arrangement of wafers to be tested in different cavities in a wafer box provided in an embodiment of the present application;

[0014] Figure 4 Schematic diagram of the sampling mechanism of bright field detection provided in an embodiment of the present application;

[0015] Figure 5 This is a schematic diagram of the random inspection mechanism for dark field detection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0017] In this document, "plurality" refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0018] In related technologies such as Figure 1As shown in the figure, a wafer cassette contains 25 wafers to be tested. These wafers come from different cavities of a production machine. Batches of wafers produced in different cavities may exhibit variations in precision and quality. Current defect detection methods select wafers with corresponding numbers from a set of wafer cassettes for testing. For example, wafers #1 and #25 are always selected for testing. This situation can result in some wafers in production cavities not being tested for a period of time. Furthermore, the testing locations within the cassette remain fixed, resulting in low detection coverage.

[0019] Figure 2 : is a flowchart of the wafer defect detection optimization method provided in an embodiment of the present application, comprising the following steps:

[0020] Step 201 : receiving a target wafer box and obtaining corresponding tail number information, where the tail number information is used to distinguish test batches, and the target wafer box contains wafers to be tested produced by various cavities.

[0021] The wafers to be tested produced by the machine need to be loaded onto trays for inspection. The wafer box is usually 5*5 in size and can hold 25 wafers to be tested. The fault detector scan tool is a device specifically used for wafer defect detection. It records and identifies the defects through the unique number of the wafer box. In this solution, the tail digit identification marking method is used to distinguish the inspection batches based on the wafer number, that is, the tail digit numerical identification of the number. For example, the number of the wafer box submitted for inspection is: ABCD23981, and its tail digit information is 1. During the inspection process, the tail digit number can be set to mark in a cyclic manner according to the order in which the target wafer boxes are received.

[0022] In addition, this solution takes into account the multi-cavity situation of the production machine. The wafers to be tested in the target wafer box are wafers from different cavities. For example, if the production machine contains 5 cavities, they will be numbered and placed in sequence according to the number and order of cavities when they are sent for inspection. Figure 3 As shown in the figure, A, B, C, D, and E represent wafers to be tested produced by five different cavities. The wafers from different cavities are placed in the wafer box in order and numbered from slot #1 to slot #25.

[0023] Step 202 : When the target detection item is bright field detection, a first sampling mechanism is determined. The first sampling mechanism includes sampling at least two wafers to be tested from different production chambers from the target detection box according to a first sampling formula.

[0024] Wafer defect detection includes bright-field inspection and dark-field inspection. In bright-field inspection, the incident light source transmits incident light vertically to the surface of the wafer to be tested. The detector is placed vertically and receives both reflected light and stray light. Because the detector always receives reflected light, the field of view is bright. Only scattered light from defects cannot reach the detector. In other words, the area without defects is bright, while the defect area appears dark due to scattered light. This operating mode is called bright-field inspection.

[0025] In darkfield inspection, the solid angle of the lens is larger than that of the incident light. This avoids reflected light from the wafer surface, allowing only stray light from defects to reach the lens. The field of view on the wafer surface is dark; areas without defects are completely dark, while scattered light from defects allows detection of surface defects, particles, and scratches. This operating mode is called darkfield inspection.

[0026] Due to different detection mechanisms, the reaction time varies. The reaction time of bright field detection is longer than that of dark field detection. Therefore, different sampling inspection mechanisms need to be set up for different detection items.

[0027] When bright field inspection is required for the target wafer box to be inspected, the first sampling mechanism is selected. The first sampling mechanism needs to sample at least two wafers to be tested from different production chambers in the target inspection box according to the first sampling formula. Figure 3 As shown in the figure, the wafers sampled are wafers #1 and #25 (cavity A and cavity E). However, in order to achieve efficient detection and high coverage, it is necessary to combine the tail number information for reasonable allocation.

[0028] In a possible implementation, when the first sampling mechanism selects two wafers to be tested, the first sampling formula P(x) is expressed as follows:

[0029] P(x)=(a,b|a=x+1,b=x+14,x≤4)

[0030] P(x)=(a,b|a=x+2,b=x+16,x≥5)

[0031] Where P(x) represents the target wafer selected under the corresponding mantissa and extraction mechanism conditions, x represents the mantissa information of the target wafer box, and a and b represent the two selected wafer numbers. The value range of x is an integer between 0 and 9.

[0032] According to the above formula, when the tail digit information does not exceed 4 and the tail digit information of the wafer box to be inspected is 0, the corresponding wafer numbers are #1 and #14 (A and D); when the tail digit information is 1, the corresponding wafer numbers are #2 and #15 (B and E). Sequentially, the tail digit 2 is used to inspect #3 and #16 (C and A), the tail digit 3 is used to inspect #4 and #17 (D and B), and the tail digit 4 is used to inspect #5 and #18 (E and C). When the tail digit information exceeds 4, the tail digit 5 ​​is used to inspect #7 and #21 (B and A), the tail digit 6 is used to inspect #8 and #22 (C and B), the tail digit 7 is used to inspect #9 and #23 (D and C), the tail digit 8 is used to inspect #10 and #24 (E and D), and the tail digit 9 is used to inspect #11 and #25 (A and E). In this way, the inspection is carried out cyclically, as follows Figure 4 It should be noted that during this random inspection process, #6, #12, #13, #19, and #20 in the matrix are ignored. However, the inspection position is changed during each random inspection, and the wafers inspected each time come from at least two different production chambers. Compared to the method of fixedly collecting data at two locations, the inspection coverage rate is greatly improved after one round of inspection. The inspection coverage rate in the related art is 2 / 25 = 8%, and the optimized inspection coverage rate is 20 / 25 = 80%.

[0033] Step 203 : When the target detection item is dark field detection, a second sampling mechanism is determined. The second sampling mechanism includes sampling n wafers to be tested from different production chambers from the target detection box according to a second sampling formula.

[0034] When dark-field inspection is required for the target wafer cassette, the second sampling mechanism is used. This mechanism involves sampling n wafers from different production chambers from the target cassette according to the second sampling formula. Here, n is a positive integer not less than the number of chambers in the machine.

[0035] In a possible implementation, when the second sampling mechanism selects 5 wafers to be tested, the second sampling formula P(x) is expressed as follows:

[0036] P(x)=A(x+1,:),x≤4

[0037] P(x)=A(x-2,:),x≥5

[0038] Here, A(x+1,:) selects all wafers in the x+1th row of the target cassette matrix, and A(x-2,:) selects all wafers in the x-2th row of the target cassette matrix, where the five wafers in that row are produced by all chambers. For example, when the digit number does not exceed 4 and the digit number of the wafer cassette being inspected is 0, the corresponding wafer numbers are #1 to #5 (wafers in the first row, chambers A to E); when the digit number is 1, the corresponding wafer numbers are #6 and #10 (wafers in the second row, chambers A to E). Sequentially, wafers with a digit number of 2 are sampled for inspection, wafers #11 and #15 (wafers in the third row, chambers A to E), wafers with a digit number of 3 are sampled for inspection, wafers #16 and #20 (wafers in the fourth row, chambers A to E), and wafers #21 and #25 (wafers in the fifth row, chambers A to E) are sampled for inspection. When the tail digit information exceeds 4, the tail digits 5 to 9 are randomly checked from the first row to the fifth row in the same manner as the tail digits 1 to 4. Figure 5 This random inspection method uses rows as units and performs random inspections in a cycle. After one round of inspection, the inspection coverage rate reaches 100%, that is, the wafers in all positions of the wafer box matrix can be inspected and all cavities are covered.

[0039] Step 204 : Calculate the target wafer number based on the mantissa information and the first sampling formula or the second sampling formula, and select the corresponding target wafer.

[0040] Step 205 , performing defect detection on the selected target wafer.

[0041] Defect detection includes chamber, slot effect, diffusion fork scratch, and CMP micro-scratch. In some embodiments, each wafer cassette to be inspected may be subjected to bright field inspection and dark field inspection in sequence to ensure detection accuracy.

[0042] Step 206 : When the round number information reaches a preset value, the wafer sampling rates of the wafers under the bright field detection and the dark field detection are respectively obtained.

[0043] As mentioned above, when inspecting a target cassette, the inspection equipment also obtains the round number information. The round number information is used to indicate the number of cycles of the cassette's tail number, that is, the number of times the corresponding target wafer is inspected in a loop. For bright-field inspection, the round number information is automatically incremented by 1 after all target cassettes with tail numbers between 0 and 9 are inspected consecutively. Similarly, for dark-field inspection, the round number information is updated after all wafer inspection cassettes with tail numbers between 0 and 4 or 5 and 9 are inspected and recorded.

[0044] In some other embodiments, when the round number information reaches a preset value, that is, when the number of cycles is reached, the sampling pass rate under various tests is obtained, and subsequent adjustments are determined based on the sampling pass rate and the cycle preset value.

[0045] When the inspection pass rate of wafers under bright field detection and / or dark field detection is less than the preset value, the number of wafers inspected under the corresponding inspection mechanism is increased, and the inspection pass rate is calculated for the wafers.

[0046] When the sampling pass rate of the above aspects is greater than the preset value, it means that the produced wafers meet the relevant tests. However, when the test results of the bright field test and / or dark field test are lower than the sampling pass rate, it means that the production accuracy of the batch is insufficient, or the data error is caused by accidental factors. The sampling mechanism should be appropriately changed, such as increasing the number of samplings. In one possible implementation, the number of bright field tests is set to twice the original number, that is, wafers in four different cavities are sampled separately. For dark field testing, two rows are also sampled, the sampling intensity is increased, and the samples are sent for inspection again to calculate the sampling pass rate. This ensures the accuracy of the data.

[0047] In summary, in the embodiment of the present application, the wafers in the wafer box are sorted and numbered according to the order of the cavities. During the extraction process, the corresponding sampling mechanism is determined according to the bit information of the target wafer box and the sampling items, and the target wafer is selected according to the corresponding first sampling mechanism or the second sampling mechanism. During the sampling process, whether it is bright field sampling or dark field sampling, the wafer number corresponding to the different cavities can be selected according to their response and speed; in addition, by recording the number of rounds for cyclic sampling, the detection coverage of bright field detection can be increased to 80%, and dark field detection can achieve full coverage. Compared with the fixed number sampling and random sampling of wafer boxes in the related art, the sampling coverage and efficiency can be improved.

[0048] The above describes the preferred embodiments of the present invention; it should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention that do not depart from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A wafer defect detection optimization method, characterized in that: The method comprises: Receive a target wafer box and obtain corresponding tail number information, where the tail number information is used to distinguish test batches, and the target wafer box contains wafers to be tested produced by various cavities; Determine the target detection item of the target wafer box, and randomly select the target wafers with corresponding numbers from the target wafer box according to the target detection item, the corresponding wafer random inspection mechanism, and the tail digit information; wherein different detection items correspond to different wafer random inspection mechanisms, and the wafer random inspection mechanism is used to determine and calculate the number and number of the wafers to be randomly inspected; when the target detection item is bright field detection, determine to use the first random inspection mechanism, and the first random inspection mechanism includes randomly inspecting at least two wafers to be tested from different production cavities from the target detection box according to a first random inspection formula; when the first random inspection mechanism selects two wafers to be tested, the first random inspection formula P(x) is expressed as follows: P(x)=(a,b|a=x+1,b=x+14,x≤4) P(x)=(a,b|a=x+2,b=x+16,x≥5) When the target detection item is dark field detection, the second sampling mechanism is determined to be used. The second sampling mechanism includes sampling n wafers to be tested from different production cavities from the target detection box according to a second sampling formula; wherein n is a positive integer not less than the number of machine cavities; when the second sampling mechanism selects 5 wafers to be tested, the second sampling formula P(x) is expressed as follows: P(x)=A(x+1,:),x≤4 P(x)=A(x-2,:),x≥5 Where P(x) represents the target wafer selected under the corresponding mantissa and extraction mechanism conditions, x represents the mantissa information of the target wafer box, a and b represent the two selected wafer numbers, and A(x+1,:) represents the selection of all wafers in the x+1th row of the target wafer box matrix, and the five wafers in the row are from all chamber production; Calculating the number of the target wafer based on the mantissa information and the first sampling formula or the second sampling formula, and selecting the corresponding target wafer; Defect detection is performed on the selected target wafer.

2. The method according to claim 1, characterized in that The target wafer box contains 25 wafers to be tested, and is placed and numbered in a horizontal order according to the number and sequence of cavities of the production machine; The target wafer boxes sent for inspection are sequentially encoded with the tail number information according to the inspection order, and the tail number information is sequentially all integers between 0 and 9.

3. The method according to claim 1, characterized in that The method further comprises: Obtaining round number information corresponding to the current target wafer box, the round number information is used to indicate the round number of detecting the target wafer number in the wafer box; when the target detection item is bright field detection, and the wafer detection box containing all the last digits between 0 and 9 is detected and recorded, updating the round number information; When the target inspection item is dark field inspection, and after wafer inspection boxes containing all tail numbers between 0 and 4 or 5 and 9 are continuously inspected and recorded, the round number information is updated.

4. The method according to claim 1, wherein The detection speed under bright field detection is lower than that under dark field detection.

5. The method according to any one of claims 1 to 4, characterized in that: The defect detection content includes at least one of chamber, slot effect, diffusion fork scratch and CMP micro-scratch.

6. A wafer defect detection optimization device, characterized in that: The device is used for wafer defect detection, and the device includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the wafer defect detection optimization method as described in any one of claims 1 to 5.

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