Floating ground voltage generating circuit

Abstract

The application discloses a floating ground voltage generating circuit, which comprises a power supply end, a bias circuit, an operational amplifier circuit, a fast response circuit and an output circuit, the bias circuit provides bias voltage and bias current for the operational amplifier circuit and the fast response circuit respectively, the bias circuit provides reference voltage for the operational amplifier circuit, and the fast response circuit is used for quickly adjusting the change of output voltage of the output circuit, so that the stable floating ground voltage is obtained. The application can effectively solve the problem of large deviation of the output floating ground voltage and improve the performance of the driving circuit.

Description

Technical Field

[0001] This invention relates to the field of drive circuit technology, and more specifically, to a floating ground voltage generating circuit. Background Technology

[0002] With the increasing localization of chip production, most electric vehicles, home appliances, new energy vehicles and renewable energy products have begun to gradually use specialized power semiconductor devices as switches. As a key component in switching power supply systems, the design of the drive circuit for power semiconductor devices is one of the key technologies in the power supply field.

[0003] Currently, power MOSFETs and IGBTs are widely used as power switches. As market demand shifts towards high-speed, high-voltage applications, isolated drive circuits can address these challenges. According to market research data, the market size is projected to exceed $2 billion by 2023, with a compound annual growth rate of approximately 6%. This indicates a rapid market growth and significant potential for isolated drive circuits.

[0004] Among them, the capacitor-isolated drive circuit is a type of isolated drive circuit. Because the insulating layer between the capacitor plates is made of a dielectric insulating material (such as silicon dioxide), this high-performance insulating material possesses very stable durability, reliability, and electromagnetic interference resistance, while also being able to withstand instantaneous high voltage. The distance, size, area, and insulating material of the capacitor plates in the capacitor-isolated drive circuit determine its electrical characteristics. The advantages of the capacitor-isolated drive circuit are high efficiency, excellent characteristics in terms of size, energy conversion, and resistance to electromagnetic interference and transient voltages. Furthermore, capacitor isolation has strong anti-interference capabilities and can operate in strong magnetic field environments. The excellent characteristics of capacitor isolation make it possible to realize low-cost, low-power integrated isolated drive circuits.

[0005] As a crucial component of capacitor-isolated drive circuits, the floating ground voltage generation circuit primarily generates a floating ground voltage that maintains a constant voltage difference from the power supply to drive the switching power transistor. For example... Figure 1 As shown, traditional floating ground voltage generation circuits mainly utilize the clamping principle of diodes to maintain a certain voltage difference between the power supply PVDD and the floating ground voltage FGND. Due to the large deviation of diodes with varying process angles, the voltage difference between the power supply PVDD and the floating ground voltage FGND varies greatly. A large voltage difference between the power supply PVDD and the floating ground voltage FGND can cause the gate-source VGS of the power transistor PMOS in the drive circuit to have withstand voltage problems. Conversely, a small voltage difference between the power supply PVDD and the floating ground voltage FGND can cause the drive current of the power transistor PMO in the drive circuit to be small, thus affecting the performance of the circuit system. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a floating ground voltage generation circuit that can effectively solve the problem of large deviation of the output floating ground voltage and improve the performance of the drive circuit.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A floating ground voltage generating circuit is characterized by comprising a power supply terminal, a bias circuit, an operational amplifier circuit, a fast response circuit, and an output circuit, wherein power is input to the bias circuit, the operational amplifier circuit, the fast response circuit, and the output circuit through the power supply terminal.

[0009] The bias circuit provides bias voltage and bias current for the operational amplifier circuit and the fast response circuit, respectively. The bias circuit has a reference voltage output terminal, which outputs a reference voltage.

[0010] The first input terminal of the operational amplifier circuit is connected to the reference voltage output terminal, so that the voltage output by the operational amplifier circuit is proportional to the reference voltage.

[0011] The output terminal of the operational amplifier circuit is connected to the input terminal of the fast response circuit, and the output terminal of the fast response circuit is connected to the adjustment input terminal of the output circuit. The floating ground voltage output terminal of the output circuit outputs a floating ground voltage with a fixed voltage difference from the power supply. The fast response circuit quickly adjusts the output voltage of the output circuit to obtain a stable floating ground voltage. Optionally, the output circuit has a feedback voltage output terminal, which outputs a feedback voltage and is connected to the second input terminal of the operational amplifier circuit.

[0012] Optionally, the output circuit obtains the floating ground voltage and feedback voltage by dividing the voltage using voltage divider resistors.

[0013] Optionally, the operational amplifier circuit and the fast response circuit can each replicate the bias current from the bias circuit via a common-source cascode current mirror circuit.

[0014] Optionally, the bias circuit includes transistors MP1, HVMP2, MP3, HVMN1, HVMN3, HVMN5, MN2, MN4, MN6, resistors R0, R1, R2, R3, capacitor C1, a reference current input terminal, a first bias voltage output terminal, and a second bias voltage output terminal.

[0015] The reference current input terminal is connected to the first terminal of resistor R0, the gate of transistor HVMN1, the gate of transistor HVMN3, and the gate of transistor HVMN5. The second terminal of resistor R0 is connected to the drain of transistor HVMN1, the gate of transistor MN2, the gate of transistor MN4, and the gate of transistor MN6. The source of transistor HVMN1 is connected to the drain of transistor MN2, and the source of transistor MN2 is grounded.

[0016] The source of transistor MN4 is grounded, the drain of transistor MN4 is connected to the source of transistor HVMN3, the drain of transistor HVMN3 is connected to the drain of transistor MP3; the gate of transistor MP3 is connected to the drain of transistor MP3, the source of transistor MP3 is connected to the first terminal of resistor R1, the gate of transistor HVMP2 and the second bias voltage output terminal, the second terminal of resistor R1 is connected to the drain of transistor HVMP2, the gate of transistor MP1 and the first bias voltage output terminal, the source of transistor HVMP2 is connected to the drain of transistor MP1, and the source of transistor MP1 is connected to the power supply terminal.

[0017] The source of transistor MN6 is grounded, the drain of transistor MN6 is connected to the source of transistor HVMN5, the drain of transistor HVMN5 is connected to the first terminal of resistor R3, the second terminal of resistor R3 is connected to the first terminal of resistor R2, the first terminal of capacitor C1 and the reference voltage output terminal, and the second terminal of resistor R2 and the second terminal of capacitor C1 are connected to the power supply terminal.

[0018] Optionally, the operational amplifier circuit includes transistors MP4, MP7, MP8, HVMP5, HVMP6, HVMP9, HVMP10, MN7, MN8, MN11, MN12, HVMN9, and HVMN10.

[0019] The gate of transistor HVMP5 is the first input terminal of the operational amplifier circuit. The source of transistor HVMP5 is connected to the drain of transistor MP4 and the source of transistor HVMP6. The drain of transistor HVMP5 is connected to the drain of transistor MN7. The gate of transistor MP4 is connected to the first bias voltage output terminal, and the source of transistor MP4 is connected to the power supply terminal. The gate of transistor HVMP6 is the second input terminal of the operational amplifier circuit. The drain of transistor HVMP6 is connected to the drain of transistor MN8. The gates of transistors MN7 and MN8 are connected to the external clamping voltage input terminal. The source of transistor MN7 is connected to the source of transistor HVMN9 and the drain of transistor MN11. The source of transistor MN8 is connected to the source of transistor HVMN10 and the drain of transistor MN12. Transistors MN11 and MN12... The gate of transistor MN11 is connected to the gate of transistor MN2, and the sources of transistors MN11 and MN12 are grounded; the gates of transistors HVMN9 and HVMN10 are connected to the gate of transistor HVMN1, and the drain of transistor HVMN9 is connected to the drain of transistor HVMP9; the drain of transistor HVMP9 is connected to the gates of transistors MP7 and MP8, the gates of transistors HVMP9 and HVMP10 are connected to the second bias voltage output terminal, the source of transistor HVMP9 is connected to the drain of transistor MP7, and the source of transistor MP7 is connected to the power supply terminal; the output terminal of the operational amplifier circuit is connected to the drains of transistors HVMN10 and HVMP10, the source of transistor HVMP10 is connected to the drain of transistor MP8, and the source of transistor MP8 is connected to the power supply terminal.

[0020] Optional, the fast response circuit includes transistor MP11, transistor HVMP12, transistor MN13, capacitor C2, resistor R7 and resistor R8;

[0021] The gate of transistor MN13 is connected to the output of the operational amplifier circuit, the source of transistor MN13 is connected to the first output of the fast response circuit, and the drain of transistor MN13 is connected to the drain of transistor MP11 and the source of transistor HVMP12. The first end of resistor R7 is connected to the drain of transistor MN13, the second end of resistor R7 is connected to the first end of capacitor C2, and the second end of capacitor C2 is connected to the gate of transistor MN13. The source of transistor MP11 is connected to the power supply terminal, the gate of transistor MP11 is connected to the first bias voltage output terminal, the gate of transistor HVMP12 is connected to the second bias voltage output terminal, and the drain of transistor HVMP12 is connected to the first end of resistor R8 and the second output of the fast response circuit. The second end of resistor R8 is grounded.

[0022] Optionally, the output circuit includes transistors HVMN14, HVMN15, MN16, diode D0, resistors R4, R5, R6, and VB_BOOT voltage output terminal;

[0023] The gate of transistor HVMN14 is connected to the second output terminal of the fast response circuit, the source of transistor HVMN14 is grounded, and the drain of transistor HVMN14 is connected to the positive terminal of diode D0, the first output terminal of the fast response circuit, the gate of transistor HVMN15, and the floating ground voltage output terminal. The second terminal of resistor R5 is connected to the first terminal of resistor R4 and the feedback voltage output terminal, which is connected to the second input terminal of the operational amplifier circuit. The second terminal of resistor R4 and the negative terminal of diode D0 are connected to the power supply terminal.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The voltage difference between the PVDD input voltage and the FGND output voltage of the power supply terminal of the present invention has small deviation under temperature, process and voltage changes.

[0026] 2. This invention forms a fast response path through a fast response circuit, which quickly adjusts the change of the output floating ground voltage and reduces the jitter of the floating ground voltage. When the external load of the circuit changes, it can quickly adjust the output floating ground voltage back to the steady state value. The floating ground voltage output terminal FGND has a fast transient response and can quickly adjust to the steady state value when the external load changes.

[0027] 3. This invention solves the problem of large output voltage deviation in traditional floating ground voltage generation circuits, which affects the gate-source VGS withstand voltage of the PMOS power transistor in the drive circuit and the small output pull-up current. It can effectively solve the problem of large output floating ground voltage deviation and improve the performance of the drive circuit. Attached Figure Description

[0028] Figure 1 This is a circuit diagram of a traditional floating ground voltage generation circuit.

[0029] Figure 2 This is a circuit diagram of the high-precision floating ground voltage generation circuit of the present invention;

[0030] Figure 3 The simulation results of the voltage difference (PVDD-FGND) between the power supply voltage and the floating ground voltage for a traditional floating ground voltage generation circuit under the voltage range of 7V to 25V, temperature range of -40℃ to 125℃, and all process angles are shown.

[0031] Figure 4The simulation results of the floating ground voltage generation circuit of this invention, under the voltage range of 7V to 25V, temperature range of -40℃ to 125℃, and all process angles, show the voltage difference (PVDD-FGND) between the power supply voltage and the floating ground voltage.

[0032] Figure 5 The figure shows a comparison of the simulation results of the high-precision floating ground voltage generation circuit of the present invention and the traditional floating ground voltage generation circuit in the drive circuit system.

[0033] Meaning of the labels in the attached diagram:

[0034] 1-Bias circuit; 2-Operational amplifier circuit; 3-Fast response circuit; 4-Output circuit. Detailed Implementation

[0035] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0036] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0037] The present invention will be further described below with reference to embodiments.

[0038] like Figure 2 The high-precision floating ground voltage generation circuit of this embodiment is shown, which includes a power supply terminal PVDD, a bias circuit 1, an operational amplifier circuit 2, a fast response circuit 3, and an output circuit 4. Power is input to the bias circuit 1, the operational amplifier circuit 2, the fast response circuit 3, and the output circuit 4 through the power supply terminal PVDD.

[0039] Bias circuit 1 provides bias voltage and bias current to operational amplifier circuit 2 and fast response circuit 3, respectively. Bias circuit 1 has a reference voltage output terminal VREF, which outputs a reference voltage. The first input terminal of operational amplifier circuit 2 is connected to the reference voltage output terminal VREF. Operational amplifier circuit 2 obtains the reference voltage from bias circuit 1, so that the voltage output by the output terminal of operational amplifier circuit 2 is proportional to the reference voltage. The output terminal of operational amplifier circuit 2 is connected to the input terminal of fast response circuit 3. The output terminal of fast response circuit 3 is connected to the adjustment input terminal of output circuit 4. The floating ground voltage output terminal FGND of output circuit 4 outputs a floating ground voltage with a fixed voltage difference from the power supply input terminal PVDD. The fast response circuit reflects the change in the voltage output by the output terminal of operational amplifier circuit 2 to output circuit 4 to adjust the floating ground voltage.

[0040] The output circuit 4 is provided with a feedback voltage output terminal STB1, which outputs a feedback voltage. The feedback voltage output terminal STB1 is connected to the second input terminal of the operational amplifier circuit 2.

[0041] The output circuit obtains the floating ground voltage and feedback voltage through voltage divider resistors.

[0042] The operational amplifier circuit and the fast response circuit replicate the bias current from the bias circuit through the common source cascode current mirror circuit.

[0043] like Figure 2 As shown, the specific circuit in this embodiment is as follows:

[0044] The bias circuit includes transistors MP1, HVMP2, MP3, HVMN1, HVMN3, HVMN5, MN2, MN4, MN6, resistors R0, R1, R2, R3, capacitor C1, reference current input terminal IREF, first bias voltage output terminal Vb1, and second bias voltage output terminal Vb2.

[0045] In operation, the reference current input terminal IEF is connected to an external circuit. A reference current is input from the external circuit to form a bias current. The reference current input terminal IEF is connected to the first terminal of resistor R0, the gate of transistor HVMN1, the gate of transistor HVMN3, and the gate of transistor HVMN5. The second terminal of resistor R0 is connected to the drain of transistor HVMN1, the gate of transistor MN2, the gate of transistor MN4, and the gate of transistor MN6. The source of transistor HVMN1 is connected to the drain of transistor MN2, and the source of transistor MN2 is grounded to GND. The source of transistor MN4 is grounded to GND, and the drain of transistor MN4 is connected to the source of transistor HVMN3. The drain of transistor HVMN3 is connected to the drain of transistor MP3. The gate of transistor MP3 is connected to the gate of transistor M... The drain of P3 and the source of transistor MP3 are connected to the first terminal of resistor R1, the gate of transistor HVMP2, and the second bias voltage output terminal Vb2. The second terminal of resistor R1 is connected to the drain of transistor HVMP2, the gate of transistor MP1, and the first bias voltage output terminal Vb1. The source of transistor HVMP2 is connected to the drain of transistor MP1. The source of transistor MP1 is connected to the power supply terminal PVDD. The source of transistor MN6 is grounded to GND. The drain of transistor MN6 is connected to the source of transistor HVMN5. The drain of transistor HVMN5 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the first terminal of resistor R2, the first terminal of capacitor C1, and the reference voltage output terminal VREF. The second terminals of resistor R2 and capacitor C1 are connected to the power supply terminal PVDD.

[0046] Operational amplifier circuit 2 is a folded operational amplifier circuit, which includes transistors MP4, MP7, MP8, HVMP5, HVMP6, HVMP9, HVMP10, MN7, MN8, MN11, MN12, HVMN9, and HVMN10.

[0047] The gate of transistor HVMP5 is the first input terminal of the operational amplifier circuit, connected to the reference voltage output terminal VREF to obtain the reference voltage from the bias circuit. The source of transistor HVMP5 is connected to the drain of transistor MP4 and the source of transistor HVMP6, and the drain of transistor HVMP5 is connected to the drain of transistor MN7. The gate of transistor MP4 is connected to the first bias voltage output terminal Vb1, and the source of transistor MP4 is connected to the power supply terminal PVDD. The gate of transistor HVMP6 is the second input terminal of the operational amplifier circuit, and the drain of transistor HVMP6 is connected to the drain of transistor MN8. The gates of transistors MN7 and MN8 are connected to the external clamping voltage input terminal Vdz, which is connected to an external voltage. The source of transistor MN7 is connected to the source of transistor HVMN9 and the drain of transistor MN11. The source of transistor MN8 is connected to the source of transistor HVMN10 and the drain of transistor MN12. The gates of transistors MN11 and MN12 are connected to... The gate of transistor MN2 is connected to the ground, and the sources of transistors MN11 and MN12 are grounded; the gates of transistors HVMN9 and HVMN10 are connected to the gate of transistor HVMN1, and the drain of transistor HVMN9 is connected to the drain of transistor HVMP9; the drain of transistor HVMP9 is connected to the gates of transistors MP7 and MP8, the gates of transistors HVMP9 and HVMP10 are connected to the second bias voltage output terminal Vb2, the source of transistor HVMP9 is connected to the drain of transistor MP7, and the source of transistor MP7 is connected to the power supply terminal PVDD; the output terminal of operational amplifier circuit 2 is connected to the drains of transistors HVMN10 and HVMP10, the source of transistor HVMP10 is connected to the drain of transistor MP8, and the source of transistor MP8 is connected to the power supply terminal PVDD.

[0048] The fast response circuit 3 includes transistor MP11, transistor HVMP12, transistor MN13, capacitor C2, resistor R7, and resistor R8.

[0049] The gate of transistor MN13 is connected to the output of the operational amplifier circuit, the source of transistor MN13 is connected to the first output of the fast response circuit, and the drain of transistor MN13 is connected to the drain of transistor MP11 and the source of transistor HVMP12. The first end of resistor R7 is connected to the drain of transistor MN13, the second end of resistor R7 is connected to the first end of capacitor C2, and the second end of capacitor C2 is connected to the gate of transistor MN13. The source of transistor MP11 is connected to the power supply terminal PVDD, the gate of transistor MP11 is connected to the first bias voltage output terminal Vb1, the gate of transistor HVMP12 is connected to the second bias voltage output terminal Vb2, the drain of transistor HVMP12 is connected to the first end of resistor R8 and the second output of the fast response circuit, and the second end of resistor R8 is grounded to GND.

[0050] Output circuit 4 includes transistor HVMN14, diode D0, resistor R4, resistor R5, and resistor R6;

[0051] The gate of transistor HVMN14 is connected to the second output terminal of the fast response circuit, the source of transistor HVMN14 is grounded to GND, and the drain of transistor HVMN14 is connected to the first terminal of resistor R5, the positive terminal of diode D0, the first output terminal of the fast response circuit, and the floating ground voltage output terminal FGND. The second terminal of resistor R5 is connected to the first terminal of resistor R4 and the feedback voltage output terminal STBI. The feedback voltage output terminal STBI is connected to the second input terminal of the operational amplifier circuit. The second terminal of resistor R4 and the negative terminal of diode D0 are connected to the power supply terminal PVDD.

[0052] This embodiment uses an operational amplifier circuit with deep negative feedback, so that its output voltage Vout is proportional to the reference voltage Vref, i.e., Vout=K*Vref, where K is the proportionality coefficient.

[0053] The working principle of the high-precision floating ground voltage generation circuit in this embodiment is as follows:

[0054] The bias circuit 1 mainly consists of a common-source cascode current mirror circuit, resistors, and capacitors. Transistors HVMN3 and MN4 form the common-source cascode current mirror circuit to replicate the current at the reference current input terminal IREF. Transistor MP3 is connected as a diode. By dividing the voltage across resistor R1, two bias voltages are obtained: the first bias voltage output terminal Vb1 and the second bias voltage output terminal Vb2. Transistors HVMN5 and MN6 also form the common-source cascode current mirror circuit to replicate the current at the reference current input terminal IREF. A voltage drop is generated between resistors R2 and R3, which serves as the reference voltage at the input terminal of operational amplifier circuit 2. The output reference voltage is 2.5V. Capacitor C1 is used to stabilize the reference voltage.

[0055] The first input terminal of operational amplifier circuit 2 is connected to the reference voltage output terminal VREF, and the second input terminal is connected to the feedback voltage output terminal STBI of output circuit 4. Operational amplifier circuit 2 operates in deep negative feedback, clamping the voltage of the feedback voltage output terminal STBI of output circuit 4 to 2.5V. Transistor MP4 is the tail current transistor of operational amplifier circuit 2, and transistors HVMP5 and HVMP6 are the input pair transistors of operational amplifier circuit 2. The voltage input at the external clamping voltage input terminal Vdz is 5.9V, clamping the gate voltage of transistors MN7 and MN8 to 5.9V to prevent transistors MN11 and MN12 from having a breakdown voltage risk. Transistors HVMN9, MN11, HVMN10, and MN12 are common-source cascode current mirror circuits, mirroring the current at the reference current input terminal IREF to provide current to operational amplifier circuit 2. Transistors MP7, HVMP9, MP8, and HVMP10 are the load transistors of operational amplifier circuit.

[0056] Fast response circuit 3 connects the gate of transistor MN13 to the output of operational amplifier circuit 2, and the drain of transistor MN13 is connected to the floating ground voltage output terminal FGND, forming a fast response path. This path allows for rapid adjustment of the floating ground voltage. Resistor R7 and capacitor C2 quickly respond to the phase curve of the output to obtain a more stable voltage. Transistors MP11 and HVMP12 mirror the branch currents of transistors MP1 and HVMP2. Output circuit 4 generates a fixed voltage, which is then divided by resistors R4 and R5 to obtain a floating ground voltage with a fixed voltage difference of 5V from the power supply terminal PVDD. Capacitor C2, resistor R7, transistors HVMN10, MN8, HVMP6, resistor R5, and transistor MN13 form a negative feedback loop. Transistors MN13, HVMN14, and HVMP12 form a fast response path, enabling rapid adjustment of the output floating ground voltage in response to changes in external load.

[0057] In this embodiment, the first input terminal of the operational amplifier circuit is connected to the reference voltage of the bias circuit, and the second input terminal is connected to the feedback voltage output terminal of the output circuit, forming a negative feedback loop to stabilize the output floating ground voltage. At the same time, it makes the floating ground voltage proportional to the reference voltage, resulting in an output floating ground voltage that is almost unaffected by temperature, process, or voltage.

[0058] The high-precision floating ground voltage generation circuit of this embodiment was designed and simulated using the Spectre process model. The simulation results of the traditional floating ground voltage generation circuit under the following conditions are as follows: temperature range -40 to 125°C, power supply voltage range 7V to 25V, and full process angle. Figure 3 As shown, the typical value is 5.14V, the maximum voltage is 6.29V, and the deviation from the typical value is 1.15V; the minimum voltage is 4.16V, and the deviation from the typical value is 0.98V.

[0059] The high-precision floating ground voltage generation circuit of this embodiment, under simulation results in the temperature range of -40 to 125°C, power supply voltage range of 7V to 25V, and across the entire process angle, is as follows: Figure 4 As shown, the typical value is 5.2V, the maximum voltage is 5.37V, and the deviation from the typical value is 0.17V; the minimum voltage is 5V, and the deviation from the typical value is 0.21V.

[0060] Under the conditions of 12V voltage, 27℃ temperature, process angle tt, and square wave signal period of 4µs, the simulation comparison results of the high-precision floating ground voltage generation circuit of this embodiment and the traditional floating ground voltage generation circuit in the drive circuit system are as follows: Figure 5 As shown, the black curve is the PPVDD-FGND voltage curve output by the floating ground voltage generation circuit, and the gray curve is the PPVDD-FGND output voltage curve of the circuit in this embodiment. It can be seen that the response speed of the high-precision floating ground voltage generation circuit in this embodiment is 441.77ns faster than that of the traditional floating ground voltage generation circuit.

[0061] As can be seen from the simulation results above, the voltage deviation of the high-precision floating ground voltage generation circuit in this embodiment is about 5 times smaller than that of the traditional floating ground voltage generation circuit under all process angles, which can effectively improve the accuracy of the floating ground voltage. In the simulation of the drive system, the high-precision floating ground voltage generation circuit in this embodiment has a faster response speed than the traditional floating ground voltage generation circuit, which enables the output floating ground voltage FGND to quickly return to the steady state value.

[0062] This embodiment Using high-voltage MOSFETs can effectively solve the circuit voltage withstand problem, and the supply voltage can be up to 30V.

[0063] The above embodiments of the present invention are not intended to limit the scope of protection of the present invention. The implementation of the present invention is not limited thereto. All other modifications, substitutions or alterations made to the above structure of the present invention based on the above content of the present invention, in accordance with ordinary technical knowledge and common practice in the field, without departing from the basic technical idea of ​​the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A floating ground voltage generating circuit, characterized in that: It includes a power supply terminal, a bias circuit, an operational amplifier circuit, a fast response circuit, and an output circuit. Power is input to the bias circuit, the operational amplifier circuit, the fast response circuit, and the output circuit through the power supply terminal. The bias circuit provides bias voltage and bias current to the operational amplifier circuit and the fast response circuit, respectively. The bias circuit is provided with a reference voltage output terminal, which outputs a reference voltage. The first input terminal of the operational amplifier circuit is connected to the reference voltage output terminal, so that the voltage output by the output terminal of the operational amplifier circuit is proportional to the reference voltage. The output terminal of the operational amplifier circuit is connected to the input terminal of the fast response circuit, and the output terminal of the fast response circuit is connected to the adjustment input terminal of the output circuit. The floating ground voltage output terminal of the output circuit outputs a floating ground voltage with a fixed voltage difference from the power supply. The fast response circuit reflects the change in the voltage output by the output terminal of the operational amplifier circuit to the output circuit to adjust the floating ground voltage. The operational amplifier circuit includes transistors MP4, MP7, MP8, HVMP5, HVMP6, HVMP9, HVMP10, MN7, MN8, MN11, MN12, HVMN9, and HVMN10. The gate of transistor HVMP5 is the first input terminal of the operational amplifier circuit. The source of transistor HVMP5 is connected to the drain of transistor MP4 and the source of transistor HVMP6. The drain of transistor HVMP5 is connected to the drain of transistor MN7. The gate of transistor MP4 is connected to the first bias voltage output terminal, and the source of transistor MP4 is connected to the power supply terminal; the gate of transistor HVMP6 is the second input terminal of the operational amplifier circuit, and the drain of transistor HVMP6 is connected to the drain of transistor MN8; the gates of transistors MN7 and MN8 are connected to the external clamping voltage input terminal; the source of transistor MN7 is connected to the source of transistor HVMN9 and the drain of transistor MN11. The source of transistor MN8 is connected to the source of transistor HVMN10 and the drain of transistor MN12; The gates of transistors MN11 and MN12 are connected to the gate of transistor MN2, and the sources of transistors MN11 and MN12 are grounded; the gates of transistors HVMN9 and HVMN10 are connected to the gate of transistor HVMN1, and the drain of transistor HVMN9 is connected to the drain of transistor HVMP9; the drain of transistor HVMP9 is connected to the gates of transistors MP7 and MP8, the gates of transistors HVMP9 and HVMP10 are connected to the second bias voltage output terminal, the source of transistor HVMP9 is connected to the drain of transistor MP7, and the source of transistor MP7 is connected to the power supply terminal; the output terminal of the operational amplifier circuit is connected to the drains of transistors HVMN10 and HVMP10, the source of transistor HVMP10 is connected to the drain of transistor MP8, and the source of transistor MP8 is connected to the power supply terminal; The fast response circuit includes transistor MP11, transistor HVMP12, transistor MN13, capacitor C2, resistor R7, and resistor R8. The gate of transistor MN13 is connected to the output terminal of the operational amplifier circuit, the source of transistor MN13 is connected to the first output terminal of the fast response circuit, and the drain of transistor MN13 is connected to the drain of transistor MP11 and the source of transistor HVMP12; the first end of resistor R7 is connected to the drain of transistor MN13, the second end of resistor R7 is connected to the first end of capacitor C2, and the second end of capacitor C2 is connected to the gate of transistor MN13. The source of transistor MP11 is connected to the power supply terminal, the gate of transistor MP11 is connected to the first bias voltage output terminal, the gate of transistor HVMP12 is connected to the second bias voltage output terminal, the drain of transistor HVMP12 is connected to the first terminal of resistor R8 and the second output terminal of the fast response circuit, and the second terminal of resistor R8 is grounded.

2. The floating ground voltage generating circuit according to claim 1, characterized in that: The output circuit is provided with a feedback voltage output terminal, which outputs a feedback voltage and is connected to the second input terminal of the operational amplifier circuit.

3. The floating ground voltage generating circuit according to claim 2, characterized in that: The output circuit obtains the floating ground voltage and the feedback voltage by dividing the voltage using a voltage divider resistor.

4. The floating ground voltage generating circuit according to claim 1, characterized in that: The operational amplifier circuit and the fast response circuit respectively replicate the bias current from the bias circuit through a common-source cascode current mirror circuit.

5. The floating ground voltage generating circuit according to claim 2, characterized in that: The bias circuit includes transistors MP1, HVMP2, MP3, HVMN1, HVMN3, HVMN5, MN2, MN4, MN6, resistors R0, R1, R2, R3, capacitor C1, a reference current input terminal, a first bias voltage output terminal, and a second bias voltage output terminal. The reference current input terminal is connected to the first terminal of resistor R0, the gate of transistor HVMN1, the gate of transistor HVMN3 and the gate of transistor HVMN5, the second terminal of resistor R0 is connected to the drain of transistor HVMN1, the gate of transistor MN2, the gate of transistor MN4 and the gate of transistor MN6, the source of transistor HVMN1 is connected to the drain of transistor MN2, and the source of transistor MN2 is grounded. The source of transistor MN4 is grounded, the drain of transistor MN4 is connected to the source of transistor HVMN3, and the drain of transistor HVMN3 is connected to the drain of transistor MP3. The gate of transistor MP3 is connected to the drain of transistor MP3. The source of transistor MP3 is connected to the first terminal of resistor R1, the gate of transistor HVMP2, and the second bias voltage output terminal. The second terminal of resistor R1 is connected to the drain of transistor HVMP2, the gate of transistor MP1, and the first bias voltage output terminal. The source of transistor HVMP2 is connected to the drain of transistor MP1. The source of transistor MP1 is connected to the power supply terminal. The source of transistor MN6 is grounded, the drain of transistor MN6 is connected to the source of transistor HVMN5, the drain of transistor HVMN5 is connected to the first end of resistor R3, the second end of resistor R3 is connected to the first end of resistor R2, the first end of capacitor C1 and the reference voltage output terminal, and the second end of resistor R2 and the second end of capacitor C1 are connected to the power supply terminal.

6. The floating ground voltage generating circuit according to claim 1, characterized in that: The output circuit includes transistor HVMN14, diode D0, resistor R4, and resistor R5; The gate of transistor HVMN14 is connected to the second output terminal of the fast response circuit, the source of transistor HVMN14 is grounded, and the drain of transistor HVMN14 is connected to the first terminal of resistor R5, the positive terminal of diode D0, the first output terminal of the fast response circuit, and the floating ground voltage output terminal. The second terminal of resistor R5 is connected to the first terminal of resistor R4 and the feedback voltage output terminal. The feedback voltage output terminal is connected to the second input terminal of the operational amplifier circuit. The second terminal of resistor R4 and the negative terminal of diode D0 are connected to the power supply terminal.

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