Radiation-hardened sensitive amplifier

Abstract

The application discloses a kind of anti-radiation sensitive amplifiers in the field of semiconductor integrated circuits, comprising: switch NMOS tube, first differential NMOS tube, second differential NMOS tube, first latch circuit module and second latch circuit module;The source stage of the switch NMOS tube is grounded, the drain of the switch NMOS tube, the source stage of the first differential NMOS tube and the source stage of the second differential NMOS tube are electrically connected, the gate of the first differential NMOS tube is accessed first input signal, the gate of the second differential NMOS tube is accessed second input signal;First input signal, second input signal are amplified by positive feedback by first latch circuit module and second latch circuit module;The gate of the switch NMOS tube, the gate of the first transmission gate NMOS tube, the gate of the second transmission gate NMOS tube and the precharge module access control signal SENSE;Ensure that sensitive amplifier precision, speed and power consumption performance are good under the premise, sensitive amplifier can withstand higher level of particle strike.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, and specifically relates to a sensitive amplifier. Background Technology

[0002] The specific function of a sensitive amplifier in a memory circuit is to sense the voltage difference between bit lines during the sensing phase, and then rapidly amplify this voltage difference during the amplification phase, outputting a pair of complementary full-swing levels to achieve fast reading of the stored value in the memory cell. As a key component in analog integrated circuits, existing designs of sensitive amplifiers focus primarily on improving their accuracy and speed. Accuracy refers to the smallest voltage difference that a sensitive amplifier can detect. The pursuit of this technical indicator is an inevitable result of the shrinking of CMOS process dimensions and the reduction of power supply voltage. The introduction of differential pair and latch structure designs has made significant contributions to improving accuracy.

[0003] High-energy particles in the space environment can strike sensitive amplifiers, causing single-event effects, which can even generate transient pulses at the struck nodes in the sensitive amplifier circuit. In severe cases, this effect can even alter the logic state of the circuit, disrupting the circuit function of the sensitive amplifier and posing a significant reliability threat to sensitive amplifier circuits used in aerospace applications. Summary of the Invention

[0004] The purpose of this invention is to provide a radiation-resistant sensitive amplifier that improves the particle impact resistance of the sensitive amplifier while ensuring good accuracy, speed and power consumption performance.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] The first aspect of the present invention provides a radiation-resistant sensitive amplifier, comprising: a switching NMOS transistor, a first differential NMOS transistor, a second differential NMOS transistor, a first latch circuit module, and a second latch circuit module; the source of the switching NMOS transistor is grounded, the drain of the switching NMOS transistor, the source of the first differential NMOS transistor, and the source of the second differential NMOS transistor are electrically connected, a first input signal is connected to the gate of the first differential NMOS transistor, and a second input signal is connected to the gate of the second differential NMOS transistor;

[0007] The drain of the first differential NMOS transistor, the first input terminal of the first latch circuit module, and the first input terminal of the second latch circuit module are electrically connected; the drain of the second differential NMOS transistor, the second input terminal of the first latch circuit module, and the second input terminal of the second latch circuit module are electrically connected.

[0008] The first output terminal of the precharge module and the first output terminal of the first latch circuit module are electrically connected to the drain of the first transmission gate NMOS transistor; the source of the first transmission gate NMOS transistor and the first output terminal of the second latch circuit module are electrically connected to the input terminal of the first output inverter; the output terminal of the first output inverter is used to output the first output signal.

[0009] The second output terminal of the precharge module and the second output terminal of the first latch circuit module are electrically connected to the drain of the second transmission gate NMOS transistor; the source of the second transmission gate NMOS transistor and the second output terminal of the second latch circuit module are electrically connected to the input terminal of the second output inverter; the output terminal of the second output inverter is used to output the second output signal.

[0010] The gates of the switching NMOS transistor, the first transmission gate NMOS transistor, the second transmission gate NMOS transistor, and the precharge module access control signal SENSE.

[0011] Preferably, the pre-charge module includes a first pre-charge PMOS transistor, a second pre-charge PMOS transistor, and an equalization PMOS transistor; the gates of the first pre-charge PMOS transistor, the second pre-charge PMOS transistor, and the equalization PMOS transistor are connected to a control signal SENSE; the sources of the first and second pre-charge PMOS transistors are connected to a power supply; the drain of the first pre-charge PMOS transistor is connected to the source of the equalization PMOS transistor and serves as the first output terminal of the pre-charge module; the drain of the second pre-charge PMOS transistor is connected to the drain of the equalization PMOS transistor and serves as the second output terminal of the pre-charge module.

[0012] Preferably, both the first output inverter and the second output inverter include an inverting PMOS transistor and an inverting NMOS transistor; the source of the inverting PMOS transistor is connected to a power supply; the gate of the inverting PMOS transistor is connected to the gate of the inverting NMOS transistor and serves as an input terminal; the drain of the inverting PMOS transistor is connected to the drain of the inverting NMOS transistor and serves as an output terminal; and the source of the inverting NMOS transistor is grounded.

[0013] Preferably, the first latch circuit module and the second latch circuit module include a first latch PMOS transistor, a first latch NMOS transistor, a second latch PMOS transistor and a second latch NMOS transistor; the source of the first latch PMOS transistor and the source of the second latch PMOS transistor are connected to a power supply.

[0014] The drain of the first latching PMOS transistor, the drain of the first latching NMOS transistor, the gate of the second latching PMOS transistor, and the gate of the second latching NMOS transistor are connected and serve as the first output terminal; the source of the first latching NMOS transistor serves as the first input terminal.

[0015] The drain of the second latching PMOS transistor, the drain of the second latching NMOS transistor, the gate of the first latching PMOS transistor, and the gate of the first latching NMOS transistor are connected and serve as the second output terminal; the source of the second latching NMOS transistor serves as the second input terminal.

[0016] Preferably, the control signal SENSE is divided into a high-level signal and a low-level signal; when the control signal SENSE is a low-level signal, the first pre-charge PMOS transistor, the second pre-charge PMOS transistor, and the equalization PMOS transistor are in the on state, and the switching NMOS transistor, the first transmission gate NMOS transistor, and the second transmission gate NMOS transistor are in the off state; when the control signal SENSE is a high-level signal, the first pre-charge PMOS transistor, the second pre-charge PMOS transistor, and the equalization PMOS transistor are in the off state, and the switching NMOS transistor, the first transmission gate NMOS transistor, and the second transmission gate NMOS transistor are in the on state.

[0017] A second aspect of the present invention provides a central processing unit, characterized in that it includes the aforementioned sensitive amplifier.

[0018] A third aspect of the present invention provides an electronic device, characterized in that it includes the aforementioned central processing unit.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] The present invention provides a first latch circuit module and a second latch circuit module within the sensitive amplifier. When the first latch circuit module is hit by a particle, the second latch circuit module can still maintain the correct output. The correct output of the sensitive amplifier is ensured by the first transmission gate NMOS transistor and the second transmission gate NMOS transistor. Under the premise of ensuring good accuracy, speed and power consumption performance of the sensitive amplifier, the ability of the sensitive amplifier to withstand particle impact is improved. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a radiation-resistant sensitive amplifier provided in Embodiment 1 of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0023] Example 1

[0024] like Figure 1As shown, the first aspect of the present invention provides a radiation-resistant sensitive amplifier, comprising: a switching NMOS transistor NM5, a first differential NMOS transistor NM6, a second differential NMOS transistor NM7, a first latch circuit module SC1, and a second latch circuit module SC2; the source of the switching NMOS transistor NM5 is grounded, the drain of the switching NMOS transistor NM5, the source of the first differential NMOS transistor NM6, and the source of the second differential NMOS transistor NM7 are electrically connected, a first input signal is connected to the gate of the first differential NMOS transistor NM6, and a second input signal is connected to the gate of the second differential NMOS transistor NM7;

[0025] The drain of the first differential NMOS transistor NM6, the first input terminal of the first latch circuit module SC1, and the first input terminal of the second latch circuit module SC2 are electrically connected; the drain of the second differential NMOS transistor NM7, the second input terminal of the first latch circuit module SC1, and the second input terminal of the second latch circuit module SC2 are electrically connected.

[0026] The first output terminal of the precharge module and the first output terminal of the first latch circuit module SC1 are electrically connected to the drain of the first transmission gate NMOS transistor NM3; the source of the first transmission gate NMOS transistor NM3 and the first output terminal of the second latch circuit module SC2 are electrically connected to the input terminal of the first output inverter; the output terminal of the first output inverter is used to output the first output signal.

[0027] The second output terminal of the precharge module and the second output terminal of the first latch circuit module SC1 are electrically connected to the drain of the second transmission gate NMOS transistor NM4; the source of the second transmission gate NMOS transistor NM4 and the second output terminal of the second latch circuit module SC2 are electrically connected to the input terminal of the second output inverter; the output terminal of the second output inverter is used to output the second output signal.

[0028] The gate of the switching NMOS transistor NM5, the gate of the first transmission gate NMOS transistor NM6, the gate of the second transmission gate NMOS transistor NM7, and the precharge module access control signal SENSE.

[0029] The pre-charge module includes a first pre-charge PMOS transistor PM1, a second pre-charge PMOS transistor PM2, and an equalizing PMOS transistor PM3; the gates of the first pre-charge PMOS transistor PM1, the second pre-charge PMOS transistor PM2, and the equalizing PMOS transistor PM3 are connected to the control signal SENSE; the sources of the first pre-charge PMOS transistor PM1 and the second pre-charge PMOS transistor PM2 are connected to the power supply VDD; the drain of the first pre-charge PMOS transistor PM1 is connected to the source of the equalizing PMOS transistor PM3 and serves as the first output terminal of the pre-charge module; the drain of the second pre-charge PMOS transistor PM2 is connected to the drain of the equalizing PMOS transistor PM3 and serves as the second output terminal of the pre-charge module.

[0030] Both the first and second output inverters include an inverting PMOS transistor PM6 and an inverting NMOS transistor NM8; the source of the inverting PMOS transistor PM6 is connected to the power supply; the gate of the inverting PMOS transistor PM6 is connected to the gate of the inverting NMOS transistor NM8 and serves as the input terminal; the drain of the inverting PMOS transistor PM6 is connected to the drain of the inverting NMOS transistor NM8 and serves as the output terminal; the source of the inverting NMOS transistor NM8 is grounded.

[0031] The first latch circuit module SC1 and the second latch circuit module SC2 include a first latch PMOS transistor PM4, a first latch NMOS transistor NM1, a second latch PMOS transistor PM5, and a second latch NMOS transistor NM2; the source of the first latch PMOS transistor PM4 and the source of the second latch PMOS transistor PM5 are connected to the power supply; the first latch PMOS transistor PM4 and the first latch NMOS transistor NM1 form a left-side inverter; the second latch PMOS transistor PM5 and the second latch NMOS transistor NM2 form a right-side inverter;

[0032] The drain of the first latching PMOS transistor PM4, the drain of the first latching NMOS transistor NM1, the gate of the second latching PMOS transistor PM5, and the gate of the second latching NMOS transistor NM2 are connected and serve as the first output terminal; the source of the first latching NMOS transistor NM1 serves as the first input terminal.

[0033] The drain of the second latching PMOS transistor PM5, the drain of the second latching NMOS transistor NM2, the gate of the first latching PMOS transistor PM4, and the gate of the first latching NMOS transistor NM1 are connected and serve as the second output terminal; the source of the second latching NMOS transistor NM2 serves as the second input terminal.

[0034] The control signal SENSE is divided into a high-level signal and a low-level signal. When the control signal SENSE is a low-level signal, the first pre-charge PMOS transistor PM1, the second pre-charge PMOS transistor PM2, and the equalization PMOS transistor PM3 are in the on state, and the switching NMOS transistor NM5, the first transmission gate NMOS transistor NM3, and the second transmission gate NMOS transistor NM4 are in the off state. When the control signal SENSE is a high-level signal, the first pre-charge PMOS transistor PM1, the second pre-charge PMOS transistor PM2, and the equalization PMOS transistor PM3 are in the off state, and the switching NMOS transistor NM5, the first transmission gate NMOS transistor NM3, and the second transmission gate NMOS transistor NM4 are in the on state.

[0035] During normal operation: The sensitive amplifier circuit goes through two phases: a pre-charge phase and an amplification phase. When the control signal SENSE is low, the sensitive amplifier circuit is in the pre-charge phase; when the control signal SENSE jumps to high, the sensitive amplifier circuit enters the amplification phase. The specific workflow is as follows:

[0036] The control signal SENSE is initially low, turning on the first pre-charge PMOS transistor PM1, the second pre-charge PMOS transistor PM2, and the equalizing PMOS transistor PM3. A path exists from the power supply VDD to the first output terminal A and the second output terminal B of the first latch circuit module, thus charging both output terminals A and B to the same intermediate level. Simultaneously, the low-level SENSE signal turns off the switching NMOS transistor NM5, the first transmission gate NMOS transistor NM3, and the second transmission gate NMOS transistor NM4. Since the drain of the switching NMOS transistor NM5 is connected to the source terminals of the first differential NMOS transistor NM6 and the second differential NMOS transistor NM7, the first and second differential NMOS transistors cannot operate normally in the saturation region. This further causes the two latch circuit modules used for signal amplification to malfunction. Therefore, the outputs OUTL and OUTR of the sensitive amplifier remain in their initial states at this time.

[0037] During the amplification phase, the control signal SENSE transitions to a high level, and the first pre-charge PMOS transistor PM1, the second pre-charge PMOS transistor PM2, and the equalization PMOS transistor PM3 are in the off state, while the switching NMOS transistor NM5, the first transmission gate NMOS transistor NM3, and the second transmission gate NMOS transistor NM4 are in the on state. The voltage of the first input signal is input to the sensitive amplifier circuit through the gate of the first differential NMOS transistor NM6, and the voltage of the second input signal is input to the sensitive amplifier circuit through the gate of the second differential NMOS transistor NM7.

[0038] The first differential NMOS transistor NM6 and the second differential NMOS transistor NM7 convert the gate-source voltage into drain currents in two branches. The drain currents of the two branches of the first differential NMOS transistor NM6 enter the first latch circuit module SC1 and the second latch circuit module SC2, respectively; similarly, the drain currents of the two branches of the second differential NMOS transistor NM7 enter the first latch circuit module SC1 and the second latch circuit module SC2, respectively. Due to a slight voltage difference between the first and second input signals, the drain currents of the first differential NMOS transistor NM6 and the second differential NMOS transistor NM7 are slightly different. These differences are continuously amplified by positive feedback through the first latch circuit module SC1 and the second latch circuit module SC2, ultimately resulting in an amplified voltage at the output of the latch structure, which outputs a pair of complementary levels with opposite logic values. Because there are two sets of latch circuit modules, the complementary signal "01" is output through the first output terminal A and the second output terminal B after amplification by the first latch circuit module SC1; and another pair of complementary signals "01" is output through the first output terminal C and the second output terminal D after amplification by the second latch circuit module SC2.

[0039] The sensitive phase of the amplifier is the amplification phase, while the pre-charge phase is less affected. This is because the amplifier's output during the amplification phase is the target output, crucial for its proper operation. Changes in the pre-charge phase output have a relatively small impact on the final output. Furthermore, the sensitive nodes in the amplifier circuit are the first output terminal A and the second output terminal B. These terminals connect to the latch circuit module, determining the amplifier's core function, and also form a path with the output inverter, making them critical paths in the output circuit. Therefore, a pulse or logic flip generated at these points after a particle impact can have a fatal impact on the entire amplifier's functionality.

[0040] When the sensitive amplifier is operating in the amplification stage, assuming that the voltage of the first input signal is slightly higher than the voltage of the second input signal, after voltage-to-current conversion by the first differential NMOS transistor NM6 and the second differential NMOS transistor NM7, the drain current through the first differential NMOS transistor NM6 is slightly higher than the drain current through the second differential NMOS transistor NM7. When the amplified current passes through the first output terminal A and the second output terminal B, since the current entering the second output inverter is slightly greater than the current entering the first output inverter, the output terminal of the second output inverter, i.e., the second output terminal B, receives a voltage that has been inverted and become a lower level, while the output terminal of the first output inverter, i.e., the first output terminal A, receives a voltage that has been inverted and become a higher level. The positive feedback function of the first output inverter and the second output inverter further amplifies the voltages of the first output terminal A and the second output terminal B in a cyclic amplification, i.e., the first output terminal A is at a high level and the second output terminal B is at a low level. At this time, the first latching NMOS transistor NM1 of the first latching circuit module SC1 is cut off, the first latching PMOS transistor PM4 is turned on, the second latching NMOS transistor NM2 is turned on, and the second latching PMOS transistor PM5 is cut off.

[0041] If a particle strikes the drain of the first latching NMOS transistor NM1 in the first latching circuit module SC1, the pull-down branch of the left inverter is turned on, and a negative pulse is generated at the first output terminal A, pulling the high level of the first output terminal A low. Simultaneously, the second latching circuit module SC2 maintains its correct output; that is, the current in the left branch of the second latching circuit module SC2 is output through the first output terminal C, and the current in the right branch of the second latching circuit module SC2 is output through the second output terminal D. After positive feedback amplification, the current is finally output as high and low levels at the first output terminal C and the second output terminal D, respectively.

[0042] The first output terminal A of the first latch circuit module SC1 and the first output terminal C of the second latch circuit module SC2 are respectively connected to the source and drain sides of the first transmission gate NMOS transistor NM3. The second output terminal B of the first latch circuit module SC1 and the second output terminal D of the second latch circuit module SC2 are respectively connected to the source and drain sides of the second transmission gate NMOS transistor NM4. The output signal of the second latch circuit module SC2 is directly output through the first and second output inverters. The output signal of the first latch circuit module SC1 first passes through the first or second transmission gate NMOS transistor NM3, and then through the first and second output inverters. In summary, negative disturbances at the first output terminal A will not affect the correct high-level output of the first output terminal C, ultimately enabling the sensitive amplifier output terminals OUTL and OUTR to correctly output 1 and 0.

[0043] Similarly, if a particle strikes the drain of the second latching PMOS transistor PM5 in the first latching circuit module SC1, the pull-up branch of the inverter on the right side is turned on, and a positive pulse is generated at the second output terminal B, raising the low level of the second output terminal B. At the same time, the second latching circuit module SC2 still maintains the correct output. That is, the current of the left branch of the second latching circuit module SC2 passes through the first output terminal C, and the current of the right branch of the second latching circuit module SC2 passes through the second output terminal D. After positive feedback amplification, the high and low levels are finally output at the first output terminal C and the second output terminal D, respectively. In summary, the positive disturbance at the second output terminal B will not affect the correct low level output of the second output terminal D, and finally the output terminals OUTL and OUTR of the sensitive amplifier can correctly output 1 and 0.

[0044] Example 2

[0045] A central processing unit, characterized in that it includes the aforementioned sensitive amplifier.

[0046] Example 3

[0047] An electronic device, characterized in that it includes the aforementioned central processing unit.

[0048] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0049] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0050] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0051] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0052] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A radiation-hardened sense amplifier characterized by, The application relates to a differential input circuit module, which comprises a switch NMOS tube, a first differential NMOS tube, a second differential NMOS tube, a first latch circuit module and a second latch circuit module; the source electrode of the switch NMOS tube is connected with ground; the drain electrode of the switch NMOS tube, the source electrode of the first differential NMOS tube and the source electrode of the second differential NMOS tube are electrically connected; the gate electrode of the first differential NMOS tube is connected with a first input signal; the gate electrode of the second differential NMOS tube is connected with a second input signal; the drain electrode of the first differential NMOS tube, the first input end of the first latch circuit module and the first input end of the second latch circuit module are electrically connected; the drain electrode of the second differential NMOS tube, the second input end of the first latch circuit module and the second input end of the second latch circuit module are electrically connected; the first output end of a precharge module and the first output end of the first latch circuit module are electrically connected with the drain electrode of a first transmission gate NMOS tube; the source electrode of the first transmission gate NMOS tube and the first output end of the second latch circuit module are electrically connected with the input end of a first output inverter; the output end of the first output inverter is used for outputting a first output signal; the second output end of the precharge module and the second output end of the first latch circuit module are electrically connected with the drain electrode of a second transmission gate NMOS tube; the source electrode of the second transmission gate NMOS tube and the second output end of the second latch circuit module are electrically connected with the input end of a second output inverter; the output end of the second output inverter is used for outputting a second output signal; the gate electrode of the switch NMOS tube, the gate electrode of the first transmission gate NMOS tube, the gate electrode of the second transmission gate NMOS tube and the precharge module are connected with a control signal SENSE; the precharge module comprises a first precharge PMOS tube, a second precharge PMOS tube and a balance PMOS tube; the gate electrode of the first precharge PMOS tube, the gate electrode of the second precharge PMOS tube and the gate electrode of the balance PMOS tube are connected with the control signal SENSE; the source electrode of the first precharge PMOS tube and the source electrode of the second precharge PMOS tube are connected with a power supply; the drain electrode of the first precharge PMOS tube and the source electrode of the balance PMOS tube are connected and used as the first output end of the precharge module; the drain electrode of the second precharge PMOS tube and the drain electrode of the balance PMOS tube are connected and used as the second output end of the precharge module; the first output inverter and the second output inverter each comprise an inverting PMOS tube and an inverting NMOS tube; the source electrode of the inverting PMOS tube is connected with the power supply; the gate electrode of the inverting PMOS tube and the gate electrode of the inverting NMOS tube are connected and used as the input end; the drain electrode of the inverting PMOS tube and the drain electrode of the inverting NMOS tube are connected and used as the output end; the source electrode of the inverting NMOS tube is connected with ground; the first latch circuit module and the second latch circuit module each comprise a first latch PMOS tube, a first latch NMOS tube, a second latch PMOS tube and a second latch NMOS tube; the source electrode of the first latch PMOS tube and the source electrode of the second latch PMOS tube are connected with the power supply; the gate electrode of the first latch PMOS tube and the gate electrode of the second latch PMOS tube are connected with a first input signal; the drain electrode of the first latch PMOS tube and the drain electrode of the second latch PMOS tube are electrically connected; the gate electrode of the first latch NMOS tube and the gate electrode of the second latch NMOS tube are electrically connected; the source electrode of the first latch NMOS tube and the source electrode of the second latch NMOS tube are connected with ground; the drain electrode of the first latch NMOS tube and the drain electrode of the second latch NMOS tube are electrically connected; the gate electrode of the first latch NMOS tube is connected with a second input signal; the gate electrode of the second latch NMOS tube is connected with a second output signal. ​ ​ ​ ​ ​ 2. A radiation-hardened sense amplifier as claimed in claim 1, characterized in that ​ 3. A radiation-hardened sense amplifier as claimed in claim 1, wherein, ​ 4. A radiation-hardened sense amplifier as claimed in claim 1, wherein, ​ The drain of the first latching PMOS, the drain of the first latching NMOS, the gate of the second latching PMOS and the gate of the second latching NMOS are connected and serve as a first output terminal; the source of the first latching NMOS serves as a first input terminal; The drain of the second latching PMOS, the drain of the second latching NMOS, the gate of the first latching PMOS and the gate of the first latching NMOS are connected and serve as a second output terminal; the source of the second latching NMOS serves as a second input terminal.

5. A radiation-hardened sense amplifier as claimed in claim 2, wherein, The control signal SENSE is divided into a high level signal and a low level signal; when the control signal SENSE is a low level signal, the first pre-charge PMOS, the second pre-charge PMOS and the equalization PMOS are in an open state, and the switch NMOS, the first transmission gate NMOS and the second transmission gate NMOS are in a closed state; when the control signal SENSE is a high level signal, the first pre-charge PMOS, the second pre-charge PMOS and the equalization PMOS are in a closed state, and the switch NMOS, the first transmission gate NMOS and the second transmission gate NMOS are in an open state.

6. A central processing unit, characterized by The sensitive amplifier comprises any one of claims 1 to 5.

7. An electronic device, comprising: The central processing unit comprises claim 6.

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