Latch circuit and method, and electronic equipment

Abstract

The present disclosure relates to a latch circuit, method, and electronic device, and relates to the field of integrated circuit technology. The latch circuit includes: a transmission module, a latch module, and a control module; wherein the transmission module is used to transmit an input signal to the latch module; the latch module is used to latch the input signal or output the input signal when the set signal or reset signal is at a low level; and the control module is used to control the transmission module and the latch module to prevent a current leakage path from forming when the set signal or the reset signal is at a high level. The present disclosure provides a method for reducing current leakage.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a latch circuit and method, and an electronic device. Background Art

[0002] A latch circuit is a logic element with memory function in digital circuits. It can temporarily store a signal to maintain a certain level state. For example, it can record the binary digital signals "0" and "1" in a digital circuit.

[0003] When the set signal or the reset signal is at a low level, the latch circuit can usually perform normal data transmission or latching; however, when the set signal or the reset signal is at a high level, the latch circuit often generates a current leakage path, resulting in power consumption.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure aims to provide a latch circuit, a latch method, and an electronic device, so as to provide a method for reducing current leakage.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a latch circuit is provided, comprising: a transmission module, a latch module and a control module; wherein,

[0008] The transmission module is used to transmit the input signal to the latch module;

[0009] The latch module is used to latch the input signal or output the input signal when the set signal or the reset signal is at a low level;

[0010] The control module is configured to control the transmission module and the latch module so that no current leakage path is formed when the set signal or the reset signal is at a high level.

[0011] In an exemplary embodiment of the present disclosure, the transmission module includes a first NMOS transistor and a first PMOS transistor arranged in parallel;

[0012] The first NMOS transistor is controlled by a first clock signal, and the first PMOS transistor is controlled by a second clock signal opposite to the first clock signal.

[0013] In an exemplary embodiment of the present disclosure, the control module is configured to change the first clock signal to shut down the transmission module.

[0014] In an exemplary embodiment of the present disclosure, the control module includes a first NOR gate and a first inverter; wherein,

[0015] The input end of the first NOR gate is connected to the reset signal, and the output end of the first NOR gate outputs the first clock signal;

[0016] The input end of the first inverter is connected to the output end of the first NOR gate, and the output end of the first inverter outputs the second clock signal.

[0017] In an exemplary embodiment of the present disclosure, the control module includes a second NOR gate and a second inverter; wherein,

[0018] The input end of the second NOR gate is connected to the set signal, and the output end of the second NOR gate outputs the first clock signal;

[0019] The input end of the second inverter is connected to the output end of the second NOR gate, and the output end of the second inverter outputs the second clock signal.

[0020] In an exemplary embodiment of the present disclosure, the control module is used to control the input signal to be a low level when the reset signal is a high level; or, when the set signal is a high level, control the input signal to be a high level, so that a current leakage path cannot be formed between the transmission module and the latch module.

[0021] In an exemplary embodiment of the present disclosure, the control module includes a third NOR gate and a third inverter; wherein,

[0022] The input end of the third NOR gate receives the reset signal, and the output end of the third NOR gate outputs the input signal;

[0023] The input end of the third inverter is connected to the output end of the third NOR gate, and the output end of the third inverter outputs an inverted data delayed transmission signal.

[0024] In an exemplary embodiment of the present disclosure, the control module includes a fourth NOR gate and a fourth inverter; wherein,

[0025] The input end of the fourth NOR gate is connected to the set signal, and the output end of the fourth NOR gate outputs the input signal;

[0026] The input end of the fourth inverter is connected to the output end of the fourth NOR gate, and the output end of the fourth inverter outputs an inverted data transmission signal.

[0027] In an exemplary embodiment of the present disclosure, the latch module includes a reset unit and a first latch unit; wherein,

[0028] The reset section includes a second NMOS transistor coupled between the first latch section and a terminal of a ground voltage, and receives the reset signal through a gate of the second NMOS transistor.

[0029] In an exemplary embodiment of the present disclosure, the first latch unit includes: a first enabling inverter, and a fifth inverter and a sixth inverter arranged in series; wherein,

[0030] The input terminal of the first enabling inverter is connected to the output terminal of the fifth inverter; the output terminal of the first enabling inverter is connected to the input terminal of the fifth inverter;

[0031] The second NMOS transistor is coupled to the input terminal of the fifth inverter;

[0032] The output end of the transmission module is connected to the input end of the fifth inverter.

[0033] In an exemplary embodiment of the present disclosure, the latch module includes a setting unit and a second latch unit; wherein,

[0034] The setting unit includes a second PMOS transistor coupled between a terminal of a power supply voltage and the second latch unit, and receives a signal obtained by inverting the set signal through a gate of the second PMOS transistor.

[0035] In an exemplary embodiment of the present disclosure, the second latch unit includes: a second enabling inverter, and a seventh inverter and an eighth inverter arranged in series; wherein,

[0036] The input terminal of the second enabling inverter is connected to the output terminal of the seventh inverter; the output terminal of the second enabling inverter is connected to the input terminal of the seventh inverter;

[0037] The second PMOS transistor is coupled to the input terminal of the seventh inverter;

[0038] The output end of the transmission module is connected to the input end of the seventh inverter.

[0039] According to a second aspect of the present disclosure, a latching method for a latch circuit is provided. The method is applied to a latch circuit, wherein the latch circuit includes: a transmission module, a latching module, and a control module; the method includes:

[0040] Transmitting the input signal to the latch module through the transmission module;

[0041] When the set signal or the reset signal is at a low level, latching the input signal or outputting the input signal through the latch module;

[0042] When the set signal or the reset signal is at a high level, the control module controls the transmission module and the latch module so that no current leakage path is formed.

[0043] In an exemplary embodiment of the present disclosure, controlling, by the control module, to prevent a current leakage path from being formed between the transmission module and the latch module includes:

[0044] The transmission module is turned off by the control module, so that no current leakage path is formed between the transmission module and the latch module.

[0045] In an exemplary embodiment of the present disclosure, the transmission module includes: a first NMOS transistor controlled by a first clock signal, a first PMOS transistor controlled by a second clock signal opposite to the first clock signal;

[0046] The controlling the transmission module and the latch module so that no current leakage path is formed includes: changing the first clock signal through the control module to shut down the transmission module.

[0047] In an exemplary embodiment of the present disclosure, the transmission module includes: a first NMOS transistor controlled by a first clock signal, a first PMOS transistor controlled by a second clock signal opposite to the first clock signal;

[0048] The controlling of the transmission module and the latch module so that no current leakage path is formed includes: controlling the input signal to be a low level when the reset signal is a high level; or controlling the input signal to be a high level when the set signal is a high level, so that no current leakage path is formed between the transmission module and the latch module.

[0049] According to a third aspect of the present disclosure, an electronic device is provided, comprising the latch circuit described above.

[0050] The technical solution provided by the present disclosure may have the following beneficial effects:

[0051] In the latch circuit provided in the exemplary embodiments of the present disclosure, when the set signal SET or the reset signal RST is at a low level, the latch circuit can normally latch the input signal and can also output the latched signal as needed. When the set signal SET or the reset signal RST is at a high level, the control module can prevent the formation of a current leakage path between the transmission module and the latch module, thereby preventing current leakage, reducing power consumption, and preventing functional failure of the latch circuit due to current leakage.

[0052] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0054] Figure 1 Schematically shows a structural diagram of a logic symbol of a latch according to an exemplary embodiment of the present disclosure;

[0055] Figure 2 Schematically shows a structural diagram of a logic symbol of another latch according to an exemplary embodiment of the present disclosure;

[0056] Figure 3 Schematically shows an architecture diagram of a latch circuit according to an exemplary embodiment of the present disclosure;

[0057] Figure 4 Schematically shows a structural diagram of a latch circuit according to an exemplary embodiment of the present disclosure;

[0058] Figure 5 Schematically shows Figure 4 A schematic structural diagram of a control module in the latch circuit shown;

[0059] Figure 6 Schematically shows Figure 4 A schematic structural diagram of another control module in the latch circuit shown;

[0060] Figure 7 Schematically shows a structural diagram of another latch circuit in an exemplary embodiment of the present disclosure;

[0061] Figure 8 Schematically shows Figure 7A schematic structural diagram of a control module in the latch circuit shown;

[0062] Figure 9 Schematically shows Figure 7 A schematic structural diagram of another control module in the latch circuit shown;

[0063] Figure 10 The flowchart schematically shows a latching method of a latch circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0065] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0066] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0067] A latch is a logic element with memory function. The state of its output end does not change with the state of the input end. The input state is only saved to the output when there is a latch signal and will not change until the next latch signal arrives.

[0068] Reference Figure 1 and Figure 2 The following diagram shows the logic symbols of two latches. Figure 1 and Figure 2As can be seen, both latches are D latches, and are controlled by two opposite clock signals CKT and CKB to latch an input signal D or output opposite signals Q and QB. The input signal D can be a digital signal, and the latches can be used to latch or output digital signals.

[0069] The difference is, Figure 1 The latch signal of the latch in is the reset signal RST. Figure 2 The latch signal of the latch in the example is the set signal SET. When the reset signal RST or the set signal SET is low, the latch or output function of the latch can operate normally; when the reset signal RST or the set signal SET is high, the output Q will be forced to output a low level.

[0070] However, a common problem with the above latch is that when the reset signal RST or the set signal SET is at a high level, the input signal D, as well as the clock signals CKT and CKB are uncertain, which may lead to a current leakage path in the latch, thereby causing current leakage, resulting in power consumption, and even causing the latch to fail.

[0071] Based on this, an exemplary embodiment of the present disclosure provides a latch circuit. Figure 3 The latch circuit 100 provided in the exemplary embodiment of the present disclosure may mainly include: a transmission module 110 , a latch module 120 and a control module 130 .

[0072] Specifically, the transmission module 110 can be used to transmit the input signal D to the latch module 120; the latch module 120 can be used to latch the input signal D or output the input signal D when the set signal SET or the reset signal RST is at a low level; the control module 130 can be used to control that no current leakage path is formed between the transmission module 110 and the latch module 120 when the set signal SET or the reset signal RST is at a high level.

[0073] According to the latch circuit provided above, when the set signal SET or the reset signal RST is at a low level, the latch circuit can normally latch the input signal and can also output the latched signal as needed. In particular, when the set signal SET or the reset signal RST is at a high level, the control module can prevent the formation of a current leakage path between the transmission module and the latch module, thereby preventing current leakage, reducing power consumption, and preventing functional failure of the latch circuit due to current leakage.

[0074] In an exemplary embodiment of the present disclosure, the control module 130 may control the transmission module 110 and the latch module 120 in a variety of ways to prevent a current leakage path from being formed between the control module 110 and the latch module 120. For example, when the set signal SET or the reset signal RST is at a high level, the transmission module 110 is turned off to avoid the formation of a current leakage path between the transmission module 110 and the latch module 120; or, when the reset signal RST is at a high level, the control input signal D is at a low level; when the set signal SET is at a high level, the control input signal D is at a high level, thereby also achieving the purpose of avoiding the formation of a current leakage path between the transmission module 110 and the latch module 120.

[0075] The following mainly takes the latch circuit controlled by the dual clock signals CKT and CKB as an example to explain in detail the internal structure and working principle of the latch circuit provided by the present disclosure. Other latch circuits controlled by single or multiple clock signals can be implemented similarly.

[0076] Implementation method one:

[0077] Reference Figure 4 and Figure 5 In the latch circuit provided in the exemplary embodiment of the present disclosure, the transmission module 110 includes a first NMOS transistor 111 and a first PMOS transistor 112 arranged in parallel; and the first NMOS transistor 111 is controlled by a first clock signal CKT, and the first PMOS transistor 112 is controlled by a second clock signal CKB that is opposite to the first clock signal CKT. The input signal D can be transmitted to the latch module 120 through the transmission module 110. Figure 4 In the embodiment, the latch module 120 connected to the transmission module 110 includes a reset unit 121 and a first latch unit. The first latch unit includes a first enabling inverter 122, and a fifth inverter 123 and a sixth inverter 124 arranged in series. The output of the sixth inverter 124 outputs the output signal Q of the latch circuit. The input of the first enabling inverter 122 is connected to the output of the fifth inverter 123; the output of the first enabling inverter 122 is connected to the input of the fifth inverter 123; that is, the first enabling inverter 122 is also connected in series with the fifth inverter 123.

[0078] Furthermore, the reset unit 121 primarily includes a second NMOS transistor coupled between the first latch unit and a ground voltage terminal, and receives a reset signal RST via the gate of the second NMOS transistor. Specifically, the second NMOS transistor is coupled between the input terminal of the fifth inverter 123 of the first latch unit and the ground voltage terminal. Typically, the reset signal RST has two logic level states: high and low.

[0079] For Figure 4In a latch circuit consisting solely of the transmission module 110 and the latch module 120, when the reset signal RST is low, the second NMOS transistor of the reset section 121 is off, and the circuit is blocked. Therefore, when the first clock signal CKT is high and the second clock signal CKB is low, because the output of the transmission module 110 is connected to the input of the fifth inverter 123, the input signal D can be directly transmitted through the transmission module 110 to the fifth inverter 123, and then from the fifth inverter 123 to the sixth inverter 124, ultimately providing the output signal Q of the sixth inverter 124, i.e., Q = D.

[0080] When the reset signal RST is low, the corresponding second NMOS transistor is in the off state. When the first clock signal CKT is low and the second clock signal CKB is high, the transmission module 110 is in the off state. In addition, since the first enable inverter 122, which is enabled by the first clock signal CKT and the second clock signal CKB, is in the on state when the first clock signal CKT is low and the second clock signal CKB is high, the latch module 120 is mainly used to latch and maintain the D value of the previous state, thereby achieving the purpose of latching the input signal D.

[0081] When the reset signal RST is at a high level, since the second NMOS transistor of the reset unit 121 is grounded, the output signal Q is directly forced to output a low level. However, since in this state, the value of the output signal Q is not affected by the input signal D, the input signal D, the first clock signal CKT, and the second clock signal CKB are uncertain. There is a possible situation: the input signal D is at a high level, the first clock signal CKT is at a high level, and the second clock signal CKB is at a low level. In this case, the transmission module 110 and the reset unit 121 will form the following situation: Figure 4 The current leakage path is shown by the dotted arrow. The input signal D input from the input end will leak along the current leakage path, resulting in power consumption and even causing the latch circuit to fail.

[0082] Therefore, in order to avoid the formation of the above-mentioned current leakage path, such as Figure 5As shown, the control module 130 provided in the exemplary embodiment of the present disclosure includes a first NOR gate 131 and a first inverter 132. The input of the first NOR gate 131 is connected to the reset signal RST. In addition, the input of the first NOR gate 131 can also be connected to another clock signal CLKB. After these two signals pass through the first NOR gate 131, the output of the first NOR gate 131 outputs the first clock signal CKT. The input of the first inverter 132 is connected to the output of the first NOR gate 131, and the output of the first inverter 132 outputs the second clock signal CKB.

[0083] from Figure 5 As can be seen from the circuit diagram of the control module 130 shown in FIG, when the reset signal RST is at a high level, the first NOR gate 131 will output a low level, that is, the first clock signal CKT is at a low level, and at the same time, the second clock signal CKB is at a high level. When the first clock signal CKT is at a low level and the second clock signal CKB is at a high level, the transmission module 110 will be in a closed state, that is, through Figure 5 The control module 130 shown can prevent a current leakage path from being formed between the transmission module 110 and the latch module 120 by shutting down the transmission module 110 , thereby preventing current leakage from occurring.

[0084] In addition, for Figure 4 and Figure 5 In the latch circuit formed by this circuit, when the reset signal RST is low and the clock signal CLKB is low, the two low levels pass through the first NOR gate 131 and output a high level. In this case, the first clock signal CKT is high and the second clock signal CKB is low. When the first clock signal CKT is high and the second clock signal CKB is low, the transmission module 110 is in the on state, and the first enable inverter 122 is in the off state. The latch module 120 can directly assign the input signal D to the output signal Q.

[0085] When the reset signal RST is low and the clock signal CLKB is high, both signals output a low level after passing through the first NOR gate 131. This means that the first clock signal CKT is low and the second clock signal CKB is high. When the first clock signal CKT is low and the second clock signal CKB is high, the transmission module 110 is in the off state. At this time, the first enable inverter 122 is in the on state, allowing the latch module 120 to latch the D value from the previous state, thereby latching the input signal D.

[0086] It can be seen from this that through Figure 4 and Figure 5The latch circuit thus formed can not only output the input signal D or latch the input signal D normally when the reset signal RST is at a low level, but can also turn off the transmission module 110 when the reset signal RST is at a high level to avoid the formation of a current leakage path, thereby achieving the purpose of avoiding current leakage and saving power consumption.

[0087] Implementation method 2:

[0088] for Figure 4 In order to solve the problem of the current leakage path between the transmission module 110 and the latch module 120 shown in FIG, the exemplary embodiment of the present disclosure further provides another control module, referring to FIG. Figure 6 The control module 130 includes a third NOR gate 601 and a third inverter 602. The input of the third NOR gate 601 is connected to a reset signal RST. Additionally, the input of the third NOR gate 601 can also be connected to another inverted data transmission signal DB. After these two signals pass through the third NOR gate 601, the output of the third NOR gate 601 outputs an input signal D for inputting into the transmission module 110. The input of the third inverter 602 is connected to the output of the third NOR gate 601, and the output of the third inverter 602 outputs an inverted data delay transmission signal DB_Delay.

[0089] from Figure 6 As shown in the circuit diagram of the control module 130, when the reset signal RST is high, the third NOR gate 601 outputs a low level. In other words, the input signal D is at the low level VSS. Even if the first clock signal CKT is high and the second clock signal CKB is low, the transmission module 110 is in the on state. Because the input signal D inputted by the transmission module 110 is at the low level VSS, no current leakage path is formed between the transmission module 110 and the reset unit 121. This prevents the formation of a current leakage path between the transmission module 110 and the latch module 120, thus also preventing current leakage.

[0090] In addition, for Figure 4 and Figure 6 When the reset signal RST is low and the inverted data transmission signal DB is low, the two low levels pass through the third NOR gate 601 and output a high level. This means that the input signal D is now high. Whether the latch module 120 directly assigns the input signal D to the output signal Q or latches the input signal D can be determined based on whether the transmission module 110 is in the on or off state.

[0091] When the reset signal RST is at a low level, if the inverted data transmission signal DB is at a high level, the two signals will output a low level after passing through the third NOR gate 601. That is, the input signal D is at a low level at this time. Whether the latch module 120 directly assigns the input signal D to the output signal Q or latches the input signal D can be determined based on whether the transmission module 110 is in the on state or the off state.

[0092] It can be seen from this that through Figure 4 and Figure 6 The latch circuit thus formed can not only output the input signal D normally or latch the input signal D when the reset signal RST is at a low level, but can also control the input signal D to be at a low level when the reset signal RST is at a high level, thereby avoiding the formation of a current leakage path, thereby achieving the purpose of avoiding current leakage and saving power consumption.

[0093] Implementation method three:

[0094] Reference Figure 7 and Figure 8 In the latch circuit provided in the exemplary embodiment of the present disclosure, the transmission module 110 includes a first NMOS transistor 111 and a first PMOS transistor 112 arranged in parallel; and the first NMOS transistor 111 is controlled by a first clock signal CKT, and the first PMOS transistor 112 is controlled by a second clock signal CKB that is opposite to the first clock signal CKT. The input signal D can be transmitted to the latch module 120 through the transmission module 110. Figure 7 In the embodiment, the latch module 120 connected to the transmission module 110 includes a setting unit 710 and a second latch unit. The second latch unit includes a second enabling inverter 720, and a seventh inverter 730 and an eighth inverter 740 arranged in series. The output of the eighth inverter 740 outputs the output signal Q of the latch circuit. The input of the second enabling inverter 720 is connected to the output of the seventh inverter 730; the output of the second enabling inverter 720 is connected to the input of the seventh inverter 730; that is, the second enabling inverter 720 is also connected in series with the seventh inverter 730.

[0095] Furthermore, the set unit 710 primarily includes a second PMOS transistor 711 coupled between a power supply voltage terminal and a second latch unit. The gate of the second PMOS transistor 711 receives a signal that inverts the set signal SET. Specifically, a set signal inverter 712 is provided at the gate of the second PMOS transistor 711 to invert the set signal SET. The second PMOS transistor 711 is specifically coupled between the power supply voltage terminal and the input of a seventh inverter 730 in the second latch unit. Typically, the set signal SET has two logic level states: high and low.

[0096] For Figure 7 In a latch circuit consisting solely of the transmission module 110 and the latch module 120, when the set signal SET is low, the second PMOS transistor 711 of the set portion 710 is off, and the circuit is closed. Therefore, when the first clock signal CKT is high and the second clock signal CKB is low, because the output of the transmission module 110 is connected to the input of the seventh inverter 730, the input signal D can be directly transmitted through the transmission module 110 to the seventh inverter 730, and then from the seventh inverter 730 to the eighth inverter 740, ultimately resulting in the output signal Q of the eighth inverter 740, i.e., Q = D.

[0097] When the set signal SET is low, the corresponding second PMOS transistor 711 is in the off state. When the first clock signal CKT is low and the second clock signal CKB is high, the transmission module 110 is in the off state. In addition, since the second enable inverter 720, which is enabled by the first clock signal CKT and the second clock signal CKB, is in the on state when the first clock signal CKT is low and the second clock signal CKB is high, the latch module 120 is mainly used to latch and maintain the D value of the previous state, thereby achieving the purpose of latching the input signal D.

[0098] When the set signal SET is at a high level, since the second PMOS transistor 711 of the set unit 710 is connected to the power supply, the output signal Q is directly forced to output a high level. However, since in this state, the value of the output signal Q is not affected by the input signal D, the input signal D, the first clock signal CKT, and the second clock signal CKB are uncertain at this time. There is also a possible situation: that is, the input signal D is at a low level, the first clock signal CKT is at a high level, and the second clock signal CKB is at a low level. In this case, the transmission module 110 and the set unit 710 will form the following situation: Figure 7 The power signal may leak along the current leakage path indicated by the dotted arrow, thereby causing power consumption and even causing the latch circuit to malfunction.

[0099] Therefore, in order to avoid the formation of the above-mentioned current leakage path, such as Figure 8As shown, the control module 130 provided in the exemplary embodiment of the present disclosure includes a second NOR gate 801 and a second inverter 802. The input of the second NOR gate 801 is connected to the set signal SET. In addition, the input of the second NOR gate 801 can also be connected to another clock signal CLKB. After these two signals pass through the second NOR gate 801, the output of the second NOR gate 801 outputs the first clock signal CKT. The input of the second inverter 802 is connected to the output of the second NOR gate 801, and the output of the second inverter 802 outputs the second clock signal CKB.

[0100] from Figure 8 As can be seen from the circuit diagram of the control module 130 shown in FIG, when the set signal SET is at a high level, the second NOR gate 801 will output a low level, that is, the first clock signal CKT is at a low level, and the second clock signal CKB is at a high level. When the first clock signal CKT is at a low level and the second clock signal CKB is at a high level, the transmission module 110 will be in a closed state, that is, through Figure 8 The control module 130 shown can prevent a current leakage path from being formed between the transmission module 110 and the latch module 120 by shutting down the transmission module 110 , thereby preventing current leakage from occurring.

[0101] In addition, for Figure 7 and Figure 8 In the latch circuit, when the set signal SET is low, the set unit 710 is closed. If the clock signal CLKB is low, the two low levels pass through the second NOR gate 801 and output a high level. In this case, the first clock signal CKT is high and the second clock signal CKB is low. When the first clock signal CKT is high and the second clock signal CKB is low, the transmission module 110 is in the on state, and the second enable inverter 720 is in the off state. The latch module 120 can directly assign the input signal D to the output signal Q.

[0102] When the set signal SET is low, the set unit 710 is turned off. If the clock signal CLKB is high, these two signals will output a low level after passing through the second NOR gate 801. In this case, the first clock signal CKT is low and the second clock signal CKB is high. When the first clock signal CKT is low and the second clock signal CKB is high, the transmission module 110 is turned off. At this time, the second enable inverter 720 is turned on, and the latch module 120 can latch the D value of the previous state, thereby achieving the purpose of latching the input signal D.

[0103] It can be seen from this that through Figure 7 and Figure 8 The latch circuit thus formed can not only output the input signal D or latch the input signal D normally when the set signal SET is at a low level, but can also shut down the transmission module 110 when the set signal SET is at a high level to prevent the formation of a current leakage path, thereby achieving the purpose of preventing current leakage and saving power consumption.

[0104] Implementation method four:

[0105] for Figure 7 In order to solve the problem of the current leakage path between the transmission module 110 and the latch module 120 shown in FIG, the exemplary embodiment of the present disclosure further provides another control module, referring to FIG. Figure 9 The control module 130 includes a fourth NOR gate 901 and a fourth inverter 902. The input of the fourth NOR gate 901 is connected to a set signal SET. Additionally, the input of the fourth NOR gate 901 can also be connected to another signal DC, which can be the original input signal D. After these two signals pass through the fourth NOR gate 901, the output of the fourth NOR gate 901 outputs the modified input signal D through the fourth inverter 902 for input to the transmission module 110. The input of the fourth inverter 902 is connected to the output of the fourth NOR gate 901, and the output of the fourth inverter 902 outputs the inverted data transmission signal DB.

[0106] from Figure 9 As shown in the circuit diagram of the control module 130, when the set signal SET is high, the fourth NOR gate 901 outputs a low level. After passing through the fourth inverter 902, the input signal D becomes a high level VDD. Even if the first clock signal CKT is high and the second clock signal CKB is low, the transmission module 110 is in the on state. Because the input signal D inputted by the transmission module 110 is a high level VDD, no current leakage path is formed between the transmission module 110 and the set unit 710. This prevents the formation of a current leakage path between the transmission module 110 and the latch module 120, thus preventing current leakage.

[0107] In addition, for Figure 7 and Figure 9 In the latch circuit formed, when the set signal SET is at a low level, the set unit 710 is closed. If the signal DC is at a low level, the two low levels will output a high level after passing through the fourth NOR gate 901. After passing through the fourth inverter 902, the input signal D is now at a low level. Whether the latch module 120 directly assigns the input signal D to the output signal Q or latches the input signal D can be determined based on whether the transmission module 110 is in the on or off state.

[0108] When the set signal SET is low, the set unit 710 is closed. If the signal DC is high, the two signals will output a low level after passing through the fourth NOR gate 901. After passing through the fourth inverter 902, the input signal D is now high. Whether the latch module 120 directly assigns the input signal D to the output signal Q or latches the input signal D can be determined based on whether the transmission module 110 is in the on or off state.

[0109] It can be seen from this that through Figure 7 and Figure 9 The latch circuit thus formed can not only output the input signal D normally or latch the input signal D when the set signal SET is at a low level, but can also control the input signal D to be at a high level when the set signal SET is at a high level, thereby avoiding the formation of a current leakage path, thereby achieving the purpose of avoiding current leakage and saving power consumption.

[0110] In combination with the above four embodiments, it can be seen that the latch circuit provided by the exemplary embodiment of the present disclosure controls the input signal or clock signal that needs to be input through the control module, so that when the set signal or the reset signal is at a high level, a current leakage path cannot be formed between the control transmission module and the latch module, thereby avoiding current leakage in this case and achieving the purpose of saving power consumption; and, the input signal or clock signal processed by the control module can normally output the input signal D or latch the input signal D when the set signal or the reset signal is at a low level, without affecting the function of the latch circuit.

[0111] The exemplary embodiment of the present disclosure further provides a latching method of a latch circuit, which is applied to the latch circuit described above. The latch circuit includes: a transmission module, a latch module, and a control module. Figure 10 , the latching method may specifically include the following steps:

[0112] Step S102: transmitting the input signal to the latch module via the transmission module;

[0113] Step S104: when the set signal or the reset signal is at a low level, the input signal is latched or the input signal is output through the latch module;

[0114] Step S106 : When the set signal or the reset signal is at a high level, the control module controls the transmission module and the latch module so that no current leakage path is formed.

[0115] In some embodiments of the present disclosure, controlling the transmission module and the latch module so that no current leakage path is formed between the transmission module and the latch module by the control module includes: shutting down the transmission module by the control module so that no current leakage path is formed between the transmission module and the latch module.

[0116] In some embodiments of the present disclosure, the transmission module includes: a first NMOS transistor controlled by a first clock signal, and a first PMOS transistor controlled by a second clock signal opposite to the first clock signal; controlling the transmission module and the latch module so that no current leakage path is formed includes: changing the first clock signal through the control module to shut down the transmission module.

[0117] In some embodiments of the present disclosure, the transmission module includes: a first NMOS transistor controlled by a first clock signal, and a first PMOS transistor controlled by a second clock signal opposite to the first clock signal; controlling the transmission module and the latch module so that no current leakage path is formed includes: changing the input signal to a low level through the control module so that no current leakage path is formed between the transmission module and the latch module.

[0118] The specific details of each step in the latching method of the above latch circuit have been described in detail in the corresponding latch circuit, so they will not be repeated here.

[0119] The exemplary embodiments of the present disclosure further provide an electronic device, which may include the latch circuit described above, wherein the specific structure and working principle of the latch circuit have been described in detail in the above embodiments and will not be repeated here.

[0120] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that can be integrated with one or more media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)). In the embodiment of the present disclosure, the computer may include the device described above.

[0121] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the disclosure for which protection is sought, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. The fact that certain measures are recorded in mutually different dependent claims does not mean that these measures cannot be combined to produce good results.

[0122] Although the present disclosure has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely illustrative of the present disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such modifications and variations if they fall within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A latch circuit, characterized in that: include: Transmission module, latch module and control module; wherein, The transmission module is used to transmit the input signal to the latch module; The latch module is used to latch the input signal or output the input signal when the reset signal is at a low level; The control module is configured to control the transmission module and the latch module so that no current leakage path is formed when the reset signal is at a high level; The control module includes a first NOR gate and a first inverter; wherein, The input end of the first NOR gate is connected to the reset signal, and the output end of the first NOR gate outputs the first clock signal; The input end of the first inverter is connected to the output end of the first NOR gate, and the output end of the first inverter outputs a second clock signal.

2. A latch circuit, characterized in that: include: Transmission module, latch module and control module; wherein, The transmission module is used to transmit the input signal to the latch module; The latch module is used to latch the input signal or output the input signal when the reset signal is at a low level; The control module is configured to control the transmission module and the latch module so that no current leakage path is formed when the reset signal is at a high level; The control module includes a third NOR gate and a third inverter; wherein, The input end of the third NOR gate receives the reset signal, and the output end of the third NOR gate outputs the input signal; The input end of the third inverter is connected to the output end of the third NOR gate, and the output end of the third inverter outputs an inverted data delayed transmission signal.

3. The circuit according to claim 1 or 2, characterized in that The latch module includes a reset unit and a first latch unit; wherein, The reset section includes a second NMOS transistor coupled between the first latch section and a terminal of a ground voltage, and receives the reset signal through a gate of the second NMOS transistor.

4. The circuit according to claim 3, characterized in that The first latch unit includes: a first enabling inverter, and a fifth inverter and a sixth inverter arranged in series; wherein, The input terminal of the first enabling inverter is connected to the output terminal of the fifth inverter; the output terminal of the first enabling inverter is connected to the input terminal of the fifth inverter; The second NMOS transistor is coupled to the input terminal of the fifth inverter; The output end of the transmission module is connected to the input end of the fifth inverter.

5. A latch circuit, characterized in that: include: Transmission module, latch module and control module; wherein, The transmission module is used to transmit the input signal to the latch module; The latch module is used to latch the input signal or output the input signal when the set signal is at a low level; The control module is configured to control the transmission module and the latch module so that no current leakage path is formed when the set signal is at a high level; The control module includes a second NOR gate and a second inverter; wherein, The input end of the second NOR gate is connected to the set signal, and the output end of the second NOR gate outputs the first clock signal; The input end of the second inverter is connected to the output end of the second NOR gate, and the output end of the second inverter outputs a second clock signal.

6. A latch circuit, characterized in that: include: Transmission module, latch module and control module; wherein, The transmission module is used to transmit the input signal to the latch module; The latch module is used to latch the input signal or output the input signal when the set signal is at a low level; The control module is configured to control the transmission module and the latch module so that no current leakage path is formed when the set signal is at a high level; The control module includes a fourth NOR gate and a fourth inverter; wherein, The input end of the fourth NOR gate is connected to the set signal, and the output end of the fourth NOR gate outputs the input signal; The input end of the fourth inverter is connected to the output end of the fourth NOR gate, and the output end of the fourth inverter outputs an inverted data transmission signal.

7. The circuit according to claim 5 or 6, characterized in that The latch module includes a setting part and a second latch part; wherein, The setting unit includes a second PMOS transistor coupled between a terminal of a power supply voltage and the second latch unit, and receives a signal obtained by inverting the set signal through a gate of the second PMOS transistor.

8. The circuit according to claim 7, characterized in that The second latch unit includes: a second enabling inverter, and a seventh inverter and an eighth inverter arranged in series; wherein, The input terminal of the second enabling inverter is connected to the output terminal of the seventh inverter; the output terminal of the second enabling inverter is connected to the input terminal of the seventh inverter; The second PMOS transistor is coupled to the input terminal of the seventh inverter; The output end of the transmission module is connected to the input end of the seventh inverter.

9. The circuit according to any one of claims 1-2 or 5-6, characterized in that: The transmission module includes a first NMOS transistor and a first PMOS transistor arranged in parallel; The first NMOS transistor is controlled by a first clock signal, and the first PMOS transistor is controlled by a second clock signal opposite to the first clock signal.

10. The circuit according to claim 9, characterized in that The control module is used to change the first clock signal to shut down the transmission module.

11. The circuit according to any one of claims 1-2 or 5-6, characterized in that: The control module is used to control the input signal to be low when the reset signal is high; or to control the input signal to be high when the set signal is high, so that no current leakage path is formed between the transmission module and the latch module.

12. An electronic device, characterized in that: The method comprises the latch circuit according to any one of claims 1 to 11.

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