A clamping circuit and an electrostatic discharge protection circuit module

Abstract

The application discloses a clamping circuit and an electrostatic discharge protection circuit module, and the circuit comprises a detection module, an anti-mis-triggering module, a voltage pull-up module and a first transistor. The first end of the first transistor is grounded, the second end of the first transistor is connected with a target power supply, and the gate of the first transistor is connected with the output end of the pull-up module. The detection module is used for raising the voltage of the second end of the detection module when the voltage of the target power supply generates an electrostatic pulse. The anti-mis-triggering module is used for triggering the voltage pull-up module when the voltage of the second end of the detection module is greater than a voltage threshold. The voltage pull-up module is used for raising the gate voltage of the first transistor to the voltage of the target power supply when the voltage pull-up module is triggered by the anti-mis-triggering module, so that the first transistor is turned on. The gate voltage of the first transistor is raised by triggering the voltage pull-up module, so that the first transistor can adopt a transistor with a smaller volume, and the clamping circuit has a smaller volume and a lower cost.

Description

Technical Field

[0001] This application relates to the field of circuits, and more particularly to a clamping circuit and an electrostatic discharge protection circuit module. Background Technology

[0002] Clamping circuits are typically used to prevent damage to circuits caused by electrostatic discharge (ESD). ESD refers to a momentary high-voltage electrostatic pulse generated by a target power source. When this pulse flows through the functional circuit connected to the target power source, it damages the components, causing the circuit to malfunction. Clamping circuits suppress this high-voltage ESD pulse from the target power source, keeping its voltage below the clamping voltage and thus protecting the functional circuit.

[0003] To achieve better suppression and reduce the clamping voltage, current clamping circuits require transistors that release high-voltage electrostatic pulses to have high conduction capability. Therefore, larger transistors are typically used to release these pulses, resulting in larger clamping circuits and higher costs. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a clamping circuit that reduces the size and cost of the clamping circuit.

[0005] To achieve the above objectives, the technical solutions provided in this application are as follows:

[0006] This application provides a clamping circuit, including: a detection module, an anti-false triggering module, a voltage pull-up module, and a first transistor; the first terminal of the first transistor is grounded, the second terminal of the first transistor is connected to a target power supply, and the gate of the first transistor is connected to the output terminal of the pull-up module; the first terminal of the detection module is connected to the target power supply, and the second terminal of the detection module is connected to the input terminal of the anti-false triggering module; the detection module is used to increase the voltage of the second terminal of the detection module when an electrostatic pulse is generated at the voltage of the target power supply; the anti-false triggering module is used to trigger the voltage pull-up module when the voltage of the second terminal of the detection module is greater than a voltage threshold; the voltage pull-up module is used to increase the gate voltage of the first transistor to the voltage of the target power supply when triggered by the anti-false triggering module, so as to turn on the first transistor.

[0007] As one possible implementation, the voltage pull-up module includes: a second transistor, a third transistor, and a first resistor; the gate of the second transistor is connected to the output terminal of the anti-false triggering module, the source of the second transistor is grounded, and the drain of the second transistor is connected to the target power supply through the first resistor; the gate of the third transistor is connected to the drain of the second transistor, the source of the third transistor is connected to the target power supply, and the drain of the third transistor is connected to the gate of the first transistor.

[0008] As one possible implementation, the anti-false triggering module includes: a fourth transistor M4; the gate of the fourth transistor M4 is connected to the second terminal of a capacitor, the drain of the fourth transistor M4 is connected to a target power supply, and the source of the fourth transistor M4 is connected to the gate of a second transistor.

[0009] As one possible implementation, the anti-false triggering module further includes: a fifth transistor; the source of the fourth transistor M4 is connected to the gate of the fifth transistor; the drain of the fifth transistor is connected to the target power supply, and the source of the fifth transistor is connected to the gate of the second transistor.

[0010] In one possible implementation, the detection module includes a capacitor and a second resistor; the first end of the capacitor is connected to the target power supply, the first end of the second resistor is connected to the second end of the capacitor, and the second end of the second resistor is grounded.

[0011] In one possible implementation, the detection module includes a diode and a second resistor; the cathode of the diode is connected to the target power supply, the first end of the second resistor is connected to the anode of the diode, and the second end of the second resistor is grounded.

[0012] As one possible implementation, the voltage pull-up module also includes a third resistor; the first end of the third resistor is connected to the drain of the third transistor; the second end of the third resistor is grounded.

[0013] As one possible implementation, the anti-false triggering module further includes: a fourth resistor; the first end of the fourth resistor is connected to the source of the fourth transistor M4, and the second end of the fourth resistor is grounded.

[0014] As one possible implementation, the anti-false triggering module further includes: a fifth resistor; the first end of the fifth resistor is connected to the source of the fifth transistor, and the second end of the fifth resistor is grounded.

[0015] This application also provides an electrostatic discharge protection circuit module, which includes the clamping circuit described above.

[0016] As can be seen from the above technical solution, this application has the following beneficial effects:

[0017] This application provides a clamping circuit, including: a detection module, an anti-false triggering module, a voltage pull-up module, and a first transistor; the first terminal of the first transistor is grounded, the second terminal of the first transistor is connected to a target power supply, and the gate of the first transistor is connected to the output terminal of the pull-up module; the first terminal of the detection module is connected to the target power supply, and the second terminal of the detection module is connected to the input terminal of the anti-false triggering module; the detection module is used to increase the voltage of the second terminal of the detection module when an electrostatic pulse is generated at the voltage of the target power supply; the anti-false triggering module is used to trigger the voltage pull-up module when the voltage of the second terminal of the detection module is greater than a voltage threshold; the voltage pull-up module is used to increase the gate voltage of the first transistor to the voltage of the target power supply when triggered by the anti-false triggering module, so as to turn on the first transistor.

[0018] Therefore, the clamping circuit provided in this application embodiment can, on the one hand, prevent voltage fluctuations, glitches and ripples of the target power supply below the voltage threshold from triggering the first transistor through the anti-false triggering module, so that the voltage of the target power supply is too low and affects the normal operation of the functional circuit; on the other hand, by increasing the gate voltage of the first transistor through the trigger voltage pull-up module, the conduction capability of the first transistor can be increased, so that the first transistor can be a smaller transistor, thereby making the clamping circuit smaller and less expensive. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A circuit diagram of an anti-false triggering power clamping circuit provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram of a clamping circuit provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram of a clamping circuit provided in an embodiment of this application;

[0023] Figure 4 A schematic diagram of another clamping circuit provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of a clamping circuit provided in an embodiment of this application. Detailed Implementation

[0025] To help better understand the solutions provided in the embodiments of this application, before introducing the methods provided in the embodiments of this application, we will first introduce the application scenarios of the solutions in the embodiments of this application.

[0026] Electrostatic discharge (ESD) can occur on the pins of integrated circuits during the manufacturing, transportation, system integration, and user operation stages. ESD can generate instantaneous high-voltage electrostatic pulses that can flow through the chip's internal circuitry, causing damage and rendering it inoperable. In recent years, with the increasing integration of microelectronic devices and the narrowing of process linewidths, their resistance to ESD events has become increasingly weaker. With the rapid development of the integrated circuit industry in recent years, ESD events pose an ever-growing threat to increasingly smaller and more advanced chips. Therefore, research and upgrading of ESD protection are both necessary and urgent for safety and economic reasons.

[0027] For chip-level ESD protection, electrostatic discharge testing has different modes, each with its own corresponding ESD protection devices or circuits. Power clamping circuits primarily target ESD protection in power-to-ground mode. When the power and ground ports encounter ESD impacts, they provide a fast, low-resistance ESD discharge path for the chip, clamping the power supply voltage below the damage voltage of the internal circuitry, effectively protecting it from damage. Power clamping circuits include detection circuits that can distinguish between ESD pulses and normal operating pulses based on the pulse rise speed and magnitude, controlling whether the power clamping circuit is activated. Conventional power supply ports use DC voltage sources with minimal voltage fluctuations, keeping the power clamping circuit in the off state. However, some chips use high-voltage sources generated internally by low-voltage circuitry, which can be unstable, exhibiting glitches and significant ripple, potentially causing false triggering of the power clamping circuit and affecting normal circuit operation.

[0028] See Figure 1 The figure is a circuit diagram of an anti-false triggering power clamping circuit provided in an embodiment of this application.

[0029] like Figure 1 As shown, when an ESD pulse is applied to the power supply, the voltage at the node between resistor R1 and capacitor C1 will increase, causing transistors M1 and M2 to turn on successively. This causes the gate potential of clamping transistor M3 to increase. Clamping transistor M3 is a large-size transistor, and after it is turned on, it can release the electrostatic charge accumulated by the ESD pulse.

[0030] During normal power-on, the node voltage between capacitor C1 and resistor R1 is at ground potential, ensuring that the gates of transistors M1, M2, and M3 are at a low potential and the channels are off. Since the gate of transistor M2 is connected to the source of transistor M1, and the gate of transistor M3 is connected to the source of transistor M2, and each transistor in the preceding stage needs its gate voltage to be greater than its source voltage by at least one threshold voltage for it to conduct, the gate voltages of M1 / M2 / M3 decrease sequentially. To clamp transistor M3 to turn on, a power supply glitch of at least three times the threshold voltage is required. Therefore, this circuit has good resistance to power supply glitches and jitter.

[0031] However, to achieve better suppression and reduce the clamping voltage, the clamping circuit described above requires a high conduction capability of transistor M3. Therefore, transistor M3 typically needs to be a large transistor to release the high-voltage electrostatic pulse, resulting in a larger clamping circuit and higher cost.

[0032] To address the aforementioned technical problems, this application provides a clamping circuit, comprising: a detection module, an anti-false triggering module, a voltage pull-up module, and a first transistor; a first terminal of the first transistor is grounded, a second terminal of the first transistor is connected to a target power supply, and the gate of the first transistor is connected to the output terminal of the pull-up module; a first terminal of the detection module is connected to the target power supply, and a second terminal of the detection module is connected to the input terminal of the anti-false triggering module; the detection module is used to increase the voltage of the second terminal of the detection module when an electrostatic pulse is generated at the voltage of the target power supply; the anti-false triggering module is used to trigger the voltage pull-up module when the voltage of the second terminal of the detection module is greater than a voltage threshold; the voltage pull-up module is used to increase the gate voltage of the first transistor to the voltage of the target power supply when triggered by the anti-false triggering module, so as to turn on the first transistor.

[0033] Therefore, the clamping circuit provided in this application embodiment can increase the gate voltage of the first transistor to the voltage of the target power supply by triggering the voltage pull-up module, thereby increasing the conduction capability of the first transistor. This allows the first transistor to be a smaller transistor, which in turn makes the clamping circuit smaller and less expensive.

[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] See Figure 2 The figure is a schematic diagram of a clamping circuit provided in an embodiment of this application.

[0036] like Figure 2As shown, the clamping circuit provided in this application embodiment includes: a detection module 100, an anti-false triggering module 200, a voltage pull-up module 300, and a first transistor Q1; the first terminal of the first transistor Q1 is grounded, the second terminal of the first transistor Q1 is connected to the target power supply Ve, and the gate of the first transistor Q1 is connected to the output terminal of the pull-up module;

[0037] The first terminal of the detection module 100 is connected to the target power supply Ve, and the second terminal of the detection module 100 is connected to the input terminal of the anti-false triggering module 200; the detection module 100 is used to increase the voltage of the second terminal of the detection module 100 when the voltage of the target power supply Ve generates an electrostatic pulse.

[0038] The anti-false triggering module 200 is used to trigger the voltage pull-up module 300 when the voltage at the second terminal of the detection module 100 is greater than the voltage threshold.

[0039] The voltage pull-up module 300 is used to increase the gate voltage of the first transistor Q1 to the voltage of the target power supply Ve when it is triggered by the anti-false triggering module, so as to turn on the first transistor Q1.

[0040] It should be noted that the transistors in this embodiment can be either Insulated Gate Bipolar Transistors (IGBTs) or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and this embodiment is not limited thereto. The first transistor Q1 can be a P-type transistor or an N-type transistor. Specifically, when the first transistor Q1 is a P-type transistor, its source can be connected to the target power supply Ve, and its drain can be grounded. When the first transistor Q1 is an N-type transistor, its drain can be connected to the target power supply Ve, and its source can be grounded.

[0041] It should be noted that when a positive ESD pulse from the target power supply Ve to ground occurs, the voltage at the second terminal of the detection module 100 will rise to a voltage greater than the voltage threshold. Consequently, the anti-false triggering module 200 will quickly trigger the voltage pull-up module 300, which raises the gate voltage of the first transistor Q1 to the voltage of the target power supply Ve. This causes the first transistor Q1 to turn on, and the voltage of the target power supply Ve flows through the drain of the first transistor Q1 to the source of the first transistor, and then to ground, thereby reducing the voltage of the target power supply Ve and protecting the functional circuits connected to the power supply voltage from damage by the ESD pulse.

[0042] The clamping circuit provided in this application embodiment can, on the one hand, prevent voltage fluctuations, glitches, and ripples of the target power supply Ve below the voltage threshold from triggering the first transistor through the anti-false triggering module, thus avoiding the impact of excessively low voltage of the target power supply Ve on the normal operation of the functional circuit; on the other hand, by pulling the voltage of the trigger voltage up module to the voltage of the target power supply Ve, the gate voltage of the first transistor is increased, which can increase the conduction capability of the first transistor, thereby allowing the first transistor to be a smaller transistor, and thus making the clamping circuit smaller and less expensive.

[0043] To better understand the clamping circuit provided in the embodiments of this application, a specific example will be used to illustrate it below.

[0044] See Figure 3 The figure is a schematic diagram of a clamping circuit provided in an embodiment of this application.

[0045] like Figure 3 As shown, the voltage pull-up module includes: a second transistor Q2, a third transistor Q3, and a first resistor R1; the gate of the second transistor Q2 is connected to the output terminal of the anti-false triggering module, the source of the second transistor Q2 is grounded, and the drain of the second transistor Q2 is connected to the target power supply (power supply) Ve through the first resistor R1; the gate of the third transistor Q3 is connected to the drain of the second transistor Q2, the source of the third transistor Q3 is connected to the target power supply Ve, and the drain of the third transistor Q3 is connected to the gate of the first transistor Q1.

[0046] The anti-false triggering module in this embodiment includes: a fourth transistor Q4; the gate of the fourth transistor Q4 is connected to the second terminal of a capacitor, the drain of the fourth transistor Q4 is connected to the target power supply Ve, and the source of the fourth transistor Q4 is connected to the gate of the second transistor Q2. The anti-false triggering module in this embodiment may further include: a fifth transistor Q5; the source of the fourth transistor Q4 is connected to the gate of the fifth transistor Q5; the drain of the fifth transistor Q5 is connected to the target power supply Ve, and the source of the fifth transistor Q5 is connected to the gate of the second transistor Q2.

[0047] The detection module in this embodiment may further include a capacitor C1 and a second resistor R2; the first end of the capacitor C1 is connected to the target power supply Ve, the first end of the second resistor R2 is connected to the second end of the capacitor C1, and the second end of the second resistor R2 is grounded.

[0048] The voltage pull-up module in this embodiment further includes a third resistor R3; the first end of the third resistor R3 is connected to the drain of the third transistor Q3; the second end of the third resistor R3 is grounded. The anti-false triggering module in this embodiment further includes a fourth resistor R4; the first end of the fourth resistor R4 is connected to the source of the fourth transistor Q4, and the second end of the fourth resistor R4 is grounded. The anti-false triggering module in this embodiment further includes a fifth resistor R5; the first end of the fifth resistor R5 is connected to the source of the fifth transistor Q5, and the second end of the fifth resistor R5 is grounded.

[0049] It should be noted that when a positive ESD pulse occurs from the target power supply Ve to ground, the power supply voltage will instantly become high. Since the voltage across capacitor C1 cannot change abruptly, the output signal point V1 of the detection circuit will instantly rise to a high potential. This causes the gate potential of the fourth transistor Q4 in the trigger module to rise, and the gate-source voltage difference exceeds the threshold voltage, putting the fourth transistor Q4 in the on state. The on state of the fourth transistor Q4 also causes the gate potential of the fifth transistor Q5 to rise. When its gate-source voltage exceeds the threshold voltage, the fifth transistor Q5 will also be on. After the fifth transistor Q5 is on, it pulls up the gate of the second transistor Q2. When the gate-source voltage of this transistor exceeds the threshold voltage, the second transistor Q2 is on. After the second transistor Q2 is on, current flows through the series path between the first resistor R1 and the second transistor Q2. The voltage values ​​across the first resistor R1 are different, and V4 is lower than the power supply voltage. When the difference between V4 and the power supply voltage exceeds the threshold voltage of the third transistor Q3, the third transistor Q3 is on, pulling up the V5 node voltage to the power supply voltage potential. At this point, the gate voltage of the first transistor Q1 is pulled up to the power supply voltage potential, and the ESD current is discharged.

[0050] Since the gates of the fourth transistors Q4 / Q5 / Q2 are all connected to the source of the previous stage, and the conduction condition of the fourth transistors Q4 / Q5 / Q2 requires their gate-source voltage to be greater than the clamping voltage, the gate voltages of the three transistors decrease sequentially. The gate voltage of Q1 is one threshold voltage higher than the gate voltage of Q2, and the gate voltage of Q2 is one threshold voltage higher than the gate voltage of Q3. Only when the power supply glitches exceed three times the threshold voltage can the trigger module send a signal to the clamping module to conduct and discharge the ESD current. At the same time, due to the presence of the two subsequent stages of gate voltage pull-up circuits, the gate voltage of the clamping transistor Q5 is pulled up to the power supply voltage level, allowing the clamping transistor Q5 to open its channel to discharge the ESD current to the maximum extent, thereby obtaining a lower clamping voltage.

[0051] It should be noted that Figure 3This is merely an example provided for an embodiment of this application. In this embodiment, since the second transistor in the voltage pull-up module already has a certain ability to resist false triggering, the false triggering resistance module in this embodiment may not contain any transistors and only serve a connection function.

[0052] See Figure 4 This figure is a schematic diagram of another clamping circuit provided in an embodiment of this application.

[0053] like Figure 4 As shown, the anti-false triggering module 200 in this embodiment may include one transistor (Q4), two transistors (Q4 and Q5), or N transistors (N is a positive integer), and this embodiment does not limit the number of transistors. It should be noted that the threshold voltage of the anti-false triggering module 200 is determined by the number of transistors and their on-state voltages. Specifically, the threshold voltage of the false triggering module 200 is equal to the sum of the on-state voltages of the transistors in the anti-false triggering module 200. Therefore, increasing the number of transistors in the anti-false triggering module 200 can increase the circuit's anti-false triggering capability.

[0054] See Figure 5 The figure is a schematic diagram of a clamping circuit provided in an embodiment of this application.

[0055] like Figure 5 As shown, the detection module 100 in this embodiment may further include a diode P and a second resistor R2; the cathode of the diode is connected to the target power supply Ve (power supply), the first end of the second resistor R2 is connected to the anode of the diode, and the second end of the second resistor R2 is grounded. It should be noted that the function of the diode P in the detection module 100 is similar to the function of the capacitor C1 in the above embodiment, and will not be elaborated upon here. The diode P in this embodiment may include a single diode, or may be as follows: Figure 5 The embodiment shown includes N (N is a positive integer) diodes, but this embodiment is not limited to these.

[0056] In summary, the clamping circuit provided in this application embodiment can, on the one hand, prevent voltage fluctuations, glitches, and ripples of the target power supply below the voltage threshold from triggering the first transistor through the anti-false triggering module, thus preventing the low voltage of the target power supply from affecting the normal operation of the functional circuit; on the other hand, by increasing the gate voltage of the first transistor through the trigger voltage pull-up module, the conduction capability of the first transistor can be increased, thereby allowing the first transistor to be a smaller transistor, which in turn makes the clamping circuit smaller and less expensive.

[0057] Based on the clamping circuit provided in the above embodiments, this application embodiment can also provide an electrostatic discharge protection circuit module, which includes the clamping circuit in the above embodiments.

[0058] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROQ / RAQ, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0059] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the system section description.

[0060] It should also be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] The above description of the disclosed embodiments will enable those skilled in the art to make or use various modifications to these embodiments. It will be readily apparent to those skilled in the art that the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clamping circuit, characterized in that, include: The system includes a detection module, an anti-false triggering module, a voltage pull-up module, and a first transistor; the first terminal of the first transistor is grounded, the second terminal of the first transistor is connected to the target power supply, and the gate of the first transistor is connected to the output terminal of the pull-up module. The first end of the detection module is connected to the target power supply, and the second end of the detection module is connected to the input end of the anti-false triggering module; the detection module is used to increase the voltage of the second end of the detection module when the voltage of the target power supply generates an electrostatic pulse. The anti-false triggering module is used to trigger the voltage pull-up module when the voltage at the second terminal of the detection module is greater than the voltage threshold. The voltage pull-up module is used to increase the gate voltage of the first transistor to the voltage of the target power supply when triggered by the anti-false triggering module, so as to turn on the first transistor; The voltage pull-up module includes: a second transistor, a third transistor, and a first resistor; The gate of the second transistor is connected to the output terminal of the anti-false triggering module, the source of the second transistor is grounded, and the drain of the second transistor is connected to the target power supply through the first resistor; The gate of the third transistor is connected to the drain of the second transistor, the source of the third transistor is connected to the target power supply, and the drain of the third transistor is connected to the gate of the first transistor. The anti-false triggering module includes: a fourth transistor M4; The gate of the fourth transistor M4 is connected to the second terminal of the capacitor, the drain of the fourth transistor M4 is connected to the target power supply, and the source of the fourth transistor M4 is connected to the gate of the second transistor.

2. The circuit according to claim 1, characterized in that, The anti-false triggering module also includes: a fifth transistor; The source of the fourth transistor M4 is connected to the gate of the fifth transistor; the drain of the fifth transistor is connected to the target power supply, and the source of the fifth transistor is connected to the gate of the second transistor.

3. The circuit according to claim 1, characterized in that, The detection module includes a capacitor and a second resistor; The first terminal of the capacitor is connected to the target power supply, the first terminal of the second resistor is connected to the second terminal of the capacitor, and the second terminal of the second resistor is grounded.

4. The circuit according to claim 1, characterized in that, The detection module includes a diode and a second resistor; The cathode of the diode is connected to the target power supply, the first end of the second resistor is connected to the anode of the diode, and the second end of the second resistor is grounded.

5. The circuit according to claim 1, characterized in that, The voltage pull-up module also includes a third resistor; The first end of the third resistor is connected to the drain of the third transistor; the second end of the third resistor is grounded.

6. The circuit according to claim 1, characterized in that, The anti-false triggering module also includes: a fourth resistor; The first end of the fourth resistor is connected to the source of the fourth transistor M4, and the second end of the fourth resistor is grounded.

7. The circuit according to claim 2, characterized in that, The anti-false triggering module also includes: a fifth resistor; The first end of the fifth resistor is connected to the source of the fifth transistor, and the second end of the fifth resistor is grounded.

8. An electrostatic discharge protection circuit module, characterized in that, The electrostatic discharge protection circuit module includes the circuit described in any one of claims 1-7.

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