Light emitting device array

Abstract

A light emitting device array is provided. The light emitting device array includes a light emitting stack, a first electrical contact layer, a second electrical contact array, and an anti-reflective layer. The light emitting stack has a light emitting face and a contact face; the light emitting face and the contact face define opposite sides of the light emitting stack; the light emitting stack includes a plurality of Group III nitride layers including a first semiconductor layer disposed toward the light emitting face of the light emitting stack, a second semiconductor layer disposed toward the contact face, and an active layer arranged between the first semiconductor layer and the second semiconductor. The active layer is configured to generate light having a first wavelength. The light emitting face and the contact face are parallel to each other and aligned with the plurality of Group III nitride layers. The first electrical contact layer is disposed on the light emitting stack and is configured to be in electrical contact with the first semiconductor layer. The second electrical contact array is disposed on the contact face of the light emitting stack. Each second electrical contact defines a light emitting device between the first semiconductor layer and the second electrical contact. Each second electrical contact is spaced apart from other second electrical contacts to form a two-dimensional array of light emitting devices. The anti-reflective layer is disposed on the light emitting face. The anti-reflective layer is configured to increase light extraction efficiency of light generated by the light emitting stack.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an array comprising light emitting devices. In particular, the present disclosure relates to an array of light emitting devices comprising Group III nitride. BACKGROUND

[0002] Micro light emitting device arrays are generally defined as arrays of light emitting devices such as light emitting diodes (LEDs) having a size of 100 x 100 pm 2 or less. Micro LED arrays are self-emissive micro displays / projectors which can be suitable for a variety of devices such as smart watches, head-mounted displays, head-up displays, video cameras, viewfinders, multi-point excitation sources and pico-projectors.

[0003] One known form of micro LED array comprises a plurality of LEDs formed from Group III nitride. Group III nitride LEDs are inorganic semiconductor LEDs containing GaN and its alloys with InN and AlN in the active light emitting region. Group III nitride LEDs can be driven at significantly higher current densities and emit higher optical power densities than conventional large area LEDs, for example organic light emitting diodes (OLEDs) in which the light emitting layer is an organic compound. Higher luminance (brightness), defined as the amount of light emitted per unit area of a light source in a given direction, therefore makes micro LEDs suitable for applications requiring or benefiting from high brightness. For example, applications benefiting from high brightness can include displays or projectors in high brightness environments. Furthermore, Group III nitride micro LEDs are known to have a relatively high luminous efficiency, expressed in lumens per watt (lm / W), compared to other conventional large area LEDs. The relatively high luminous efficiency of Group III nitride micro LED arrays reduces power consumption compared to other light sources and makes micro LEDs particularly suitable for portable devices.

[0004] A micro LED is disclosed in US 2016365383. The micro LED comprises a parabolic mesa structure comprising an active layer configured to generate light. The surface of the mesa structure acts as a reflector such that a greater proportion of the generated light is directed to the opposing exit face at an angle of incidence less than the critical angle to the normal.

[0005] It is an object of the present invention to provide an improved array of light emitting devices which addresses at least one of the problems associated with prior art arrays of light emitting devices or at least provides a commercially useful alternative thereto. SUMMARY

[0006] The inventors have realized that the introduction of mesa structures into light emitting devices reduces the size of the active layer that generates light. Furthermore, the patterning of the array of light emitting devices and the formation of individual mesa structures requires the array to undergo a number of processing steps that have to be carefully aligned.

[0007] According to a first aspect of the present disclosure, there is provided a light emitting device array. The light emitting device array comprises a light emitting stack, a first electrical contact layer, a second electrical contact array and an anti-reflective layer. The light emitting stack has a light emitting face and a contact face. The light emitting face and the contact face define opposite sides of the light emitting stack, the light emitting stack comprising a plurality of Ill-nitride layers, the Ill-nitride layers comprising a first semiconductor layer disposed towards the light emitting face of the light emitting stack, a second semiconductor layer disposed towards the contact face, and an active layer arranged between the first semiconductor layer and the second semiconductor. The active layer is configured to generate light having a first wavelength. The light emitting face and the contact face are parallel to each other and aligned with the plurality of Ill-nitride layers. The first electrical contact layer is disposed on the light emitting stack and is configured to be in electrical contact with the first semiconductor layer. The second electrical contact array is disposed on the contact face of the light emitting stack. Each second electrical contact defines a light emitting device between the first semiconductor layer and the second electrical contact. Each second electrical contact is spaced apart from the other second electrical contacts to form a two-dimensional array of light emitting devices. The anti-reflective layer is disposed on the light emitting face. The anti-reflective layer is configured to increase the light extraction efficiency of light generated by the light emitting stack.

[0008] The light emitting device array of the first aspect has a light emitting device layer comprising the active layer. Each light emitting device is defined by the array of second electrical contacts on the contact face. The active layer region aligned with an individual second electrical contact can be switched on by the respective second electrical contact to emit light. The first electrical contact layer effectively forms a common first electrical contact for each light emitting device.

[0009] Light generated by the active layer is emitted in all directions within the light emitting stack. Since the light emitting face and the contact face of the light emitting stack are parallel, light that is incident on the light emitting face (or the contact face) at an angle greater than the critical angle is completely internally reflected within the light emitting stack. Likewise, only light that is incident on the light emitting face at an angle smaller than the critical angle is emitted from the device. Therefore, for each light emitting device, only light in a narrow angular range is transmitted through the light emitting face. Therefore, the array of light emitting devices can be provided using a (typically planar) light emitting stack that does not require a plurality of alignment steps to form light extraction features, such as mesa structures.

[0010] Even for light having an angle of incidence less than the critical angle, the interface at the light emitting surface is subject to reflection of light. In order to extract light from the light emitting surface, an anti-reflective layer is provided. The anti-reflective layer improves the light extraction efficiency of the light emitting surface.

[0011] As light is refracted at the light emitting surface, it is important to improve the light extraction efficiency of the light emitting surface. That is, light having an angle of incidence less than the critical angle is also refracted when transmitted from the light emitting stack to air. As the refractive index of Group III nitride is generally higher than that of air, the refraction serves to reduce the crosstalk that occurs between light emitting devices of the light emitting device array.

[0012] In some embodiments, the light emitting device array includes an absorption layer configured to absorb light of the first wavelength generated by the active layer; the absorption layer is disposed on at least a portion of the light emitting stack. The absorption layer is configured to absorb stray light generated by the active layer to improve the optical properties of the light emitting device array. The absorption layer can be disposed on various regions of the light emitting stack.

[0013] For example, the absorption layer can be disposed on at least one sidewall surface of the light emitting stack that extends between the light emitting surface and the contact surface. Thus, the absorption layer can be arranged to absorb light that is totally internally reflected between the light emitting surface and the contact surface once the light reaches the sidewall surface of the light emitting stack. In some embodiments, the absorption layer can be disposed on all sidewall surfaces of the light emitting stack.

[0014] In some embodiments, the absorption layer can be disposed on the light emitting surface. For example, in some embodiments, the absorption layer can be disposed around a perimeter of the light emitting surface. In some embodiments, the absorption layer can be disposed across the light emitting surface, where the absorption layer includes a plurality of openings on the light emitting surface, each opening aligned with a second electrical contact so that light of each light emitting device is transmitted through a respective opening. Likewise, the absorption layer can be disposed on the light emitting surface in a region between each light emitting device to reduce crosstalk between adjacent light emitting devices.

[0015] In some embodiments, the absorption layer is disposed on the contact surface, where the absorption layer is disposed in a region of the contact surface between adjacent second electrical contacts of the array of second electrical contacts. By disposing the absorption layer on the contact surface, light emitted from the active layer toward the contact surface can be absorbed by the absorption layer rather than potentially being reflected back toward the light emitting surface. Thus, the absorption layer can reduce crosstalk between adjacent light emitting devices.

[0016] In some embodiments, the first electrical contact layer is disposed on the light emitting surface. In some embodiments, the anti-reflective layer is disposed between the first electrical contact layer and the light emitting surface. For example, the anti-reflective layer can include a porous semiconductor layer, and the common first contact layer includes a transparent conductive oxide, such as Indium Tin Oxide (ITO).

[0017] In some embodiments, the first electrical contact layer is disposed between the light emitting surface and the anti-reflective layer. The anti-reflective layer can comprise Si02, while the first electrical contact layer comprises a transparent conductive oxide, such as indium tin oxide (ITO).

[0018] In some embodiments, the anti-reflective layer comprises a porous semiconductor layer having a surface porosity of at least 30%. For example, the porous semiconductor layer can comprise a Group III nitride layer. In some embodiments, the porous semiconductor layer can be formed from a Group III nitride semiconductor layer that has been subjected to a porosity treatment process. For example, in some embodiments, the porous semiconductor layer can be formed from the third semiconductor layer comprising an n-type doped Group III nitride. Increasing the surface porosity of a Group III nitride semiconductor layer can change the refractive index of the Group III nitride semiconductor layer (relative to the refractive index of the layer as formed), such that the porous semiconductor layer can be suitable for use as an anti-reflective layer. Of course, it will be appreciated that surface porosity is only one possible method of assessing the porosity of a porous semiconductor layer. Other methods of characterizing porosity, such as bulk porosity, can also be used to provide a porous semiconductor layer suitable for use as an anti-reflective layer.

[0019] In some embodiments, the pitch of each second electrical contact in the array of light emitting devices is no greater than 5 μιη or 2 μιη. Likewise, the center-to-center spacing of adjacent second electrical contacts is no greater than 5 μιη or 2 μιη. It will be appreciated that as the pitch of the array is reduced, the size of the active region of each light emitting device is also reduced. For devices having a pitch no greater than 5 μιη or 2 μιη, it is important to utilize as much of the active area as possible to increase the amount of light generated by each light emitting device.

[0020] In some embodiments, the first electrical contact layer comprises a transparent conductive oxide disposed on the light emitting surface. The first electrical contacts can be substantially transparent to light of the first wavelength generated by the active layer. The first electrical contact layer can be disposed as a substantially continuous layer across the light emitting surface. Thus, a common first electrical contact can be provided for the array of light emitting devices using a process that does not require its own alignment step or any patterning. Thus, the array of light emitting devices can be formed as a device comprising a plurality of self-aligned, substantially continuous layers and an array of second electrical contacts.

[0021] In some embodiments, other methods can be used to form the first electrical contact layer to form electrical contact with the semiconductor layer. For example, in some embodiments, the light emitting stack further comprises a via semiconductor portion disposed in the light emitting stack, the via semiconductor portion extending through the active layer between the first semiconductor layer and the contact surface. The first electrical contact layer is disposed on the contact surface in electrical contact with the via semiconductor portion. In some embodiments, the first electrical contact layer can be disposed as a perimeter first electrical contact. The perimeter first electrical contact can be configured to encircle all of the second electrical contacts. The perimeter first electrical contact can be disposed on the contact surface of the light emitting stack in alignment with the respective via semiconductor portions.

[0022] In some embodiments, the first electrical contact layer can be provided as a perimeter first electrical contact disposed on the light emitting face. The perimeter electrical contact can effectively define an opening on the light emitting face, wherein the opening is aligned with the second electrical contact array 30. Thus, the arrangement of the perimeter electrical contact can provide an alternative to forming the first electrical contact layer from a transparent oxide. The formation of the perimeter electrical contact can involve further alignment and patterning steps.

[0023] In some embodiments, the first electrical contact layer and the anti-reflective layer can be formed on the light emitting face to form a graded refractive index interface between the light emitting face of the light emitting stack and the surrounding environment. Thus, the anti-reflective layer and the first electrical contact layer can be configured to form a graded refractive index (GRIN) structure having anti-reflective and electrical contact functionality. The GRIN structure can include a plurality of layers, wherein at least one of the plurality of layers provides the first electrical contact layer and at least one other layer provides the anti-reflective layer. The plurality of layers are formed so as to provide a graded refractive index between the light emitting face and the surrounding environment to reduce reflection at the interface. In some embodiments, the GRIN structure including the first electrical contact layer and the anti-reflective layer can comprise substantially the same material, such as a transparent conductive oxide.

[0024] The light emitting stack includes a plurality of Group III nitride layers. In some embodiments, the light emitting stack is formed from a plurality of generally planar Group III nitride layers. The light emitting stack can be formed from a plurality of Group III nitride layers that are configured to generate light in response to the application of an electrical current when assembled as a light emitting stack. For example, in some embodiments, the light emitting stack includes a first semiconductor layer, a second semiconductor layer, and an active layer.

[0025] In some embodiments, the first semiconductor layer includes an n-type doped Group III nitride. In some embodiments, the second semiconductor layer includes a p-type doped Group III nitride. In some embodiments, the active layer includes a quantum well layer including a plurality of Group III nitrides.

[0026] In some embodiments, the active layer extends as a continuous layer between at least two adjacent light emitting devices of the array of light emitting devices. Thus, the active layer can be provided to the light emitting devices of the array without any patterning of the active layer. That is, the active layer of each light emitting device does not use mesa structures or other patterning to provide the array of light emitting devices. Rather, the light emitting stack is configured to emit light based on the arrangement of the second electrical contact array.

[0027] According to a second aspect of the disclosure, there is provided a method of forming an array of light emitting devices. The method includes:

[0028] forming a light emitting stack on a substrate face of a substrate, the light emitting stack having a light emitting face in contact with the substrate face and a contact face on an opposite side of the light emitting stack, forming the light emitting stack including forming a plurality of Ill-nitride layers, the plurality of Ill-nitride layers including:

[0029] a first semiconductor layer disposed toward the substrate face;

[0030] a second semiconductor layer disposed toward the contact face of the light emitting stack; and

[0031] an active layer disposed between the first semiconductor layer and the second semiconductor layer, the active layer configured to generate light having a first wavelength;

[0032] wherein the light emitting face and the contact face of the light emitting stack are formed parallel to each other and aligned with the plurality of Ill-nitride layers;

[0033] forming a second array of electrical contacts on the contact face of the light emitting stack, each second electrical contact defining a light emitting device between the first semiconductor layer and the second electrical contact, wherein each second electrical contact is spaced apart from other second electrical contacts to form a two-dimensional array of light emitting devices;

[0034] removing the substrate from the light emitting stack to expose the light emitting face of the light emitting stack;

[0035] forming a first electrical contact layer on the light emitting stack, the first contact layer configured to be in electrical contact with the first semiconductor layer; and

[0036] forming an anti-reflective layer on the light emitting face, the anti-reflective layer configured to increase light extraction efficiency of light generated by the light emitting stack.

[0037] Accordingly, the method of the second aspect of the disclosure can provide an array of light emitting devices according to the first aspect of the disclosure. Accordingly, the method of the second aspect of the disclosure can include steps and associated advantages of forming optional features as discussed above for the first aspect of the disclosure.

[0038] The method according to the second aspect of the disclosure includes forming a light emitting stack on a substrate. Accordingly, the light emitting stack can be formed monolithically on the substrate prior to removal of the substrate. Monolithic formation of the light emitting stack is a self-aligned process. That is, the light emitting stack can be formed without any patterning steps, which reduces complexity of the device and also reduces alignment tolerances that can be included between devices. Reducing alignment tolerances can be particularly beneficial for small pitch devices, as the size of the active region relative to the pitch of the device can increase.

[0039] In some embodiments, forming the anti-reflective layer includes forming a third semiconductor layer on the light emitting surface, the third semiconductor layer including a group III nitride and a donor density of at least 1 x 1016cm-3, subjecting the third semiconductor layer to a porosity treatment to increase a surface porosity of the third semiconductor layer to at least 30%. By forming the anti-reflective layer from a group III nitride, the anti-reflective layer can be deposited as the third semiconductor layer as part of a process of forming a light emitting stack on a substrate. That is, the third semiconductor layer can be formed monolithically with the light emitting stack. 18 cm -3 -3 x 1016cm-3, subjecting the third semiconductor layer to a porosity treatment to increase a surface porosity of the third semiconductor layer to at least 30%. By forming the anti-reflective layer from a group III nitride, the anti-reflective layer can be deposited as the third semiconductor layer as part of a process of forming a light emitting stack on a substrate. That is, the third semiconductor layer can be formed monolithically with the light emitting stack. BRIEF DESCRIPTION OF DRAWINGS

[0040] - Figure 1 shows a cross-sectional view of a light emitting device array according to embodiments of the disclosure;

[0041] - Figure 2 shows Figure 1 an annotated cross-sectional view of the light emitting device array shown;

[0042] - Figure 3 shows a plot of the absorption of 50 nm titanium on GaN;

[0043] - Figure 4 shows a plot of the absorption of 50 nm nickel on GaN;

[0044] - Figure 5a shows a plot of the absorption of 50 nm titanium on GaN;

[0045] - Figure 5b shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0046] - Figure 6a shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0047] - Figure 6b shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0048] - Figure 7 shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0049] - Figure 8 shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0050] - Figure 9 shows Figure 8 a plot of the reflectivity of the structure shown;

[0051] - Figure 10 shows a plot of the reflectivity at the light emitting interface between the light emitting stack and air at different angles of incidence;

[0052] - Figure 11 It shows Figure 10 The reflectance diagram of the structure shown;

[0053] - Figure 12 A schematic diagram of a light-emitting stack having an anti-reflective layer comprising multiple sublayers and a transparent conductive oxide common contact layer is shown.

[0054] - Figure 13 It shows Figure 12 The reflectance diagram of the structure shown;

[0055] - Figure 14 A schematic diagram of a light-emitting stack having an anti-reflective layer and a transparent conductive oxide common contact layer arranged to provide a gradient refractive index interface is shown.

[0056] - Figure 15 A cross-sectional view of a light-emitting device array according to a second embodiment of the present disclosure is shown;

[0057] - Figure 16 A cross-sectional view of a light-emitting device array according to a third embodiment of the present disclosure is shown;

[0058] - Figure 17a , 17b 17c, 17d and 17e show cross-sectional views of a process flow for forming an array of light-emitting devices according to a fourth embodiment of the present disclosure;

[0059] - Figure 18 A plan view of the contact surface of the light-emitting device array is shown. Detailed Implementation

[0060] According to a first embodiment of this disclosure, a light-emitting device array 1 is provided. The light-emitting device array 1 includes a light-emitting stack 10, a common first contact layer 40, a second electrical contact array 30, an anti-reflection layer 20, and an absorption layer 50. Figure 1 A cross-section of a light-emitting device array according to a first embodiment is shown.

[0061] like Figure 1 As shown, the light-emitting stack 10 has a contact surface 11 and a light-emitting surface 12. The light-emitting surface 12 and the contact surface 11 are the (opposite) main surfaces of the light-emitting stack 10. The light-emitting stack 10 also includes a sidewall surface 16 extending from the contact surface 11 to the light-emitting surface 12. Figure 1The illustrated cross-section shows a portion of the light emitting device array 1 in a central region of the light emitting device array and a portion of the light emitting device array towards one of the sidewall faces 16. The light emitting face 12 and the contact face 11 of the light emitting stack 10 are parallel to each other. Thus, the light emitting face 12 and the contact face 11 are substantially continuous surfaces extending in planes parallel to each other. The parallel nature of the light emitting face 12 and the contact face 11 allows light generated within the light emitting stack 10 to be totally internally reflected between the light emitting face 12 and the contact face 11 if the angle of incidence of the light on the light emitting face 12 or the contact face 11 is larger than the critical angle.

[0062] The light emitting stack 10 comprises a plurality of Ill-nitride layers. The plurality of Ill-nitride layers is configured to provide a light emitting region within the light emitting stack 10. As Figure 1 illustrated, the light emitting stack 10 comprises a first semiconductor layer 13, an active layer 14 and a second semiconductor layer 15. The active layer 14 is arranged between the first semiconductor layer 13 and the second semi-conductive layer 15. As Figure 1 illustrated in embodiments, the first semiconductor layer 13, the active layer 14 and the second semiconductor layer 15 are all substantially continuous layers which are stacked on top of each other. Thus, the layers of the light emitting stack are generally co-planar.

[0063] In Figure 1 embodiments, the first semiconductor layer 13 comprises Ill-nitride. In some embodiments, the first semiconductor layer 13 comprises GaN. In some embodiments, the first semiconductor layer 13 comprises Ill-nitride doped with an n-type dopant. For example, the first semiconductor layer 13 can comprise n-type doped GaN. Any suitable n-type dopant can be used to dope the first semiconductor layer n-type, for example Si or Ge.

[0064] The active layer 14 is configured to generate light having a first wavelength. Thus, the active layer 14 is configured to provide a light generating region of the light emitting stack 10. In some embodiments, the active layer can comprise a plurality of quantum well layers. Thus, the active layer 14 can be configured to generate light of a first wavelength which is a wavelength of at least 400 nm. In some embodiments, the light of the first wavelength can have a wavelength of no more than 650 nm or no more than 500 nm. Thus, the active layer 14 of the first embodiment can be configured to generate substantially visible light.

[0065] The active layer 14 can comprise one or more quantum wells for generating photons. The quantum well can be formed from a plurality of Ill-nitride layers having different bandgaps. In some embodiments, Ill-nitride alloys comprising In can be used to form the quantum well. A plurality of quantum well active layers for LEDs comprising Ill-nitride are known to the person skilled in the art. In some embodiments, an active layer 14 comprising alternating GaN and InGaN layers can be provided.

[0066] The second semiconductor layer 15 can be p-type doped. Therefore, the second semiconductor layer 15 can include a p-type dopant, such as Mg. For example, in Figure 1 In one embodiment, the second semiconductor layer comprises p-type Mg-doped GaN.

[0067] The first semiconductor layer 13, the active layer 14, and the second semiconductor layer 15 can be formed by any suitable process for forming group III nitrides. For example, in some embodiments, the layers of the light-emitting stack 10 can be formed using metal-organo chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or any other suitable method. In some embodiments, for example Figure 1 In this embodiment, the layers of the light-emitting stack 1 can be formed as a monolithic structure in a single deposition process. The layers of the light-emitting stack 10 can be formed on a substrate (not shown). The light-emitting device stack 10 can be formed on the substrate, first forming a first semiconductor layer 13, then forming an active layer 14, and subsequently forming a second semiconductor layer 15. Other electronic layers (not shown) may also be included in the light-emitting device stack. For example, as part of the process of forming the light-emitting stack 10, an electron blocking layer or a third semiconductor layer (discussed below) may also be formed.

[0068] like Figure 1 As shown, an antireflective layer 20 is formed on the emitting surface 12 of the light-emitting stack 10. The antireflective layer 20 is configured to reduce the reflection of light of a first wavelength at the interface between the light-emitting device array and the surrounding air at the emitting surface 12. Any suitable antireflective layer known to those skilled in the art can be used to form the antireflective layer 20. For example, in Figure 1 In one embodiment, the antireflective layer 20 comprises a material with a refractive index no greater than that of the second semiconductor layer 15 but greater than that of air. The antireflective layer also has a thickness approximately one-quarter the thickness of the first wavelength in a direction perpendicular to the emitting surface 12.

[0069] exist Figure 1 In this embodiment, the antireflective layer 20 includes a porous semiconductor layer. The porous semiconductor layer will be discussed in more detail below. The antireflective layer 20 is disposed at the light-emitting surface 12 to improve the reflection efficiency at a light-emitting angle less than the critical angle (θ). c The extraction efficiency of light incident on the luminous surface 12 at an incident angle of 100°.

[0070] like Figure 1As shown, the array of light emitting devices 1 includes an array of second electrical contacts 30. The array of second electrical contacts 30 is disposed on the contact face 11 of the light emitting stack 10. Each second electrical contact 30 defines a light emitting device between the first semiconductor layer 13 and the respective second electrical contact 30. As Figure 1 As shown in the middle, the second electrical contacts 30 are spaced apart from one another to form the array of second electrical contacts 30. Thus, when each second electrical contact 30 defines a light emitting device, the array of second electrical contacts 30 defines an arrangement of light emitting devices in the array of light emitting devices. Each second electrical contact 30 allows the respective light emitting device to be controlled independently of the other light emitting devices. Applying a voltage to the second electrical contact provides a local electric field between the third electrical contact and the first semiconductor layer 13, causing the active layer 14 to generate light.

[0071] The generation of light in the active layer 14 is confined to the region of the active layer that overlaps the second electrical contact 30. Thus, the active layer 14 includes a plurality of light generating regions. Each light generating region is aligned with a respective second electrical contact. Each light generating region generally has a similar cross-sectional area to the respective second electrical contact 30 in a plane parallel to the light emitting face 12.

[0072] Each light generating region of the active layer 14 generates light that is emitted in all directions. A portion of the light generated by each light generating region will be transmitted in a direction normal to the active layer 14 towards the light emitting face 12. As Figure 2 shown, light incident on the light emitting face 12 at an angle (θ1< θ c ) relative to the normal will at least partially transmit through the light emitting face 12. For example, light generated by the active layer 14 in a direction normal to the active layer 14 will generally transmit through the light emitting face 12. Light incident on the light emitting face 12 at an angle greater than or equal to the critical angle θ c will be totally internally reflected within the light emitting stack 10. Thus, light incident on the light emitting face 12 at an angle relative to the normal of at least the critical angle will not transmit through the light emitting face 12. Thus, total internal reflection and the critical angle are used in the array of light emitting devices 1 to restrict the light emitted from the light emitting devices to a subset of the emission angle.

[0073] The second electrical contacts 30 can comprise any suitable material for forming an ohmic contact with the second semiconductor layer 15. For example, in some embodiments, the second electrical contacts 30 can comprise one or more metal layers, such as gold, nickel or titanium. The second electrical contacts 30 can be arranged as a two-dimensional array on the contact face 11. In some embodiments, the second electrical contacts 30 can be arranged as a square package array, or a hexagonal package array. In a first embodiment, the second electrical contacts 30 are regularly spaced apart from one another so as to define an array of light emitting devices. The second electrical contacts 30 are spaced apart from one another so as to allow the individual light emitting devices to be controlled independently of one another.

[0074] In embodiments of this disclosure, the second electrical contacts 30 are spaced apart to provide a pitched array of light-emitting devices. In this disclosure, the pitch of the light-emitting device array 1 refers to the center-to-center distance between adjacent second electrical contacts 30. Furthermore, the pitch refers to the minimum center-to-center distance between adjacent second electrical contacts in the array of second electrical contacts 30. That is, for example, in a square package array, the pitch refers to the center-to-center distance between adjacent second electrical contacts in a row and / or column, rather than along a diagonal direction. In some embodiments, the pitch of each second electrical contact in the light-emitting device array may be no greater than 5 μm or no greater than 2 μm. Therefore, the pitch of each second electrical contact can define an array of micro-light-emitting devices, wherein the pitch of each micro-light-emitting device is no greater than 5 μm or 2 μm.

[0075] For a given light-emitting device pitch, a first portion of the light-emitting device pitch may be occupied by the second electrical contact 30. A second portion of the light-emitting device pitch may be dedicated to the spacing between adjacent second electrical contacts 30. In some embodiments, the spacing between adjacent second electrical contacts may be at least 500 nm. The amount of spacing between adjacent second electrical contacts 30 may not change significantly with the increase in the size of the light-emitting device pitch. Therefore, as the device size increases, the portion of the light-emitting device pitch used for the device spacing that is not the portion used for the second electrical contacts may decrease.

[0076] like Figure 1 As shown, the common first contact layer 40 is disposed on the light-emitting surface 12. Figure 1 In some embodiments, the common first contact layer 40 is configured to cover the light-emitting surface 12 of the light-emitting stack 10 and the anti-reflection layer 20. Therefore, the anti-reflection layer 20 is disposed between the light-emitting stack 10 and the common first contact layer 40. In some embodiments, the anti-reflection layer 20 and the common first contact layer may be arranged in opposite directions (i.e., the common first contact layer 40 is disposed between the light-emitting stack 10 and the anti-reflection layer 20).

[0077] exist Figure 1 In some embodiments, the common first contact layer 40 comprises a transparent conductive oxide. The transparent conductive oxide is configured to be generally transparent to the first wavelength and also forms an ohmic contact with the first semiconductor layer 13 via the antireflective layer 20. For example, in some embodiments, the transparent conductive oxide may have at least 90% transmittance to light of the first wavelength.

[0078] like Figure 1 As shown, the common first contact layer 40 is provided as a substantially continuous layer across the light-emitting surface 12. The common first contact layer 40 provides a first contact for each light-emitting device in the light-emitting device array 1. Therefore, the light-emitting device array 1 of the first embodiment effectively provides a common first contact layer for the devices of the light-emitting device array in the self-alignment processing step.

[0079] As Figure 2 illustrated, as light from the active layer propagates from the light emitting stack through the light emitting face 12 to the ambient, the light is refracted. The refraction of the light results in an increase in the angle of exit (θ2in Figure 2 Figure 2 illustrated) with respect to the normal as the light exits the device. This refraction further reduces the occurrence of cross-talk between adjacent light emitting devices. A person viewing the array of light emitting devices 1 (for example, as

[0080] The array of light emitting devices 1 of the first embodiment also includes an absorbing layer 50. The absorbing layer 50 is configured to absorb light of a first wavelength generated by the active layer 14. The absorbing layer 50 can be provided on the light emitting stack 10 to cover areas of the light emitting stack where emission of light of the first wavelength is not desired. The absorbing layer 50 also provides a means for absorbing light of total internal reflection within the light emitting stack 10.

[0081] In Figure 1 embodiments, the absorbing layer 50 is provided on at least one of the sidewall faces 16 of the light emitting stack 10. The absorbing layer 50 can be provided as a substantially continuous layer on the sidewall face. As Figure 1 illustrated, a first portion 51 of the absorbing layer covers substantially the entire sidewall face 16 of the light emitting stack 10.

[0082] The absorbing layer 50 can also be provided on other surfaces of the light emitting stack 10, for example around the periphery of the light emitting face 12. As Figure 1 illustrated, a second portion 52 of the absorbing layer is provided around the periphery of the light emitting face to define an edge region of the light emitting face 12. The second portion 52 of the absorbing layer provided around the periphery of the light emitting face 12 can help to reduce or eliminate the occurrence of undesirable optical effects due to the presence of the sidewall faces of the light emitting stack 10.

[0083] The absorbing layer 50 can comprise any suitable material configured to absorb light of the first wavelength. In Figure 1 embodiments, in which the active layer 14 is configured to emit light having a first wavelength of between 440 nm and 500 nm, the absorbing layer 50 can comprise a layer of a metal such as Ni or Ti. Figure 3a An absorption graph is shown for an absorbing layer comprising a 50 nm layer of Ti on a GaN substrate (the graph of which is shown in 3b). Figure 3 shows an absorption graph for a 50 nm layer of Ni on a GaN substrate. It will therefore be appreciated that a thin film of a metal (for example having a thickness of less than 500 nm) can be used to provide a suitable absorbing layer. ​

[0084] As described above, the anti-reflective layer 20 may include a porous semiconductor layer. Reference will now be made to... Figure 5a , 5b 6a and 6b discuss porous semiconductor layers.

[0085] Figure 5a A schematic diagram of a light-emitting stack 10 is shown, which does not have an anti-reflective layer disposed on the light-emitting surface 12. Therefore, the light-emitting surface 12 is the interface between the first semiconductor layer 13 comprising n-type doped GaN and air. Figure 5a As shown, light incident from the active layer 14 onto the light-emitting surface 12 will partially pass through the light-emitting surface 12 if the incident angle is less than the critical angle (i.e., some light can be reflected), or will be completely internally reflected if the incident angle is greater than the critical angle.

[0086] Figure 5b A graph showing the reflectivity of light at different wavelengths at the interface between the first semiconductor layer 13 and air is shown. Figure 5b The reflectivity of light incident on the luminescent surface is shown at angles a) perpendicular to the luminescent surface 12, b) at an angle of 20 degrees relative to the normal, and c) at an angle of 24 degrees relative to the normal. Figure 5b It is understandable that the interface between the light-emitting stack 10 and the air can be highly reflective of light incident at angles perpendicular or near perpendicular to the light-emitting surface. When the incident angle approaches the critical angle, the reflectivity of light with a wavelength of approximately 450 nm increases from slightly less than 0.2 to 1.0. For n-type doped GaN, the critical angle is approximately 24 degrees. Incident angles exceeding 24 degrees will result in total internal reflection of the light.

[0087] Figure 6a A schematic diagram of a light-emitting stack 10 is shown, in which an anti-reflection layer 20 is provided on the light-emitting surface 12. The anti-reflection layer 20 comprises n-type doped GaN, which undergoes porosity treatment to increase the porosity of the GaN to at least 30%. The porosity treatment process will be discussed in more detail below. Figure 6a In the schematic diagram, the porosity of GaN is approximately 70%.

[0088] Figure 6b It shows a porous semiconductor layer. Figure 6a The graph shows the reflectivity between the luminescent stack and air in the structure. (Example:) Figure 6b As shown, for light incident on the light-emitting surface 12 in a direction substantially perpendicular to it, the reflectivity is less than 0.1 for all wavelengths in the range of 400 nm to 700 nm. The reflectivity remains less than 0.1 when the incident angle increases to 20 degrees. Therefore, the anti-reflection layer 20 can be used to significantly reduce light reflection at multiple incident angles that will emit light from the light-emitting device array at an emission angle suitable for observation by an observer.Figure 6b As shown, when the incident angle increases to 24 degrees, the reflectivity at the interface significantly increases to over 0.8. Of course, from... Figure 2 As can be seen from the information shown, due to refraction at the light-emitting surface 12, a wider incident angle is unlikely to result in the emission of observable light. Therefore, reflection at incident angles greater than 20° will not affect the observable light output of the light-emitting device array 1.

[0089] like Figure 6a As shown, the thickness of the anti-reflective layer 20 is selected to provide a quarter-wavelength anti-reflective layer 20. Therefore, the thickness of the anti-reflective layer is chosen to be λ0 / 4n. p , where n p This is the refractive index of the antireflective layer 20 at λ0. In the embodiment where the antireflective layer 20 is provided by a porous semiconductor layer, the refractive index n of the porous semiconductor layer is... p This can depend on the porosity of the porous semiconductor layer. Generally, as the porosity of the porous semiconductor layer increases, the refractive index of the porous semiconductor layer can decrease. For example, in some embodiments where the porous semiconductor layer includes GaN, the following relationship between porosity and refractive index can be found in Table 1 below.

[0090] Porosity n p @450nm]]> 0％ 2.44 10.0％ 2.34 20.0％ 2.23 30.0％ 2.12 40.0％ 2.00 50.0％ 1.87 60.0％ 1.73 70.0％ 1.58 80.0％ 1.41 90.0％ 1.22

[0091] Table 1

[0092] Therefore, the thickness of the porous semiconductor layer used as the antireflective layer 20 will depend on the wavelength of the first wavelength and the porosity of the semiconductor layer. In some embodiments, a porous semiconductor layer with a porosity of at least 60% and / or no more than 80% can be selected, such that the refractive index is near xy. Figure 6a In the illustrated embodiment, the porous semiconductor layer has a porosity of 70%.

[0093] In some embodiments, the antireflective layer 20 may be provided by a stack of porous semiconductor sublayers. These stacks of porous semiconductor sublayers may have different porosities, resulting in variations in the refractive index passing through the antireflective layer 20. Each porous semiconductor sublayer is formed to form a corresponding third semiconductor sublayer by subjecting the semiconductor sublayers to a porosity treatment process. The (surface) porosity of the semiconductor sublayers can be controlled by controlling the doping density in the corresponding third semiconductor sublayer, as discussed in more detail below. The porosity of each porous semiconductor sublayer can be selected to provide each porous semiconductor sublayer with a desired refractive index. Furthermore, the thickness (in the direction perpendicular to the light-emitting surface 12) and the number of porous semiconductor sublayers can be selected separately to provide the antireflective layer 20 with desired optical properties.

[0094] By forming the antireflective layer 20 from the porous semiconductor layer, the precursor material for forming the porous semiconductor layer can be used as part of the process of forming the light-emitting stack 10. Therefore, the method of forming the light-emitting device array 1 may include forming a third semiconductor layer on the light-emitting surface 12. The third semiconductor layer comprises a group III nitride and has a density of at least 1 x 10⁻⁶. 18 cm -3 The donor density is [not specified]. Therefore, the third semiconducting layer is a relatively highly doped group III nitride semiconductor. The third semiconductor layer can be doped to have a higher doping concentration than the first semiconductor layer, such that subsequent porosity treatment processes selectively affect the third semiconductor layer rather than the first semiconductor layer 13, in order to provide a distinct boundary between the antireflective layer 20 and the first semiconductor layer 13. For example, in a first embodiment, the first semiconductor layer 13 has a donor density of at least 1 x 10⁻⁶. 17 cm -3 and no greater than 1x10 18 cm -3 The n-type doping density, and the third semiconductor layer is formed with at least 1x10⁻⁶. 18 cm -3 Preferably at least 5x10 18 cm -3 n-type doping density.

[0095] exist Figure 1 In embodiments, the antireflective layer 20 is configured to take into account the presence of the common first contact layer 40, in Figure 1 In the middle, the common first contact layer 40 is provided by a transparent conductive oxide layer. Figure 7 A schematic diagram of a light-emitting stack 10 having two layers disposed on a light-emitting surface 12 is shown. For example, according to a first embodiment of this disclosure, the two layers may be an anti-reflective layer 20 and a common first contact layer 40 comprising a transparent conductive oxide.

[0096] Next, the design of the antireflective layer 20 will be discussed with reference to an embodiment in which two layers exist on the light-emitting surface (e.g., in the first embodiment). Figure 7 As shown, the third refractive index of the first semiconductor layer 13 is n3, the second refractive index of the first layer (e.g., antireflective layer 20) disposed on the light-emitting surface 12 is n2, and the first refractive index of the second layer (e.g., transparent conductive oxide layer) disposed on the first layer is n1. The thickness of the first layer (e.g., antireflective layer 20) in the direction perpendicular to the light-emitting surface 12 is t2. The thickness of the second layer (e.g., transparent conductive oxide layer) in the direction perpendicular to the light-emitting surface 12 is t1.

[0097] Given Figure 7 The arrangement shown can be defined with the following parameters, where λ is the wavelength of the light emitted by the active layer 14:

[0098]

[0099]

[0100] Thus, for light of wavelength λ incident normally to the light emitting face, the reflectivity (R) of the bi-layer coating on the light emitting face 12 can be calculated as:

[0101]

[0102] where:

[0103]

[0104] Using the above equations, the anti-reflective layer 20 can be configured to reduce the reflection of light of the first wavelength at the interface between the light emitting stack 10 and the ambient environment (i.e. air) at the light emitting face 12.

[0105] Some possible examples of the anti-reflective layer 20 and the common first contact layer 40 will now be described with reference to

[0106] Figures. In Figures 8 to 13 the figures, diagrams of a light emitting stack 10 having an anti-reflective layer 20 and a common first contact layer 40 comprising ITO are shown. In Figure 8 the figures, diagrams of a light emitting stack 10 having an anti-reflective layer 20 and a common first contact layer 40 comprising ITO are shown. In Figure 8 the example of Figure 1, the ITO layer has a thickness t1 of 210 nm and has a refractive index n1 of 2.03 at 455 nm. According to the calculations above, the anti-reflective layer 20 is provided by a 70% areal porosity porous semiconductor layer with a thickness t2 of 100 nm (n2 = 1.58 at 450 nm). Such an anti-reflective layer 20 provides a reflectivity R of approximately 0 for light of wavelength λ = 455 nm. Figure 9 diagrams of the reflectivity of the structures shown. Figure 8 diagrams of the reflectivity of the structures shown.

[0107] As mentioned above, both the anti-reflective layer 20 and the common first contact layer 40 can be provided on the light emitting face 12. In a first embodiment, the anti-reflective layer 20 is provided in direct contact with the light emitting face 12 of the light emitting stack 12, such that the anti-reflective layer 20 is provided between the light emitting stack 10 and the common first contact layer 40. In some embodiments, the common first contact layer 40 and the anti-reflective layer 20 can be provided in reverse arrangement. For example, as shown in Figure 10 Figure 2, the common first contact layer 40 is provided in direct contact with the light emitting face 12 of the light emitting stack 10. The anti-reflective layer 20 is provided on the first contact layer 40. Thus, the first contact layer 40 is provided between the light emitting stack 10 and the anti-reflective layer 20.

[0108] In Figure 10In the example, the ITO layer has a thickness t2 of 250 nm and a refractive index n2 of 2.03 at 455 nm. Based on the above calculations, the antireflective layer 20 is provided by a SiO2 layer with a thickness t1 of 65 nm (n1 = 1.47 at 455 nm). This antireflective layer 20 provides a reflectivity R of approximately 0 for light with a wavelength λ = 455 nm. Figure 11 It shows Figure 10 The graph shows the reflectivity of the structure.

[0109] In some embodiments, the antireflective layer 20 may include a plurality of antireflective sublayers 22, 24, and 26. Figure 12 An example of this anti-reflective layer 20 is shown. For example... Figure 12 As shown, the antireflective layer 20 includes a first antireflective sublayer 22, a second antireflective sublayer 24, and a third antireflective sublayer 26. The antireflective sublayers are arranged sequentially from the emitting surface 12. The multiple antireflective sublayers 22, 24, and 26 provide an antireflective layer 20 with a graded refractive index. Therefore, the refractive index of the antireflective layer 20 is graded, decreasing in the direction perpendicular to the emitting surface 12. This decrease in refractive index is achieved by altering the porosity of the antireflective sublayers. Figure 12 In one embodiment, the refractive index decreases from 2.23 (20% porosity) to 1.58 (70% porosity). The refractive index decreases in a stepwise manner due to the multiple antireflective sublayers 22, 24, 26. In other embodiments, a graded refractive index can be provided by smoothly varying the porosity of the antireflective layer 20. Other possible variations in refractive index can also be provided, such as increases in refractive index, alternating values ​​of refractive index, or any combination of increases and decreases.

[0110] exist Figure 12 In the example, the ITO layer has a thickness t1 of 210 nm and a refractive index n1 of 2.03 at 455 nm. The first antireflective sublayer 22 is a porous semiconductor layer with a surface porosity of 20% (n = 2.23) and a thickness of 50 nm. The second antireflective sublayer 24 is a porous semiconductor layer with a surface porosity of 40% (n = 2.00) and a thickness of 50 nm, and the third antireflective sublayer 26 is a porous semiconductor layer with a surface porosity of 70% (n = 2.23) and a thickness of 60 nm. This antireflective layer 20 provides a reflectivity R of approximately 0 for light with a wavelength λ = 455 nm. Figure 13 It shows Figure 12 The graph shows the reflectivity of the structure.

[0111] from Figure 8 and Figure 10 As can be understood from the example, the relative positions of the anti-reflective layer 20 and the common first contact layer 40 can be interchanged. From Figure 12The examples will also illustrate that a layer with a graded refractive index can be disposed on the luminescent surface 12 to provide desired optical properties. Based on these concepts, Figure 14 An example is shown where the anti-reflective layer 20 and the common first contact layer 40 form a graded refractive index (GRIN) structure 28 with anti-reflective and electrical contact functions. Figure 14 In the example, the GRIN structure 28 includes multiple layers. At least one of the layers provides a common first contact layer 40, while at least another layer provides an anti-reflective layer 20. In the GRIN structure 28, each of the multiple layers includes the same transparent conductive oxide, such as ITO. Figure 12 Similar to the example, multiple layers are formed to provide a gradient refractive index. Therefore, multiple layers are formed to provide a variable refractive index that decreases toward 1 in the direction perpendicular to the emitting surface.

[0112] The refractive index of transparent conductive oxides can be varied by changing their porosity. One known method for altering the porosity of transparent conductive oxides (e.g., ITO) is oblique deposition using electron beam evaporation. By changing the angle of the deposition surface relative to the vapor flow deposition, the amount of shadow cast by the deposited material can be controlled, thereby controlling the porosity of the formed layer. Further explanation of ITO oblique deposition can be found at least in the paper "Light-Extraction Enhancement of GaInN Light EmittingDiodes by Graded-Refractive-Index Indium Tin Oxide Anti-Reflection Contact" published by Jong Kyu Kim et al. in *Advanced Materials* (0000, 00, 1-5).

[0113] exist Figure 14 In the example, the GRIN structure 28 comprises six distinct layers. Each layer comprises ITO with a different refractive index. The refractive index of the six layers can vary from approximately 2.2 at the emitting surface to approximately 1.2 at the interface with free space. For example, the refractive indices of the six distinct layers can be chosen to be 2.2, 2.0, 1.8, 1.5, 1.3, and 1.2. Of course, the thickness and refractive index of the GRIN structure 28 can be varied according to the first wavelength of the light emitted by the active region 14.

[0114] Next, a method of forming the array of light emitting devices 1 according to the first embodiment will be described. The method includes forming the light emitting stack 10 on a substrate face of a substrate. The substrate can be any suitable substrate for forming Ill-nitride. For example, the substrate can include a Si wafer or a Sapphire wafer.

[0115] The light emitting stack 10 is formed such that the light emitting face 12 in the light emitting stack 10 is oriented towards the substrate face. The contact face 11 of the light emitting stack 10 is disposed on the other side of the light emitting stack 10. Thus, the contact face 11 is oriented away from the substrate face (relative to the light emitting face 12).

[0116] Forming the light emitting stack 10 includes forming a plurality of Ill-nitride layers on the substrate face. The layers of the light emitting stack 10 include a first semiconductor layer 13, an active layer 14, and a second semiconductor layer 15. The first semiconductor layer 13, the active layer 14, and the second semiconductor layer 15 are formed in sequence such that the active layer 14 is disposed between the first semiconductor layer 13 and the second semiconductor layer 15. As described above, the first semiconductor layer 13, the second semiconductor layer 15, and the active layer 14 can be formed using the MOCVD process or the MBE process as described above. As described above with respect to the first embodiment and the second embodiment, the first semiconductor layer 13, the second semiconductor layer 15, and the active layer 14 can be formed using the same process. Figure 1 As described above with respect to the first embodiment and the second embodiment, the light emitting face and the contact face 11 of the light emitting stack 10 are formed parallel to each other and aligned with the plurality of Ill-nitride layers.

[0117] After forming the light emitting stack 10, an array of second electrical contacts 30 is formed on the contact face 11 of the light emitting stack 10. Each second electrical contact 30 defines a light emitting device between the first semiconductor layer 13 and the second electrical contact 30. Each second electrical contact 30 is spaced apart from the other second electrical contacts 30 to form a two-dimensional array of light emitting devices. The second electrical contacts 30 can be formed as discussed in more detail above.

[0118] After forming the second electrical contacts 30, the substrate can be removed from the light emitting stack. After removing the substrate, a common first contact layer 40 can be formed on the light emitting stack 10. For example, in the first embodiment, the common first contact layer 40 can be formed as a transparent conductive oxide over the light emitting face 12 of the light emitting stack 10. The common first contact layer 40 is configured to be in electrical contact with the first semiconductor layer 13 of the light emitting stack 10.

[0119] An anti-reflective layer 20 is also formed on the light emitting face 12. In some embodiments, the anti-reflective layer 20 can be formed on the light emitting face 12 after the substrate is removed. In other embodiments, for example, as described above with respect to the second embodiment, the anti-reflective layer 20 can be formed on the light emitting face 12 before the common first contact layer 40 is formed. Figure 10As shown, the anti-reflective layer 20 can be formed on the common first contact layer 40. In some embodiments, the anti-reflective layer 20 can comprise a porous semiconductor layer. In other embodiments, the anti-reflective layer can comprise Si02, ITO or any other material having a suitable refractive index.

[0120] In some embodiments, the anti-reflective layer comprises a porous semiconductor layer. Such an anti-reflective layer 20 can be formed by forming a third semiconductor layer on the substrate face of the substrate prior to forming the light emitting stack 10. The third semiconductor layer can comprise a group III nitride, such as GaN, doped with an n-type dopant. In some embodiments, the third semiconductor layer is formed from the same group III nitride as the first semiconductor layer 13, wherein the doping density of the third semiconductor layer is varied with respect to the first semiconductor layer 13. The light emitting stack 10 is then formed on the exposed surface of the third semiconductor layer, as described above. As part of the method of forming the light emitting device array 1, after removal of the substrate, the third semiconductor layer can then be subjected to a porosity treatment to form the anti-reflective layer 20 as a porous semiconductor layer. It will thus be appreciated that the formation of the anti-reflective layer 20 can be integrated into the process of forming the group III nitride layers of the light emitting stack 10. The formation of the anti-reflective layer 20 can thus be integrated as part of the group III nitride layer alignment-free process of forming the light emitting device array 1.

[0121] As described above, the anti-reflective layer 20 can be provided by a porous semiconductor layer. The porous semiconductor layer can be formed by subjecting the third semiconductor layer to a porosity treatment process. The porosity treatment process can be performed after the formation of the light emitting stack 10. The porosity treatment process is configured to increase the porosity (in-plane porosity) of the third semiconductor layer. Methods of increasing the porosity of group III nitride layers are known to those skilled in the art. For example, Xiuling Li, Young Woon Kim et al. in Applied Physics Letters, Vol. 8, No. 6, 11 February 2002, “In-plane bandgap control in porous GaN through electroless wet chemical etching” describe several processes of increasing the porosity of n-type doped group III nitride layers.

[0122] For example, the porosity treatment process can comprise subjecting the third semiconductor layer (and the layers of the light emitting stack 10) to an electrochemical treatment process. The electrochemical treatment process can comprise immersing the third semiconductor layer in an oxalic acid bath. An electrical connection is made between the oxalic acid bath and the third semiconductor layer. An electrical current is passed between the electrical contacts of the oxalic acid bath and the third semiconductor layer to electrochemically form pores within the third semiconductor layer. In some embodiments, the oxalic acid bath comprises an oxalic acid solution having a concentration between 0.03M and 0.3M. In other embodiments, the oxalic acid bath can be replaced by other electrolytes such as KOH or HC1. The electrical bias level applied to the electrochemical process will depend on the electrochemical solution used as well as the relative dimensions of the bath and the third semiconductor layer / light emitting stack 10. Further examples of porosity treatment are described in ACS applied Nano Materials 2020, vol. 3, pp. 399-402 and US 2017 / 0237234.

[0123] The porosity treatment process results in the formation of pores present in the third semiconductor layer or an increase in the size of the pores. The porosity of the third semiconductor layer can be characterised by the areal porosity. The areal porosity is the area fraction of pores present in a cross-section through the material, i.e. through the third semiconductor layer. In some embodiments, the porous semiconductor layer has an areal porosity of at least 30%. In some embodiments, the porous semiconductor layer has an areal porosity of at least 40%. In some embodiments, the areal porosity of the porous semiconductor layer 14’ is no greater than 80%. By providing a porous semiconductor layer having such an areal porosity, the third semiconductor layer has a refractive index suitable for forming the anti-reflective layer 20.

[0124] In some embodiments, the method can further comprise forming an absorption layer 50 on at least a portion of the light emitting stack 10. The absorption layer 50 can be formed on the sidewall faces of the light emitting stack.

[0125] Thus, it will be appreciated that the above described method can be used to provide a light emitting device array 1 according to the first embodiment of the disclosure.

[0126] Next, a light emitting device array 2 according to a second embodiment of the disclosure will be described.

[0127] The light emitting device array 2 according to the second embodiment of the disclosure comprises a light emitting stack 10, an anti-reflective layer 20, an array of second electrical contacts 30 and a common first contact layer 40. These features are similar to those described above in relation to the first embodiment. A cross-sectional illustration of the light emitting device array 2 according to the second embodiment of the disclosure is shown in Figure 15 .

[0128] As Figure 15As shown, the array of light emitting devices 2 includes an absorbing layer 50. The absorbing layer 50 includes a first portion 51 that substantially covers the entire sidewall surface 16 of the light emitting stack 10 in a manner similar to that described in the first embodiment. A second portion 52 of the absorbing layer can also be disposed around the perimeter of the light emitting surface 12 in a manner similar to that of the first embodiment.

[0129] In the second embodiment of the present disclosure, a third portion 53 of the absorbing layer is disposed on the contact surface 11. The third portion 53 of the absorbing layer is disposed in the area of the contact surface 11 between adjacent ones of the array of second electrical contacts 30. As shown, Figure 15 The third portion 53 of the absorbing layer can be spaced apart from the second electrical contacts 30 to prevent shorting between the second electrical contacts 30. The third portion 53 of the absorbing layer provides an additional absorption area for light generated in the active layer. The third portion 53 of the absorbing layer can be configured to absorb light generated in the active layer 14 that is reflected from the light emitting surface 12 at an angle less than the critical angle or that is directly incident on the contact surface 11. By absorbing such stray light, the likelihood of the stray light being reflected to the light emitting surface 12 and possibly being emitted is reduced, thereby further reducing the occurrence of any cross-talk between adjacent light emitting devices 1.

[0130] The third portion 53 of the absorbing layer 50 can be formed in a manner similar to the first and second portions of the absorbing layer 50. The third portion 53 of the absorbing layer can be formed using any suitable patterning technique, such as photolithography. The third portion of the absorbing layer can be formed prior to forming the second electrical contacts 30 or after forming the second electrical contacts 30. In some embodiments, the third portion 53 of the absorbing layer effectively defines a grid including a plurality of openings in which the second electrical contacts 30 are disposed. Since the formation of such a grid can require an additional patterning step in some embodiments, the third portion 53 of the absorbing layer can not be provided.

[0131] Next, a third embodiment of an array of light emitting devices 3 will be described. A cross-sectional view of the third embodiment of the array of light emitting devices 3 is shown in Figure 16 As shown in Figure 16 The array of light emitting devices 3 includes a light emitting stack 10, an anti-reflective layer 20, an array of second electrical contacts 30, a common first contact layer 40, and an absorbing layer 50. Similar to the second embodiment, the absorbing layer 50 includes a first portion 51, a second portion 52, and a third portion 53.

[0132] In the third embodiment of the array of light emitting devices 3, the absorption layer 50 also includes a fourth portion 54. The fourth portion 54 of the absorption layer is provided as a continuous layer on the light emitting face 12, the continuous layer including a plurality of openings through the thickness of the fourth portion 54 of the absorption layer. Each opening through the fourth portion 54 of the absorption layer is aligned with a second electrical contact such that light from each light emitting device propagating in a direction generally normal to the light emitting face can propagate through the respective opening. As shown in Figure 16 the fourth portion 54 of the absorption layer on the light emitting face 12 is generally aligned with the third portion 53 of the absorption layer provided on the contact face 11. Thus, the openings provided by the fourth portion 54 of the absorption layer can be similar to the openings provided by the grid of the third portion 53 of the absorption layer for the second electrical contacts 30. In some embodiments, the grid formed by the third portion 53 of the absorption layer can be the same as the grid formed by the fourth portion 54 of the absorption layer. That is, in some embodiments, the same mask pattern can be used to form both the third portion 53 and the fourth portion 54 of the absorption layer 50. Of course, in other embodiments, different patterns can be used to form the third portion 53 of the absorption layer and the fourth portion 54 of the absorption layer.

[0133] The fourth portion 54 of the absorption layer is provided on the light emitting face 12 to define a plurality of openings through which light can be emitted. Within the regions covered by the fourth portion 54 of the absorption layer, light will not be emitted from the light emitting face 12. Thus, the fourth portion 54 of the absorption layer can be provided to further reduce and / or eliminate cross-talk between adjacent light emitting devices.

[0134] As noted above, the second and third embodiments of the present disclosure have an absorption layer 20 and a common first contact layer 40 similar to those described in the first embodiment. It will be appreciated that in other embodiments of the present disclosure, other absorption layers 20 and other first electrical contact layers can be provided. For example, those skilled in the art will appreciate that the second and third embodiments can be combined with any of the absorption layers 20 and common first contact layers 40 described above in relation to the first embodiment. Figures 7 to 14

[0135] Next, reference will be made to Figure 17a , 17b ​A fourth embodiment of the light emitting device array 4 is described in Figures 9c, 17d and 17e. In the first, second and third embodiments of the disclosure, the common first contact layer 40 is provided using a transparent conductive oxide, which is disposed on the light emitting face 12 of the light emitting stack 10. According to the fourth embodiment of the disclosure, the common first contact layer 40 can also be provided using electrical contacts located on the contact face side of the light emitting stack 10. This process allows the first and second electrical contacts of the light emitting device array 4 to be located on the same surface (i.e. the contact face 11), so that the light emitting device array 4 can be more easily connected to control electronics. For example, the light emitting device array 4 of the fourth embodiment can be bonded to a backplane electronics array using suitable bonding techniques.

[0136] Figures 17a to 17e The process of forming the common first electrical contact on the contact face 11 of the light emitting stack 10 is shown. For simplicity, other layers of the light emitting device array 4 are not shown, but it will be appreciated that they can be formed by any of the methods described above in relation to the first, second and third embodiments of the disclosure.

[0137] As shown in Figures 17b and 17c, the through-semiconductor parts 61 can be formed by selectively removing a portion of the light emitting stack 10 from the contact face up to the first semiconductor layer 13. The selective removal process can be performed after the light emitting stack 10 has been formed, preferably before the substrate is removed (not shown). The selective removal process can comprise patterning the contact face 11 using a mask layer 62. The mask layer can define one or more openings which define the regions of the light emitting stack 10 to be selectively removed. The mask layer 62 can comprise any material suitable for use as a mask for a selective removal process. For example, in the embodiment of Figures 9c, 17d and 17e, the mask layer 62 comprises Si02. The mask layer can be formed by any suitable method, for example Chemical Vapour Deposition. The mask layer can be patterned using any suitable technique, for example photolithography. Figure 17a Figure 17e An example of such a through-semiconductor part 61 is shown in Figure 17a.

[0138] As shown in Figures 17b and 17c, the through-semiconductor parts 61 can be formed by selectively removing a portion of the light emitting stack 10 from the contact face up to the first semiconductor layer 13. The selective removal process can be performed after the light emitting stack 10 has been formed, preferably before the substrate is removed (not shown). The selective removal process can comprise patterning the contact face 11 using a mask layer 62. The mask layer can define one or more openings which define the regions of the light emitting stack 10 to be selectively removed. The mask layer 62 can comprise any material suitable for use as a mask for a selective removal process. For example, in the embodiment of Figures 9c, 17d and 17e, the mask layer 62 comprises Si02. The mask layer can be formed by any suitable method, for example Chemical Vapour Deposition. The mask layer can be patterned using any suitable technique, for example photolithography. Figures 17a-17e ​​

[0139] After the mask layer 62 is formed, the light-emitting stack 10 can be subjected to a selective removal process, such as etching, to form voids in which through-hole semiconductor portions 61 are formed. Figure 17b An example of this type of gap is shown.

[0140] Then, the through-hole semiconductor portion 61 can be formed within the gap, for example, as... Figure 17c As shown. In Figure 17c In one embodiment, the through-hole semiconductor portion 61 comprises the same material as the first semiconductor layer 13, which in Figure 17c The middle layer is n-type doped GaN. Therefore, the through-hole semiconductor portion 61 is regenerated on the first semiconductor layer 13 to provide an n-type doped semiconductor region on the contact surface 11.

[0141] After forming the through-hole semiconductor portion 61, the mask layer 62 is removed, and a second electrical contact 30 is formed on the contact surface 11. For example... Figure 17d As shown, the second electrical contact 30 is formed on the area of ​​the contact surface 11 provided by the second semiconductor layer 15, rather than on the through-hole semiconductor portion 61.

[0142] A first electrical contact 41 is formed on the through-hole semiconductor portion 61 to provide a contact to the first semiconductor layer 13. An example of the first electrical contact is shown below. Figure 17e As shown. Therefore, according to the fourth embodiment, the first and second electrical contacts 41, 30 can be disposed on the same surface (contact surface 11) of the light-emitting stack 10. The first electrical contact 41 may include any suitable material for forming an ohmic contact with the through-hole semiconductor portion 61 (n-type).

[0143] After the first electrical contact 61 is formed, the contact surface 11 can undergo an ion implantation process. The ion implantation process can affect the exposed area of ​​the second semiconductor layer 15 between the first and second electrical contacts 41, 30. The ion implantation process can disrupt the crystal structure of the light-emitting stack 10 in these areas to improve the electrical isolation between the through-hole semiconductor portion 61 and the light-emitting device. Therefore, the light-emitting stack 10, for example as... Figure 17e As shown, an ion implantation region 63 may be included between the through-hole semiconductor portion 61 and the light-emitting device. Therefore, the ion implantation region 63 can effectively surround the through-hole semiconductor portion 61 in the light-emitting device stack 10.

[0144] Therefore, the fourth embodiment provides a light-emitting device array 4, wherein first and second electrical contacts 41, 30 are disposed on the contact surface 11. Those skilled in the art will understand. Figures 17a-17e The embodiment shown is only one possible arrangement of the first and second electrical contacts 41, 30. Those skilled in the art will understand that the contact layout can be adjusted according to device size, device layout, etc.

[0145] As one example, Figure 18 Another example of one possible arrangement of an array of common first and second electrical contacts 30 according to embodiments of the present disclosure is provided. As shown in Figure 18 The common first electrical contact is provided as a perimeter first electrical contact 42. This perimeter first electrical contact 42 surrounds all of the second electrical contacts 30. The perimeter first electrical contact can be provided on the contact face 11 of the light emitting stack 10, in alignment with the corresponding via semiconductor portions 61. In some embodiments, the perimeter first electrical contact 42 can be provided on the light emitting face 12, as an alternative to a transparent electrical contact. The perimeter first electrical contact 42 is particularly useful in embodiments where the number of light emitting devices in the array is no greater than 1000 in each dimension. Thus, for a light emitting device array having no greater than 1000 x 1000 light emitting devices, the surface area of the light emitting device array is such that it is possible to ensure that the perimeter contact is able to provide sufficient current to all of the light emitting devices in the array. In particular, for arrays having a pitch no greater than 5 pm, it will be appreciated that an array having no greater than 1000 light emitting devices has a light emitting face no greater than about 5 mm. In some embodiments, where the light emitting array has about 400 x 600 light emitting devices with a pixel pitch of 1 pm, a light emitting device array of about 0.4 mm x 0.6 mm can be provided.

[0146] In the schematic view of Figure 18 the perimeter first electrical contact 42 is shown extending around the perimeter in a continuous loop. Of course, in other embodiments, the perimeter first electrical contact 42 can not be a continuous loop. For example, a c-shaped perimeter first electrical contact 42 can be suitable. Indeed, the perimeter electrical contact 42 defines an opening on the light emitting face 12, where this opening is aligned with the array of second electrical contacts 30.

[0147] In the schematic view of Figure 18 the second electrical contacts 30 are shown as circular contacts. Of course, other shapes of second electrical contacts can be suitable.

[0148] Thus, according to embodiments of the present disclosure, a light emitting device array and a method of forming a light emitting device array are provided. The light emitting device array of the present disclosure can be formed using minimal patterning steps, thereby reducing or eliminating alignment steps during formation of the light emitting device array. Reducing or eliminating alignment steps is particularly advantageous for small pitch devices (e.g. devices having a pitch no greater than 5 pm), as it increases the area available for forming the light emitting devices.

[0149] By using the array of second electrical contacts on the contact face to define each light emitting device, it is also possible to increase the light emitting area of each device. Thus, embodiments of the present disclosure seek to increase the size of the active region of each light emitting device relative to the overall light emitting device pitch.

[0150] While embodiments of the present disclosure have been described in detail, those skilled in the art will understand that they can be modified without departing from the scope of the application, as defined by the appended claims.

Claims

1. An array of light emitting devices comprising: a light emitting stack having a light emitting face and a contact face, the light emitting face and the contact face defining opposite sides of the light emitting stack, the light emitting stack comprising a plurality of Ill-nitride layers, the Ill-nitride layers comprising a first semiconductor layer disposed towards the light emitting face of the light emitting stack, a second semiconductor layer disposed towards the contact face, and an active layer arranged between the first semiconductor layer and the second semiconductor, the active layer configured to generate light having a first wavelength, wherein the light emitting face and the contact face are parallel to each other and aligned with the plurality of Ill-nitride layers; a first electrical contact layer disposed on the light emitting stack and configured to be in electrical contact with the first semiconductor layer; a second array of electrical contacts disposed on the contact face of the light emitting stack, each second electrical contact defining a light emitting device between the first semiconductor layer and the second electrical contact, wherein each second electrical contact is spaced apart from other second electrical contacts to form a two-dimensional array of light emitting devices; and an anti-reflection layer disposed on the light emitting face, the anti-reflection layer configured to increase light extraction efficiency of light generated by the light emitting device layer.

2. The array of light emitting devices of claim 1, further comprising: an absorbing layer configured to absorb light of the first wavelength generated by the active layer; the absorbing layer disposed on at least a portion of the light emitting stack.

3. The array of light emitting devices of claim 2, wherein the absorbing layer is disposed on at least one sidewall face of the light emitting stack, the at least one sidewall face extending between the light emitting face and the contact face.

4. The array of light emitting devices of claim 2 or claim 3, wherein the absorbing layer is disposed on the light emitting face, wherein the absorbing layer comprises a plurality of openings on the light emitting face, each opening aligned with a second electrical contact such that light from each light emitting device is transmitted through a respective opening.

5. The array of light emitting devices of claim 2 or claim 3, wherein the absorbing layer is disposed in regions of the contact face between adjacent second electrical contacts of the second array of electrical contacts.

6. The array of light emitting devices of any one of claims 1 to 3, wherein the anti-reflection layer comprises a porous semiconductor layer having a surface porosity of at least 30%.

7. The array of light emitting devices of any one of claims 1 to 3, wherein the anti-reflection layer comprises a plurality of porous semiconductor sub-layers, wherein at least two of the plurality of porous semiconductor sub-layers differ in surface porosity.

8. The array of light emitting devices of any one of claims 1 to 3, wherein a pitch of each second electrical contact in the array of light emitting devices is no greater than 5 pm or 2 pm.

9. The array of light emitting devices of any one of claims 1 to 3, wherein the first electrical contact layer comprises a transparent conductive oxide disposed on the light emitting face.

10. The array of light emitting devices of claim 9, wherein the anti-reflection layer is arranged between the first electrical contact layer and the light emitting face. ​ 11. The light emitting device array of claim 9, wherein the first electrical contact layer is disposed between the anti-reflective layer and the light emitting face.

12. The light emitting device array of any one of claims 1 to 3, wherein the anti-reflective layer and the first electrical contact layer are configured to form a graded-index (GRIN) structure having anti-reflective and electrical contact functionality.

13. The light emitting device array of any one of claims 1 to 3, wherein the light emitting stack further comprises: a through-semiconductor portion disposed in the light emitting stack extending through the active layer between the first semiconductor layer and the contact face, and the first electrical contact layer is disposed on the contact face in electrical contact with the through-semiconductor portion.

14. The light emitting device array of any one of claims 1 to 3, wherein the first semiconductor layer comprises an n-type doped III-nitride; and / or the second semiconductor layer comprises a p-type doped III-nitride; and / or the active layer comprises a plurality of quantum well layers comprising III-nitride.

15. The light emitting device array of any one of claims 1 to 3, wherein the active layer extends as a continuous layer between at least two adjacent light emitting devices of the light emitting device array.

16. A method of forming a light emitting device array, comprising: forming a light emitting stack on a substrate face of a substrate, the light emitting stack having a light emitting face oriented toward the substrate face and a contact face on an opposite side of the light emitting stack, forming the light emitting stack comprising forming a plurality of III-nitride layers, the III-nitride layers comprising: a first semiconductor layer disposed toward the substrate face; a second semiconductor layer disposed toward the contact face of the light emitting stack; and an active layer disposed between the first semiconductor layer and the second semiconductor layer, the active layer configured to generate light having a first wavelength; wherein the light emitting face and the contact face of the light emitting stack are formed parallel to each other and aligned with the plurality of III-nitride layers; forming a second electrical contact array on the contact face of the light emitting stack, each second electrical contact defining a light emitting device between the first semiconductor layer and the second electrical contact, wherein each second electrical contact is spaced apart from other second electrical contacts to form a two-dimensional array of light emitting devices; removing the substrate from the light emitting stack; forming a first electrical contact layer on the light emitting stack, the first electrical contact layer configured to be in electrical contact with the first semiconductor layer; and forming an anti-reflective layer on the light emitting face, the anti-reflective layer configured to increase light extraction efficiency of light generated by the light emitting device layer.

17. The method of claim 16, further comprising forming an absorption layer on at least a portion of the light emitting stack, the absorption layer configured to absorb light of the first wavelength generated by the active layer.

18. The method of claim 16 or 17, wherein forming the anti-reflective layer comprises: forming a third semiconductor layer on the light emitting surface, the third semiconductor layer including a group III nitride and having a donor density of at least 1 x 1014cm-2; and 18 cm -3 -2; and porosity treating the third semiconductor layer to increase a surface porosity of the third semiconductor layer to at least 30%.

19. The method of claim 16 or 17, wherein A pitch of each second electrical contact formed in the array of light emitting devices is no greater than 5 pm or 2 pm.

20. The method of claim 16 or 17, wherein Forming the first electrical contact layer includes forming a transparent conductive oxide on the light emitting face.

21. The method of claim 20, wherein the anti-reflective layer is formed on the light emitting face, and then the first electrical contact layer is formed on the anti-reflective layer.

22. The method of claim 20, wherein the first electrical contact layer is formed on the light emitting face, and then the anti-reflective layer is formed on the first electrical contact layer.

23. The method of claim 16 or 17, wherein Forming the first electrical contact layer includes: forming a via semiconductor portion in the light emitting stack, the via semiconductor portion extending through the active layer between the first semiconductor layer and the contact face, and forming the first electrical contact layer on the contact face on the via semiconductor portion.

24. The method of claim 16 or 17, wherein forming the first semiconductor layer includes forming an n-type doped III- nitride; and / or forming the second semiconductor layer includes forming a p-type doped III- nitride; and / or forming the active layer includes forming a plurality of quantum well layers including III-nitride.

25. The method of claim 16 or 17, wherein the active layer is formed as a continuous layer extending between at least two adjacent light emitting devices of the array of light emitting devices.

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