Interrupt controller, system on chip, smart device and interrupt processing method

Abstract

The application provides an interrupt controller, a system on chip, a smart device and an interrupt processing method. The interrupt controller is controlled by a management control processor and comprises: an input port configured to receive an interrupt request from external hardware; an interrupt routing module configured to bypass output the interrupt request or route and convert the interrupt request into an interrupt instruction; and an output port configured to output the interrupt instruction to one or more functional application subsystems in a plurality of mutually isolated functional application subsystems.

Description

Technical Field

[0001] This invention relates to the field of computer systems, and in particular to interrupt controllers, system-on-a-chip, intelligent devices, and interrupt handling methods. Background Technology

[0002] With the growing trend towards system integration, multiple subsystems are typically integrated onto a single System-on-Chip (SoC), which is particularly useful for multi-functional systems like automobiles. For example, an in-vehicle system platform usually includes multiple functional application subsystems, such as cockpit systems, vehicle control systems, and driver assistance systems (e.g., ADAS / ADS systems), corresponding to human-machine interaction, vehicle control, and automated driving assistance functions, respectively. For safety reasons, these multiple functional systems are isolated, preferably at the hardware level, while allowing necessary controlled communication between systems.

[0003] In traditional interrupt controllers, interrupt instructions arbitrated by the interrupt controller are directly sent to the CPU. Therefore, the control of the interrupt controller and the application of interrupt instructions are integrated, which cannot meet the management function requirements of hierarchical and role separation. In addition, for hardware platforms with multiple isolated functional application subsystems, it is difficult to configure and process interrupt information according to the actual needs of the functional subsystems, thus making it difficult to achieve flexible configuration of the overall system architecture of the SoC. Summary of the Invention

[0004] This application provides an interrupt controller, a system-on-a-chip, a smart device, and an interrupt handling method.

[0005] The first aspect of this application relates to an interrupt controller controlled by a management control processor and includes: an input port configured to receive an interrupt request from external hardware; an interrupt routing module configured to bypass the interrupt request or route the interrupt request and convert it into an interrupt instruction; and an output port configured to output the interrupt instruction to one or more of a plurality of mutually isolated functional application subsystems.

[0006] In one embodiment, the input port includes an input signal line and a message input channel; wherein the input port is configured to: receive an interrupt signal as an interrupt request from one signal line or from multiple signal lines in parallel; and / or, receive an interrupt message as an interrupt request serially from the message input channel.

[0007] In one embodiment, the output port includes an output signal line and a message output channel; wherein the output port is configured to output a signal instruction as the interrupt instruction to one or more designated functional application subsystems via the output signal line, and / or to output a message instruction as the interrupt instruction to one or more designated functional application subsystems via the message output channel.

[0008] In one embodiment, the interrupt routing module is configured to, upon receiving the interrupt signal, by default bypass the interrupt signal without converting it into an interrupt instruction if no disable bypass instruction is received from the management control processor; and to route the interrupt signal and convert it into an interrupt instruction when a disable bypass instruction is received from the management control processor; and to route the interrupt message and convert it into an interrupt instruction when the interrupt message is received.

[0009] In one embodiment, the interrupt routing module is further configured to, based on the control of the management control processor, set the enable state and parameters of the input signal line, the enable state and parameters of the output signal line, the enable state of the message input channel and the message output channel, and the trigger mode of the interrupt controller.

[0010] In one embodiment, the interrupt controller further includes a buffer module contained in the message output channel; wherein, under the control of the management control processor, the message instruction is placed into the buffer module in a plurality of message output channels with a specified priority, and is output to a plurality of functional application subsystems in sequence according to the priority.

[0011] In one embodiment, the interrupt controller further includes a statistics module, which serves as an interface with the functional application subsystem and is configured to perform statistics on the interrupt requests and interrupt instructions.

[0012] The second aspect of this application relates to a system-on-a-chip, comprising: an interrupt controller according to the above embodiments; a management and control processor configured to control the interrupt controller; and a plurality of mutually isolated functional application subsystems configured to receive interrupt instructions according to the priority order of the interrupt instructions to implement the functions of a terminal application.

[0013] In one embodiment, the system-on-a-chip includes a plurality of cascaded interrupt controllers, and the interrupt request is routed and translated into the interrupt instruction via the plurality of interrupt controllers.

[0014] A third aspect of this application relates to smart devices, including a system-on-a-chip according to the above embodiments.

[0015] The fourth aspect of this application relates to an interrupt handling method applied to an interrupt controller, comprising the following steps based on the control execution of a management control processor: receiving an interrupt request from external hardware; bypassing the interrupt request or routing the interrupt request and converting it into an interrupt instruction; and outputting the interrupt instruction to one or more of a plurality of mutually isolated functional application subsystems.

[0016] According to the interrupt controller, system-on-a-chip, intelligent device, and interrupt handling method of this application, the interrupt instructions output by the interrupt controller directly interface with multiple isolated functional application subsystems through hardware, enabling the separation of interrupt control and usage, and achieving hierarchical and role-separated management of the system. Furthermore, the interrupt controller of this application is compatible with both signal-based and message-based input and output, supporting current mainstream signal-based interrupts while simultaneously implementing message-based interrupts. This allows for dynamic configuration of the system based on the actual needs of the functional application subsystems, improving the overall system's adaptability and security. Attached Figure Description

[0017] Figure 1 This is a block diagram of the overall structure of the interrupt controller according to an embodiment of this application;

[0018] Figure 2 This is a schematic diagram illustrating an exemplary application of an interrupt controller according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram illustrating an exemplary application of an interrupt controller according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of a system-on-a-chip according to an embodiment of this application;

[0021] Figure 5 This is a flowchart illustrating the overall operation of the system-on-a-chip according to an embodiment of this application.

[0022] Figure 6 This is a schematic diagram of a system-on-a-chip according to an embodiment of this application;

[0023] Figure 7 This is a flowchart of an interrupt handling method according to an embodiment of this application. Detailed Implementation

[0024] Current SOC systems mainly include: CPU (e.g., ARMv9, ARMv8, ARMv7, RISC-V, etc.), memory (e.g., SRAM, DDR, etc.), bus (e.g., AXI, AHB, APB, etc.), communication unit (e.g., UART, CAN / CANfd, GMAC / XGMAC, USB, PCIe, etc.), and external storage unit (Norflash, Nandflash, eMMC, UFS, etc.). For configurable SOCs with multiple functional application subsystems, the following core units are also included: address mapping unit, address reverse mapping unit, interrupt signal routing control unit, multi-channel interface unit supporting multiple functional application subsystems, and platform system management control unit.

[0025] For the signal transmission control unit in the core unit, the GIC series interrupt controller is currently commonly used in the ARM architecture, but it cannot meet our management needs for hierarchical and role-separated SOC. Therefore, this application provides a signal transmission control unit that separates interrupt control and usage, and is compatible with configurable hardware platforms that support multiple functional application subsystems.

[0026] The interrupt controller according to this application can also be called a "signal routing unit," or InterruptRouteUnit (hereinafter referred to as IRU in this application). The IRU is controlled by a management control processor and interacts with multiple functional application subsystems to output interrupt instructions to the functional application subsystems. In this application, the management control processor can also be called a "management control unit," or ManageControlUnit (hereinafter referred to as MCU in this application). The multiple functional application subsystems are physically separated in hardware, and the multiple functional application subsystems can perform necessary controlled inter-system communication. For example, in an in-vehicle SOC, the multiple functional application subsystems can be a cockpit system, a vehicle control system, a driver assistance system, etc., and the cockpit system and the driver assistance system can share relevant parameters of the current vehicle operating status. In this application, the functional application subsystem can also be called an Application Processing System (hereinafter referred to as APS in this application). The APS and the MCU are independent of each other, physically separated in hardware, and may even be heterogeneous CPU systems. Furthermore, the APS only needs to implement specific functions, and each APS includes a processor as its core component. The IRU interacts with both the MCU and the APS. Specifically, the IRU is controlled by the MCU to process interrupt requests and output interrupt instructions to the APS.

[0027] See Figure 1This diagram illustrates the overall structural block diagram of an IRU 100 according to an embodiment of this application. The IRU 100 includes an input port 110, an interrupt routing module 130, and an output port 150. The input port 110 can be connected to external hardware and configured to receive interrupt requests from the external hardware. It should be understood that the input port 110 can be directly connected to the external hardware or connected via an intermediate element. For example, in the cascaded mode described later, the input port 110 can be connected to the external hardware via another IRU. The external hardware is the interrupt source that generates the interrupt, and the IRU 100 receives the interrupt request from the external hardware through the input port 110. When the IRU 100, MCU 200, and multiple APSs are all concentrated on the same SOC, the external hardware can also be a hardware module integrated on the same SOC but physically separate from the aforementioned modules, or it can be a device outside the SOC. In particular, the external hardware can also be another IRU; for example, in the case of multiple cascaded IRUs (described in detail later), an interrupt instruction output from one IRU can be used as an interrupt request input to another IRU.

[0028] Interrupt routing module 130 is the core module of the interrupt controller IRU 100 of this application. It is configured to bypass interrupt requests or route interrupt requests and convert them into interrupt instructions through the bypass unit 132 included therein. For example, an interrupt request can be bypassed through bypass port 160. Output port 150 can be connected to multiple isolated APSs and configured to output interrupt instructions to one or more APSs. In this application, multiple isolated APSs refer to hardware isolation between multiple APSs, but multiple APS systems can be controlled to communicate with each other. It should be understood that output port 150 can be directly connected to an APS or connected to an APS through an intermediate element. For example, in the cascading mode described later, output port 150 can be connected to an APS via another IRU. Interrupt instructions can be set with a priority order, and output port 150 outputs them to the APS according to the priority order. IRU 100 can output interrupt instructions to each of the multiple APSs to which it is connected through output port 150, or it can output interrupt instructions to a subset of the multiple APSs to which it is connected. Input port 110, interrupt routing module 130 and output port 150 are communicatively connected.

[0029] According to the above configuration, the input port 110, interrupt routing module 130, and output port 150 in the IRU 100 are all controlled by the MCU, and perform corresponding processing based on the MCU's configuration. The output ports directly interface with the corresponding interfaces in the APS, so interrupt instructions are directly applied to the APS, which is beneficial for dynamically and flexibly configuring the IRU 100 according to the specific application requirements of the APS. In this way, the control of interrupts (controlled by the MCU) and their use (used by the APS) can be separated. Since the MCU and APS are separated in hardware and operation control, it is easy to implement hierarchical and role-separated management of the system.

[0030] The following will refer to Figure 2 A schematic diagram illustrating an exemplary application of the IRU 100 according to an embodiment of this application.

[0031] In one embodiment, input port 110 may include input signal lines and message input channels. Multiple sets of input signal lines and message input channels may be used to input interrupt requests from external hardware to IRU 100. An interrupt request may include an interrupt signal and an interrupt message. An interrupt signal is a signal with different trigger types, such as edge-triggered and level-triggered, where edge-triggered includes rising-edge triggering and falling-edge triggering, and level-triggered includes high-level triggering and low-level triggering. The trigger types of interrupt signals are well known to those skilled in the art and will not be elaborated upon here. An interrupt message is an encoded message that may include the specific content to be transmitted by the signal. After receiving an interrupt message, IRU 100 decodes the encoding definition of the interrupt message to obtain the input signal line ID. The input signal line ID refers to the number of the input signal line, used to indicate which input signal line the interrupt request comes from, and thus indicating the interrupt source from which the interrupt request originates. Exemplarily, the input signal line ID is encoded and defined in the interrupt message; that is, a specific encoding in the interrupt message corresponds to the input signal line ID. For example, an interrupt message includes an interrupt message ID value, which corresponds to an input signal line ID. Taking eight input signal lines as an example, their signal line IDs are line0, line1, line2...line8, and the corresponding interrupt message ID values ​​are, for example, 0, 1, 2...8. By decoding the encoding definition of the interrupt message, the corresponding input signal line ID can be obtained, and from this, the external hardware that caused the interrupt can be identified.

[0032] When the interrupt request received by the IRU includes an interrupt signal, the interrupt signal is input to the IRU100 via an input signal line, specifically to the interrupt routing module 130, triggering the IRU100 to operate. Multiple parallel input signal lines can exist, allowing multiple interrupt signals to be input to the IRU100 in parallel via these lines. In other words, input port 110 is configured to receive interrupt signals as interrupt requests from one signal line or from multiple signal lines in parallel. Prioritizing signal line-based input and triggering the IRU based on the input interrupt signal facilitates easier integration with current mainstream interrupt signal protocols. Figure 2 In the example, we will use the interrupt request input to IRU 100 as an example of an interrupt signal.

[0033] When the interrupt request received by the IRU includes an interrupt message, the interrupt message is input to the IRU100 through the message input channel, specifically to the interrupt routing module 130, triggering the IRU100 to operate. The interrupt message is also input to the IRU110 in serial mode through the message input channel; in other words, input port 110 is configured to serially receive interrupt messages as interrupt requests from the message input channel. The situation where the interrupt request received by the IRU is an interrupt message is common in the cascading of IRUs 110, which will be described in detail later.

[0034] In one embodiment, output port 150 may include output signal lines and message output channels. Multiple sets of output signal lines and message output channels are available for outputting interrupt instructions obtained after the interrupt request is processed and converted by IRU 100 to the APS. The interrupt instructions obtained after the interrupt request is converted by IRU 100 include signal instructions and message instructions. A signal instruction is a signal with different trigger types, such as edge-triggered and level-triggered. Edge-triggered signals include rising-edge triggering and falling-edge triggering, while level-triggered signals include high-level triggering and low-level triggering. The trigger types of interrupt signals are well known to those skilled in the art and will not be elaborated upon here. A message instruction is an encoded message that may include the specific content to be transmitted by the signal. The output signal line ID can be obtained by decoding. The output signal line ID refers to the number of the output signal line, indicating which output signal line the interrupt instruction will be output to the corresponding APS. For example, the output signal line ID is encoded and defined in the message instruction; that is, a specific code in the message instruction corresponds to the output signal line ID. For example, a message instruction includes a message instruction ID value, which corresponds to an output signal line ID. Taking eight output signal lines as an example, their IDs are line0, line1, line2...line8, and the corresponding message instruction ID values ​​are, for example, 0, 1, 2...8. By decoding the encoding definition of the message instruction, the corresponding output signal line ID can be obtained, and from this, it can be determined which specific APS the message instruction will be output to.

[0035] When the interrupt instruction includes a signal instruction, the output port 150 of the IRU 100 can be configured to output the signal instruction, which serves as the interrupt instruction, to one or more APSs via output signal lines, thereby triggering the functional operation of the APSs. In this case, each APS receiving the signal instruction is connected to the IRU 100 via at least one signal line. When multiple output signal lines exist, these lines can be assigned priorities, and the signal instruction is output to the APS according to the priority of the signal lines.

[0036] When the interrupt command includes a message command, the output port 150 of the IRU 100 can be configured to output the message command, which serves as the interrupt command, to one or more APSs via the message output channel, triggering the functional operation of the APSs through the message command. In this case, each APS receiving the message command is connected to the IRU via at least one message output channel. For example, for each APS receiving the interrupt command, it is connected to the IRU 100 via an output signal line and one of the message output channels, and an interrupt is initiated for that APS using either a signal command or a message command accordingly. Figure 2In the example shown, the first APS and the second APS are connected to the IRU 100 via the message output channel and receive message commands output from the IRU 100 accordingly, while the third APS is connected to the IRU 100 via the output signal line and receives signal commands output from the IRU 100 accordingly.

[0037] It should be understood that among multiple isolated APSs, some APSs may be connected to IRU 100 via output signal lines, while the remaining APSs may be connected to IRU 100 via message output channels; in other embodiments, all APSs among multiple isolated APSs may be connected to IRU 100 via message output channels.

[0038] In one embodiment, the interrupt routing module 130 is configured to, upon receiving the interrupt signal, bypass the interrupt signal without converting it into an interrupt command if no disable bypass instruction is received from the MCU 200. In other words, the default processing of the received interrupt signal by the interrupt routing module 130 is to bypass the interrupt signal through the bypass unit 132, i.e., abandon the routing processing of the interrupt signal. That is, the interrupt signal input to the IRU 100 is not processed by the routing conversion unit 134 (described later) and is not routed to the APS. When a disable bypass instruction is received from the MCU 200, the interrupt signal is passed to the routing conversion unit 134 for further processing, specifically, the interrupt signal is routed and converted into an interrupt command. That is, only when the MCU 200 sends a disable bypass instruction to the IRU 100 will the input interrupt signal not be bypassed and be passed to the routing conversion unit 134 for further processing. The routing conversion unit 134 routes and converts the input interrupt signal or interrupt message according to the pre-set routing conversion rules to generate an interrupt command and route it to the corresponding output port. The routing conversion unit 134 converts the input interrupt request into target content and routes it to the destination output signal line or message output channel. The conversion rules and destination are set by the MCU 200 for the IRU 100.

[0039] In the above embodiments, bypass processing is only applied when the input interrupt request is an interrupt signal. When IRU100 receives an interrupt message, the interrupt message will not be bypassed, but will necessarily be passed to the routing conversion unit 134 for further processing. Specifically, the interrupt message is routed and converted into an interrupt instruction.

[0040] In one embodiment, the interrupt routing module 130 is further configured to, based on the control of the MCU 200, set the enable state and parameters of input signal lines, the enable state and parameters of output signal lines, the enable state of message input channels and output message channels, and the trigger mode of the IRU 100. Each input signal line is assigned a specific ID, namely the input signal line ID (signalID). The enable state of an input signal line refers to whether the input signal line is activated to receive interrupt signals. Only when the enable state of the input signal line is active can the input signal line receive interrupt signals. The parameters of the input signal line include the trigger type (TriggerType) and the trigger level (TriggerLevel). The trigger type is, for example, level trigger or edge trigger, and the trigger level is, for example, high level or low level. Only when the enable state of the input signal line is active, and the trigger type and trigger level of the interrupt signal input through the signal line are consistent with the corresponding parameters set by the interrupt routing module 130, can the interrupt signal be input to the interrupt routing module 130 through the input signal line.

[0041] Each output signal line is also assigned a specific output signal line ID. The enable state of an output signal line refers to whether it is activated for outputting interrupt signals. An output signal line can only be used to output interrupt signals when its enable state is active. The parameters of an output signal line include trigger type and trigger level. The trigger type can be, for example, level-triggered or edge-triggered, and the trigger level can be, for example, high-level or low-level. When the enable state of an output signal line is active, a signal command consistent with the parameter configuration of that output signal line is output to the APS through that output signal line.

[0042] The enable status of the message input channel and the message output channel refer to whether the message input channel and the message output channel are activated to input interrupt messages or output interrupt commands, respectively. Only when the corresponding channel is active can it be used to input / output messages.

[0043] The triggering mode of the IRU 100 refers to whether the IRU 100 triggers its operation in response to an interrupt message or an interrupt signal, corresponding to message triggering and signal triggering, respectively. In practical applications, the IRU 100 can start operating in response to receiving one or both of an interrupt message and an interrupt signal. Exemplarily, this is achieved by enabling or setting an input signal line.

[0044] It is important to note that although the interrupt routing module 130 of the IRU 100 is described above as configuring the enable states and parameters of the input and output ports, as well as the trigger mode of the interrupt controller, the interrupt routing module 130 actually provides an interface with the MCU 200. The MCU 200 uses this interface to configure the settings of the interrupt routing module 130 as described above. That is, the MCU 200 controls the interrupt routing module 130, thereby the interrupt routing module 130 controls the enable states, parameters, and trigger modes of the input and output ports of the IRU 100.

[0045] On the other hand, MCU 200 also implements the configuration of routing conversion rules. MCU 200 configures the routing conversion rules of routing conversion unit 134. Based on these routing conversion rules, conversion unit 134 routes interrupt signals and converts them into interrupt instructions. For example, the MCU 200 controls the rules for IRU 100 to output input interrupt requests as interrupt instructions, including the corresponding path settings from the input port to the output port and the corresponding conversion settings (e.g., converting interrupt signals into message instructions, interrupt messages into signal instructions, interrupt signals into signal instructions, or interrupt messages into message instructions). This enables IRU 100 to accurately convert and route interrupt messages or interrupt signals when they arrive via the routing conversion unit. For example, MCU 200 can configure the source port (SrcPort, representing the input port of the interrupt signal, such as the input signal line ID), destination port (DestPort, representing the output port of the signal command, such as the output signal line ID), source ID (SrcID, representing the input port of the interrupt message, such as the interrupt message ID value of the interrupt message), destination ID (DestID, representing the output port of the message command, such as the message command ID value of the message command), as well as the routing relationships between them and the priority order of output interrupt commands. Based on the configuration of MCU 200, IRU 100 specifies which functional application subsystem the interrupt command should be output to. MCU 200 also configures the parameters containing routing rules to the routing conversion unit 134 in interrupt routing module 130 through the interface with interrupt routing module 130. In short, the settings of the input ports, routing and conversion processing, and output ports of IRU 100 are all pre-configured by MCU 200.

[0046] In one embodiment, the IRU 100 further includes a statistics module 170, which can be implemented as a user interface for the APS and configured to perform statistics on interrupt requests and interrupt instructions. See also Figure 2The shaded arrows indicate that the APS can interact with the IRU100's statistics module 170 to perform statistics on interrupt requests and interrupt instructions, including recording the status and statistical information of interrupt requests and interrupt instructions. This information can be read, cleared, and reset by the APS 300. The accessible area of ​​the APS 300 to the IRU100 is set by the MCU.

[0047] exist Figure 2 The example illustrates three transmission paths for the input interrupt signal: bypass output, message command output via the message output channel, and signal command output via the output signal line. The specific process is as follows: The interrupt signal is input to the interrupt routing module 130 of the IRU 100 via the input signal line and bypassed by the bypass unit 132. On the other hand, signals not bypassed are first preprocessed based on parameter configuration in the routing conversion unit 134 and then routed and converted according to predetermined routing conversion rules, generating message commands and / or signal commands, which are then output to each APS accordingly via the message output channel and output signal line.

[0048] According to embodiments of this application, interrupt instructions are directly connected to the APS via hardware, enabling the separation of interrupt control and usage, and facilitating hierarchical and role-based management of the system. In practical applications, interrupt instructions are typically output as message instructions, via a message output channel to the APS. Thus, the APS handles interrupts via messages, which facilitates dynamic configuration of system functions based on actual needs, improving the overall system's adaptability and security.

[0049] Despite Figure 2 The following description uses input interrupt signals, output message commands, and signal commands as examples. However, it should be understood that, according to the IRU 100 of this application, either or both of interrupt messages and interrupt signals can be input, and after routing and conversion through predetermined routing conversion rules, either or both of message commands and signal commands can be output. For example, the IRU 100 can receive interrupt messages, and output signal commands after conversion and processing.

[0050] See further Figure 3 In one embodiment, the IRU 100 further includes a buffer module 190. The buffer module 190 may be included within a message output channel as a component of that channel. Under the control of the MCU 200, message instructions are placed into the respective buffer modules 190 of multiple message output channels, each with a specified priority, and then sequentially output to multiple functional application subsystems according to that priority. Thus, the message instructions are sequentially output to the APS for processing according to their priority.

[0051] exist Figure 3 In the example, the cache module 190 includes multiple message memories. These message memories are, for example, FIFO memories. For instance, each message output channel integrates its own FIFO memory. Each FIFO memory stores a message queue, and the number of message units in the queue is adjustable, greater than one, and is not specifically limited. The priority order of message queues being output to the APS is configured by weights set by the MCU 200. In the default mode without special settings, the priority is determined by the message output channel number.

[0052] Figure 4 This is a schematic diagram of a System-on-a-Chip (SoC) according to this application. The SoC integrates an IRU 100, an MCU 200, and multiple isolated APS 300s as described in the above embodiments. The IRU 100 interacts with both the MCU 200 and the APS 300, and is controlled by the MCU 200. The interaction and control between the IRU 100, the MCU 200, and the APS 300 are as described in the above embodiments and will not be repeated here. The APS 300 can be configured to receive interrupt instructions from the IRU 100 according to the priority of interrupt instructions to implement the functions of the terminal application. For example, when the APS 300 is a cockpit system in a vehicle, if external hardware generates an interrupt request requiring the cockpit system to adjust the seat position, under the control of the MCU 200, the IRU 100 directly outputs the interrupt instruction to the cockpit system, thereby enabling the cockpit system to adjust the seat position in response to the interrupt instruction. The APS 300 can also interact with the MCU 200 to read, clear, and reset the status and statistics of interrupt requests and interrupt instructions.

[0053] refer to Figure 5 The overall operation flow of the SOC is described. In S501, the SOC powers on and starts running. In S502, the MCU 200 starts accordingly and loads the configuration parameter file of the IRU 100. The configuration parameter file of the IRU is used to configure the IRU 100. The configuration implemented by the IRU 100 based on this file includes, for example, the enable state and parameters of the input signal lines, the enable state and parameters of the output signal lines, the enable state of the message input channel and the message output channel, the trigger mode of the IRU, the routing conversion rules, the priority order setting rules, and the areas of the IRU that can be accessed when the APS 300 interacts with the IRU 100. These specific configurations are described in detail in the above embodiments and will not be repeated here.

[0054] In S503, MCU 200 configures IRU 100 based on the configuration parameter file, and IRU 100 completes the corresponding configuration work. Accordingly, IRU 100 completes one or more of the following configurations: enable state and parameters of input signal lines, enable state and parameters of output signal lines, enable state of message input and message output channels, IRU trigger mode, routing conversion rules, priority order setting rules, and the IRU area accessible when APS 300 interacts with IRU 100. These specific configurations are described in detail in the above embodiments and will not be repeated here. The control of IRU 100 by MCU 200 can be manifested as MCU 200 configuring IRU 100 based on the configuration parameter file.

[0055] In S504, MCU 200 sends a disable bypass command to IRU 100. Only when IRU 100 receives the disable bypass command from MCU 200 will the interrupt signal be processed by the routing conversion unit in IRU 100, i.e., converted into an interrupt command according to predetermined rules and routed to the corresponding output port. In this embodiment, IRU 100 only needs to determine whether to bypass the interrupt signal based on whether it has received the disable bypass command from MCU 200 when the interrupt request input to IRU 100 includes an interrupt signal; when the interrupt request input to IRU 100 is an interrupt message, the interrupt message will not be bypassed but will necessarily be passed to the routing conversion unit 134 for subsequent routing conversion processing.

[0056] In S505, IRU 100 outputs an interrupt command to APS 300. IRU 100 routes the interrupt request according to a predetermined routing conversion rule and converts it into an interrupt command, which is then output to APS 300 through output port 150. In this embodiment, output port 150 is directly connected to APS 300, so the interrupt command output from IRU 100 is directly applied to APS 300.

[0057] In S506, APS 300 receives interrupt instructions and performs the corresponding functions according to the interrupt instructions.

[0058] See further Figure 6 In one embodiment, the SOC according to the above embodiments includes a plurality of cascaded interrupt controllers, the configuration of each interrupt controller referring to the description of the above embodiments. Figure 6 In the example shown, IRU 100-1, IRU 100-2...IRU 100-n are cascaded sequentially. Figure 6In the example shown, the input port of IRU 100-1 is directly connected to external hardware, the output port of IRU 100-1 is directly connected to the input port of IRU 100-2, the output port of IRU 100-2 is directly connected to the input port of IRU 100-3, and so on, with the output port of IRU 100-n directly connected to the APS.

[0059] IRU 100-1 receives interrupt requests (e.g., interrupt messages or interrupt signals) from external hardware via its input ports, routes the interrupt requests, and converts them into interrupt instructions (message instructions in this embodiment). The message instructions output by IRU 100-1 serve as inputs to IRU 100-2, which is cascaded with IRU 100-1. IRU 100-2 receives the message instructions output by IRU 100-1 as interrupt requests via its input port (message input channel in this example), routes and converts them, and outputs interrupt instructions (message instructions in this example) from IRU 100-2. This process continues until IRU 100-n outputs interrupt instructions (which can be signal instructions or message instructions) to the APS via its output port.

[0060] exist Figure 6 In the example shown, in cascaded mode, except for IRU 100-1 which is directly connected to external hardware, the remaining IRUs 100-2 to IRU 100-n are configured to serially receive interrupt messages from the message input channel; except for IRU-n which is directly connected to the APS, the remaining IRUs are configured to serially output message instructions from the message output channel. Overall, interrupt requests input from external hardware to the cascaded IRUs can be either interrupt messages or interrupt signals, or both; interrupt instructions output from the cascaded IRUs to the APS can be either signal instructions or message instructions, or both.

[0061] In cascading mode, the number of APS 300 units can be one or more. It's important to note that the MCU 200, as the sole management unit in the SOC, can control multiple cascaded IRUs from a single MCU 200.

[0062] This application also provides a smart device, including a System-on-Chip (SOC) according to the above embodiments. Exemplarily, the smart device can be a vehicle. Accordingly, multiple isolated Advanced Driver Assistance Systems (APS) can be, for example, a cockpit system, a vehicle control system, or a driver assistance system (such as an ADAS / ADS system), respectively corresponding to functions such as human-machine interaction, vehicle control, and automated assisted driving. Each system directly interfaces with an interrupt controller in hardware, and interrupt instructions are directly output to each functional application subsystem through output ports connected to those subsystems.

[0063] This application also provides an interrupt handling method, which can be applied to the interrupt controller described in the above embodiments. Figure 7 As shown, the interrupt handling method includes, as follows: Figure 7 Steps S710-S750 are shown.

[0064] In S710, an interrupt request is received from external hardware. For example, the interrupt controller receives the interrupt request from external hardware via an input port. In S730, the interrupt request is either bypassed and output, or the interrupt request is routed and converted into an interrupt instruction. In S750, the interrupt instruction is output to one or more of a plurality of isolated functional application subsystems. After completing the relevant interrupt handling, the functional subsystem clears the interrupt source.

[0065] In one embodiment, receiving an interrupt request from external hardware includes: receiving an interrupt signal as the interrupt request from one input signal line or from multiple input signal lines in parallel; and / or, receiving an interrupt message as the interrupt request serially from a message input channel.

[0066] In one embodiment, outputting the interrupt instruction to one or more of a plurality of mutually isolated functional application subsystems includes: outputting a signal instruction as the interrupt instruction to one or more designated functional application subsystems via an output signal line, and / or, outputting a message instruction as the interrupt instruction to one or more designated functional application subsystems via a message output channel.

[0067] In one embodiment, bypassing the interrupt request or routing the interrupt request and converting it into an interrupt instruction includes: when the interrupt signal is received, if no disable bypass instruction is received from the management control processor, by default, the interrupt signal is bypassed and not converted into an interrupt instruction; when a disable bypass instruction is received from the management control processor, the interrupt signal is routed and converted into an interrupt instruction; and when the interrupt message is received, the interrupt message is routed and converted into an interrupt instruction.

[0068] In one embodiment, the interrupt handling method further includes: setting the enable state and parameters of the input signal line, the enable state and parameters of the output signal line, the enable state of the message input channel and the message output channel, and the trigger mode of the interrupt controller based on the control of the management control processor.

[0069] In one embodiment, the interrupt handling method further includes: under the control of the management control processor, message instructions are placed into a buffer module in a plurality of message output channels with a specified priority order, and output to a plurality of functional application subsystems in sequence according to the priority order.

[0070] In one embodiment, the interrupt handling method further includes: collecting statistics on the interrupt request and the interrupt instruction to generate statistical information, and interacting with one or more functional application subsystems to collect the statistical information.

[0071] In this application, the features described in the embodiments of the interrupt controller can be applied to the interrupt handling method. Specific limitations regarding the interrupt handling method can be found in the above-described limitations of the interrupt controller, and will not be repeated here.

[0072] According to the interrupt controller, system-on-a-chip, and smart device embodiments of this application, the interrupt instructions output by the interrupt controller directly interface with multiple isolated functional application subsystems through hardware, enabling the separation of interrupt control and usage, and achieving hierarchical and role-separated management of the system. Furthermore, the interrupt controller of this application is compatible with both signal-based and message-based input and output, supporting both current mainstream signal-based interrupts and message-based interrupts. This allows for dynamic configuration of the system based on the actual needs of the functional application subsystems, improving the overall system's adaptability and security.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An interrupt controller, controlled by a management control processor, and including: An input port configured to receive an interrupt request from external hardware, the input port including an input signal line and a message input channel, the input port being configured to receive an interrupt signal as the interrupt request from one input signal line or from multiple input signal lines in parallel; And / or, serially receive an interrupt message as the interrupt request from the message input channel; An interrupt routing module is configured to either bypass the interrupt request or route the interrupt request and convert it into an interrupt command. as well as An output port is configured to output the interrupt instruction to one or more of a plurality of mutually isolated functional application subsystems. The output port includes an output signal line and a message output channel. The output port is configured to output a signal instruction as the interrupt instruction to one or more designated functional application subsystems through the output signal line, and / or to output a message instruction as the interrupt instruction to one or more designated functional application subsystems through the message output channel. The management and control processor configures the input ports, routing and conversion processing, and output ports of the interrupt controller. It is separate from the multiple functional application subsystems in terms of hardware and operation control. The interrupt messages and message instructions are encoded messages.

2. The interrupt controller according to claim 1, wherein, The interrupt routing module is configured as follows: When the interrupt signal is received, if no disable bypass instruction is received from the management and control processor, the interrupt signal is bypassed and not converted into an interrupt instruction by default; when a disable bypass instruction is received from the management and control processor, the interrupt signal is routed and converted into an interrupt instruction. Upon receiving the interrupt message, the interrupt message is routed and converted into the interrupt instruction.

3. The interrupt controller according to claim 1, wherein, The interrupt routing module is further configured to, based on the control of the management control processor, set the enable state and parameters of the input signal line, the enable state and parameters of the output signal line, the enable state of the message input channel and the message output channel, and the trigger mode of the interrupt controller.

4. The interrupt controller according to claim 1 further includes a buffer module contained in the message output channel; in, Under the control of the management and control processor, the message instruction is placed into a cache module in one of the multiple message output channels with a specified priority, and is output to one of the multiple functional application subsystems in sequence according to the priority.

5. The interrupt controller according to claim 1 further includes a statistics module, which serves as an interface with the functional application subsystem and is configured to perform statistics on the interrupt requests and the interrupt instructions.

6. System-on-a-chip, including: Interrupt controller according to any one of claims 1-5; The management control processor is configured to control the interrupt controller; as well as The multiple isolated functional application subsystems are configured to receive interrupt instructions according to the priority order of the interrupt instructions in order to realize the functions of the terminal application.

7. The system-on-a-chip according to claim 6, wherein, The interrupt controllers include multiple cascaded interrupt controllers, and the interrupt request is routed and converted into the interrupt instruction via the multiple interrupt controllers.

8. A smart device, including a system-on-a-chip according to claim 6 or 7.

9. An interrupt handling method, applied to an interrupt controller, including the following steps based on the control execution of the management control processor: The system receives interrupt requests from external hardware via an input port, which includes an input signal line and a message input channel. The input port is configured to receive an interrupt signal as the interrupt request from one input signal line or from multiple input signal lines in parallel. And / or, serially receive an interrupt message as the interrupt request from the message input channel; The interrupt request can be bypassed or output, or the interrupt request can be routed and converted into an interrupt instruction. as well as The interrupt instruction is output to one or more of the multiple isolated functional application subsystems through an output port. The output port includes an output signal line and a message output channel. The output port is configured to output a signal instruction as the interrupt instruction to one or more designated functional application subsystems through the output signal line, and / or to output a message instruction as the interrupt instruction to one or more designated functional application subsystems through the message output channel. The management and control processor configures the input ports, routing and conversion processing, and output ports of the interrupt controller. It is separate from the multiple functional application subsystems in terms of hardware and operation control. The interrupt messages and message instructions are encoded messages.

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