Display substrate, display panel, and display device

Abstract

The present disclosure provides a display substrate, a display panel, and a display device. In the display substrate, a first trace extends from a display driver chip bonding area through a corresponding fan-out area into a display area. A plurality of first traces are spaced apart in the fan-out area and the display area, and the first traces extend in a column direction in the display area; a second trace extends from the display driver chip bonding area through the corresponding fan-out area into the display area. The second trace does not overlap with the first trace, and the second trace extends in the column direction in the display area. All the second traces extending from any one display driver chip bonding area define a smallest enclosing rectangle; a third trace is located in the display area and extends in a row direction. The second trace and the third trace are located in different conductor layers, and the second trace is connected to the third trace in a one-to-one correspondence through vias; a fourth trace extends in the column direction and is distributed between any two adjacent first traces outside the latest enclosing rectangle.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate, a display panel, and a display device. Background Art

[0002] This section aims to provide background or context for the embodiments described in the claims. The description herein is not admitted to be prior art merely because it is included in this section.

[0003] In order to reduce the border size of an e-reader, both the gate lines and data lines in the display substrate are directly led out from the same display driver chip bonding area, without the need to provide a gate driver on array (GOA). Summary of the Invention

[0004] The present disclosure provides a display substrate, a display panel, and a display device.

[0005] The present disclosure adopts the following technical solutions: A display substrate is divided into at least one display driver chip bonding area, at least one fan-out area corresponding to the display driver chip bonding area one by one, and a display area. All of the at least one display driver chip bonding areas are located on the same side of the display area, and the fan-out area is located between the corresponding display driver chip bonding area and the display area;

[0006] The display substrate includes: a plurality of first traces, a plurality of second traces, a plurality of third traces, and a plurality of fourth traces;

[0007] The plurality of first traces extend from the display driver chip bonding area through the corresponding fan-out area into the display area. The plurality of first traces are spaced apart in the fan-out area and the display area, and the first traces extend along the column direction in the display area;

[0008] The plurality of second traces extend from the display driver chip bonding area through the corresponding fan-out area into the display area. The second traces do not overlap with the first traces, and the second traces extend along the column direction in the display area. All the second traces extending from any one display driver chip bonding area define a minimum bounding rectangle;

[0009] The plurality of third traces are located in the display area and extend along the row direction. The plurality of second traces and the plurality of third traces are respectively located in different conductor layers, and the plurality of second traces are connected to the plurality of third traces in a one-to-one correspondence through vias;

[0010] The plurality of fourth traces extend along the column direction and are distributed between any two adjacent first traces outside the minimum bounding rectangle.

[0011] In some embodiments, the multiple second traces extend from the display driver chip bonding area through the middle area of the corresponding fan-out area into the display area, and the multiple fourth traces are distributed on both sides of the minimum bounding rectangle along the row direction.

[0012] In some embodiments, the first trace is a gate line, and the second trace and the corresponding third trace form a data line; or,

[0013] the first trace is a data line, and the second trace and the corresponding third trace form a gate line.

[0014] In some embodiments, the first traces are equidistantly arranged along the row direction in the display area, and the number of second traces between adjacent two first traces and the number of fourth traces between adjacent two first traces are the same.

[0015] In some embodiments, the third traces connected by the second traces between adjacent first traces are continuously distributed.

[0016] In some embodiments, the fourth traces are floating or grounded.

[0017] In some embodiments, the first trace, the second trace, and the fourth trace are arranged on the same layer, and the third trace and the first trace are located in different conductor layers.

[0018] The present disclosure adopts the following technical solution: A display panel includes the aforementioned display substrate.

[0019] The present disclosure adopts the following technical solution: A display device includes the aforementioned display panel.

[0020] In some embodiments, the display device includes an e-reader. Description of the Drawings

[0021] Figure 1 is a schematic diagram of the distribution of some pads of a display driver chip in the related art.

[0022] Figure 2 is a schematic diagram of the structure of a display device in the related art, in which some traces in the display driver chip and the display substrate are shown.

[0023] Figure 3 is Figure 2 a schematic diagram of the distribution of parasitic capacitances in the shown display device.

[0024] Figure 4 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure, in which some traces in the display driver chip and the display substrate are shown.

[0025] Figure 5It is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.

[0026] Figure 6 It is a comparison diagram of the display effects between the display device according to an embodiment of the present disclosure and the display device in the related art.

[0027] Among them, the reference numerals are as follows: IC1, IC2, display driver chips; P1, first pad; P2, second pad; H, via; AA, display area; L1, first trace; L2, second trace; L3, third trace; L4, fourth trace; M, minimum bounding rectangle; 1, substrate; 2, insulating layer. Detailed implementation manners

[0028] The following further describes the present disclosure in conjunction with the embodiments shown in the drawings.

[0029] It should be noted that for convenience of description, in the present disclosure, when a trace is located between two other traces, it means that the positive projection of the former on the plane where the display substrate is located is located between the positive projections of the latter on the plane where the display substrate is located.

[0030] Figure 1 It is a schematic diagram of the distribution of some pads of the display driver chips IC1 and IC2 in the related art. The display driver chips IC1 and IC2 have a plurality of first pads P1 and a plurality of second pads P2. The first pads P1 are distributed in two end regions and a middle region along the length direction of the display driver chips IC1 and IC2, and the second pads P2 are distributed in the middle region along the length direction of the display driver chips IC1 and IC2. The first pads P1 are used to connect the gate lines in the display substrate, and the second pads P2 are used to connect the data lines in the display substrate.

[0031] Figure 2 It is a schematic structural diagram of a display device in the related art, in which, some traces in the display driver chips IC1 and IC2 and the display substrate are shown.

[0032] In this display device, the first trace L1 is connected to the first pad P1. The first trace L1 serves as the gate line of the display substrate. The first trace L1 is approximately equally spaced in the fan-out area.

[0033] The second trace L2 is connected to the second pad P2. The second trace L2 is connected to the third trace L3 through the via H. The second trace L2 and the third trace L3 serve as the data lines of the display substrate.

[0034] Since the second pad P2 is distributed in the middle region in the length direction of the display driving chips IC1 and IC2, the second trace L2 and the first trace L1 have an overlapping region, increasing the parasitic capacitance between the second trace L2 and the first trace L1, increasing the load on the display driving chips IC1 and IC2, reducing the charging ability of the display driving chips IC1 and IC2 for the gate lines and data lines, and increasing the rise time and fall time of the signals on the gate lines and data lines.

[0035] To make the display effect of the display device more uniform, further referring to Figure 2 , the vias H connecting the second trace L2 and the third trace L3 are arranged approximately along an inclined straight line.

[0036] The same second trace L2 may intersect with multiple first traces L1 in the fan-out region, which is more likely to cause signal crosstalk and affect the display effect.

[0037] Figure 3 is Figure 2 The schematic diagram of the distribution of the parasitic capacitance in the display device shown, where Figure a is the distribution diagram of the parasitic capacitance of the data line, and Figure b is the distribution diagram of the parasitic capacitance of the gate line. It can be found that whether it is the data line or the gate line, there are mutation positions in their parasitic capacitance, which makes the driving ability of the gate line or data line at the mutation position quite different from that of the surrounding gate lines or data lines, thus generating visible vertical or horizontal line defects.

[0038] Figure 4 is the schematic structural diagram of the display device of the present disclosure embodiment, where part of the traces in the display driving chips IC1 and IC2 and the display substrate are shown.

[0039] Referring to Figure 4 , the present disclosure embodiment provides a display substrate, which is divided into at least one display driving chip bonding region (the region opposite to the display driving chips IC1 and IC2), at least one fan-out region ( Figure 4 the region of the 2 fan-shaped traces in

[0040] corresponding to the display driving chip bonding region), and a display area AA. All at least one display driving chip bonding regions are located on the same side of the display area AA, and the fan-out region is located between the corresponding display driving chip bonding region and the display area AA.

[0041] Multiple first traces L1 extend from the display driving chip bonding region through the corresponding fan-out region into the display area AA. The multiple first traces L1 are spaced apart in the fan-out region and the display area AA, and the first trace L1 extends along the column direction in the display area AA.

[0042] A plurality of second traces L2 extend from the display driver chip bonding area through the corresponding fan-out area into the display area AA. The second traces L2 do not overlap with the first traces L1. The second traces L2 extend along the column direction within the display area AA. All the second traces extending from any one display driver chip bonding area define a minimum bounding rectangle M.

[0043] A plurality of third traces L3 are located in the display area AA and extend along the row direction. The plurality of second traces L2 and the plurality of third traces L3 are respectively located in different conductor layers. The plurality of second traces L2 are connected to the plurality of third traces L3 in a one-to-one correspondence through vias H;

[0044] A plurality of fourth traces L4 extend along the column direction and are distributed between any two adjacent first traces L1 outside the minimum bounding rectangle M.

[0045] In the embodiments of the present disclosure, the "row direction" and the "column direction" only represent two intersecting directions parallel to the plane where the display substrate is located. For example, the "row direction" can be the extension direction of the long side or the short side of a rectangular display substrate.

[0046] The minimum bounding rectangle M defined by all the second traces extending from a single display driver chip bonding area, that is, the rectangular outer contour with the smallest area surrounding all the second traces extending from a single display driver chip bonding area.

[0047] Specifically, the first trace L1 is a gate line, and the second trace L2 and the corresponding third trace L3 form a data line; or, the first trace L1 is a data line, and the second trace L2 and the corresponding third trace L3 form a gate line.

[0048] Specifically, the fourth trace L4 is floating or grounded. The fourth trace L4 being floating means that the fourth trace L4 is not in electrical contact with any other conductor or semiconductor. The function of the fourth trace L4 is to make the brightness of the display device more uniform.

[0049] In the embodiments of the present disclosure, the fourth traces L4 are arranged on both sides of the second traces L2 to avoid the overlap of the second traces L2 and the first traces L1 in the fan-out area. This reduces the parasitic capacitance on the first traces L1 and the second traces L2 and improves the driving capabilities of the display driver chips IC1 and IC2 for driving the first traces L1 and the second traces L2. The electrical environments of the respective first traces L1 are more similar, the equivalent impedances of the respective first traces are closer, and the driving capabilities of the display driver chips IC1 and IC2 for driving the respective first traces L1 are more similar. This also helps to improve the uniformity of the display of the display panel.

[0050] Due to the smaller differences in the lengths of adjacent second traces L2 and the surrounding electrical environment, and the smaller differences in the lengths and the surrounding electrical environments of all the second traces L2, the distribution of parasitic capacitance on the second traces L2 will be more uniform. The differences in the environments where the adjacent first traces L1 are located are also smaller, and the distribution of parasitic capacitance on the first traces L1 is also more uniform. The differences in the equivalent impedances presented by all the second traces L2 are smaller. The driving capabilities of the display driver chips IC1 and IC2 for driving the respective second traces L2 and the third traces L3 connected thereto are closer. All of these contribute to improving the display uniformity.

[0051] Specifically, in Figure 4 the illustrated embodiment, multiple second traces L2 extend from the display driver chip bonding area through the middle area of the corresponding fan-out area into the display area AA, and multiple fourth traces L4 are distributed on both sides of the minimum bounding rectangle along the row direction.

[0052] The multiple fourth traces L4 being distributed on both sides of the minimum bounding rectangle along the row direction means that the orthographic projection of the fourth traces L4 on the plane where the display substrate is located is on both sides of the orthographic projection of the minimum bounding rectangle on the plane where the display substrate is located along the row direction.

[0053] In some other embodiments, multiple second traces L2 extend from the display driver chip bonding area through one side edge area of the corresponding fan-out area into the display area AA.

[0054] In some embodiments, referring to Figure 4 , the first traces L1 are arranged at equal intervals along the row direction in the display area AA, and the number of second traces L2 between two adjacent first traces L1 and the number of fourth traces L4 between two adjacent first traces L1 are the same. With such an arrangement, it helps to further improve the display uniformity.

[0055] For example, the number of second traces L2 between two adjacent first traces L1 and the number of fourth traces L4 between two adjacent first traces L1 are both two.

[0056] To further improve the display uniformity, the width of the section of the second trace L2 in the display area AA is equal to the width of the fourth trace L4. The distance between the section of the first trace L1 in the display area AA and the nearest second trace L2 is equal to the distance between the section of the first trace L1 in the display area AA and the nearest fourth trace L4. The distance between the sections of the two nearest second traces L2 in the display area AA is equal to the distance between the two nearest fourth traces L4.

[0057] In some embodiments, referring to Figure 4 , the third traces L3 connected to the second traces L2 between adjacent first traces L1 are continuously distributed.

[0058] Specifically, inFigure 4 In the illustrated embodiment, the third traces L3 connected to two second traces L2 close to each other are also close to each other. The impedances of these two second traces L2 and the corresponding connected third traces L3 are closer, which also helps to improve the display uniformity.

[0059] Figure 5 It is a cross-sectional view of a display substrate according to an embodiment of the present disclosure. In the embodiment of the present disclosure, multiple first traces L1 are arranged on the same layer, multiple second traces L2 are arranged on the same layer, multiple third traces L3 are arranged on the same layer, and multiple fourth traces are arranged on the same layer.

[0060] Specifically, the first trace L1, the second trace L2, and the fourth trace L4 are arranged on the same layer, and the third trace L3 and the first trace L1 are located in different conductor layers.

[0061] Specifically, the substrate 1 of the display substrate is, for example, a glass substrate. The material of the insulating layer 2 between the first trace L1 and the third trace L3 is, for example, an oxide of silicon or a nitride of silicon.

[0062] The transistor in the display substrate may be a bottom-gate transistor. When the first trace L1 is a gate line, the gate of the bottom-gate transistor is arranged on the same layer as the first trace L1. When the third trace L3 is a data line, the source and drain of the bottom-gate transistor are arranged on the same layer as the third transistor L3.

[0063] Figure 6 The left figure in the middle is the display effect diagram of the display device constituted by the display substrate provided by the embodiment of the present disclosure, and the right figure is the display effect diagram of the display device constituted by the display substrate in the related art. The difference between the two is only the wiring methods of the first trace L1, the second trace L2, the third trace L3, and the fourth trace L4. The display device constituted by the display substrate provided by the embodiment of the present disclosure has a brighter brightness.

[0064] Based on the same inventive concept, the embodiment of the present disclosure also provides a display panel, including the aforementioned display substrate. The present disclosure does not limit the display type of the display panel, for example, it may be a liquid crystal display panel, a light-emitting diode display panel, or an electronic paper display panel, etc.

[0065] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the aforementioned display panel.

[0066] Specifically, the display device includes any component or product with a display function, such as a display module, an e-reader, etc.

[0067] Each embodiment in the present disclosure is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments.

[0068] The protection scope of the present disclosure is not limited to the above embodiments. Obviously, those skilled in the art can make various changes and deformations to the present disclosure without departing from the scope and spirit of the present disclosure. If these changes and deformations fall within the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure also includes these changes and deformations.

Claims

1. A display substrate, characterized in that, the display substrate is divided into at least one display driver chip bonding area, at least one fan-out area corresponding to the display driver chip bonding area one by one, and a display area. All of the at least one display driver chip bonding areas are located on the same side of the display area, and the fan-out area is located between the corresponding display driver chip bonding area and the display area; the display substrate includes: a plurality of first traces, a plurality of second traces, a plurality of third traces, and a plurality of fourth traces; the plurality of first traces extend from the display driver chip bonding area through the corresponding fan-out area into the display area. The plurality of first traces are spaced apart in the fan-out area and the display area, and the first traces extend along the column direction in the display area; the plurality of second traces extend from the display driver chip bonding area through the corresponding fan-out area into the display area. The second traces do not overlap with the first traces. The second traces extend along the column direction in the display area, and all the second traces extending from any one display driver chip bonding area define a minimum bounding rectangle; the plurality of third traces are located in the display area and extend along the row direction. The plurality of second traces and the plurality of third traces are respectively located in different conductor layers, and the plurality of second traces are connected to the plurality of third traces one by one through vias; the plurality of fourth traces extend along the column direction and are distributed between any two adjacent first traces outside the minimum bounding rectangle.

2. The display substrate according to claim 1, characterized in that, the plurality of second traces extend from the display driver chip bonding area through the middle area of the corresponding fan-out area into the display area, and the plurality of fourth traces are distributed on both sides of the minimum bounding rectangle along the row direction.

3. The display substrate according to claim 1, characterized in that, the first traces are gate lines, and the second traces and the corresponding third traces form data lines; or, the first traces are data lines, and the second traces and the corresponding third traces form gate lines.

4. The display substrate according to claim 1, characterized in that, the first traces are equally spaced along the row direction in the display area, and the number of second traces between two adjacent first traces is the same as the number of fourth traces between two adjacent first traces.

5. The display substrate according to claim 1, characterized in that, the third traces connected by the second traces between adjacent first traces are continuously distributed.

6. The display substrate according to claim 1, characterized in that, the fourth traces are floating or grounded.

7. The display substrate according to claim 1, characterized in that, the first traces, the second traces, and the fourth traces are arranged in the same layer, and the third traces and the first traces are located in different conductor layers.

8. A display panel, characterized in that, it includes the display substrate according to any one of claims 1 to 7.

9. A display device, characterized in that, it includes the display panel according to claim 8.

10. The display device according to claim 9, characterized in that, The display device includes an e-reader.

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