Array substrate and display panel thereof
By setting the connection between the auxiliary signal line, the clock signal line and the GOA driving unit on the array substrate, the overlap area is reduced, and the problem of large cross-connection capacitance between the clock signal line and the GOA driving unit in the prior art is solved, and the function is achieved Reduced consumption.
Patent Information
- Application Number
- CN202211379686.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-04
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2042-11-04
AI Technical Summary
In the existing high-resolution display panel, the clock signal line is directly connected to the GOA driving unit, resulting in the problem of large jumper capacitance and high power consumption.
An array substrate is designed, by setting a connection between the auxiliary signal line, the clock signal line and the GOA driving unit, the line width of the overlapping part of the auxiliary signal line and the second connecting line is smaller than the line width of the clock signal line, thereby reducing the overlap area. Reduce the jumper capacitance.
It effectively reduces the power consumption of the GOA driver unit and saves energy.
Smart Images
Figure CN115691392B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel thereof. Background Art
[0002] In existing high-resolution display panels, GOA (Gate on Array, gate drive circuit integrated on array substrate) driving is usually adopted, that is, the gate drive circuit is manufactured on the TFT array substrate using the existing array process to realize the driving mode of scanning the gate row by row. This technology replaces the traditional Gate IC (gate integrated circuit) driving and saves production costs. The GOA circuit includes a GOA drive unit (Circuit) and a bus unit (busline), wherein the bus unit includes a clock signal line (Clock, CK) and the like.
[0003] In the process of research and practice of the prior art, the inventors of the present application discovered that since the clock signal line is directly connected to the GOA driving unit to provide a driving signal, for medium and large-sized products, in order to reduce the impedance of the clock signal line, the clock signal line is usually designed to have a larger line width, which makes the cross-capacitance between the clock signal line and the GOA driving unit larger, which in turn causes the GOA driving unit to consume more power when driven, which is a problem that needs to be solved urgently. Summary of the invention
[0004] The embodiments of the present application provide an array substrate and a display panel thereof, aiming to solve the technical problem in the prior art that the GOA driving unit has high power consumption when being driven due to large cross-over capacitance.
[0005] The present application provides an array substrate, comprising:
[0006] at least one clock signal line;
[0007] A first connecting line, one end of which is connected to one of the clock signal lines;
[0008] at least one auxiliary signal line, the at least one auxiliary signal line being arranged at one side of the at least one clock signal line, and the other end of the first connecting line being connected to the auxiliary signal line;
[0009] at least one second connecting line, one end of the second connecting line being connected to the auxiliary signal line; and
[0010] at least one GOA driving unit, wherein the GOA driving unit is connected to the other end of the second connecting line;
[0011] Wherein, the line width of the portion where the auxiliary signal line overlaps with the second connecting line is smaller than the line width of the clock signal line.
[0012] Optionally, in some embodiments of the present application, the number of the clock signal line, the auxiliary signal line, the first connecting line, the second connecting line and the GOA driving unit are all multiple, the multiple clock signal lines and the multiple auxiliary signal lines are arranged at intervals along the same direction, and the multiple GOA driving units are arranged at intervals along the extension direction of the clock signal line;
[0013] One of the clock signal lines and one of the auxiliary signal lines are connected via one of the first connection lines, and one of the GOA driving units is electrically connected to one of the auxiliary signal lines via one of the second connection lines.
[0014] Optionally, in some embodiments of the present application, the auxiliary signal line includes multiple first segments and multiple second segments, the first segments and the second segments are alternately connected in sequence along the extension direction of the auxiliary signal line, the line width of the first segment is greater than the line width of the second segment, the line width of the second segment is smaller than the line width of the clock signal line, and the second connecting line is connected to the second segment.
[0015] Optionally, in some embodiments of the present application, the second segment of the auxiliary signal line and the two first segments connected to the second segment define a accommodating space, and a portion of the first segment of one of the auxiliary signal lines is located in the accommodating space of an adjacent auxiliary signal line.
[0016] Optionally, in some embodiments of the present application, the number of the clock signal lines and the number of the auxiliary signal lines are at least m; in the arrangement direction of the clock signal lines and the auxiliary signal lines, the nth clock signal line is connected to the nth auxiliary signal line through one of the first connecting lines; n≤m, m and n are positive integers, and m>2.
[0017] Optionally, in some embodiments of the present application, the clock signal line is provided with a connection hole, the first connection line passes through the connection hole to be electrically connected to the clock signal line, and the connection hole is located at an edge of the clock signal line close to the auxiliary signal line.
[0018] Optionally, in some embodiments of the present application, a line width of a portion where the second connecting line overlaps with the auxiliary signal line is smaller than a line width of a portion where the second connecting line does not overlap with the auxiliary signal line.
[0019] Optionally, in some embodiments of the present application, a plurality of the first connecting lines are provided at intervals of k of the GOA driving units, so as to connect the plurality of clock signal lines and the plurality of auxiliary signal lines in a one-to-one correspondence, and k is a positive integer.
[0020] Optionally, in some embodiments of the present application, a ratio of a line width of a portion where the auxiliary signal line overlaps the second connecting line to a line width of the clock signal line is D, and D<1 / 2.
[0021] Correspondingly, an embodiment of the present application further provides a display panel, which includes a color filter substrate and the array substrate as described above, wherein the color filter substrate and the array substrate are arranged opposite to each other.
[0022] The embodiment of the present application adopts an array substrate, which includes at least one clock signal line, a first connection line, at least one auxiliary signal line, at least one second connection line and at least one GOA driving unit. At least one auxiliary signal line is arranged on one side of at least one clock signal line. One end of the first connection line is connected to a clock signal line, and the other end of the first connection line is connected to the auxiliary signal line. One end of the second connection line is connected to the auxiliary signal line, and the GOA driving unit is connected to the other end of the second connection line. The line width of the part where the auxiliary signal line overlaps with the second connection line is smaller than the line width of the clock signal line. In this way, the clock signal line and the GOA driving unit are connected separately by additionally setting the auxiliary signal line, that is, the electrical connection between the clock signal line and the GOA driving unit is guaranteed. At the same time, because the line width of the part where the auxiliary signal line overlaps with the second connection line is smaller than the line width of the clock signal line, the GOA driving unit is directly connected to the clock signal line compared with the prior art to reduce the overlapping area, thereby reducing the cross-over capacitance, so as to save the power consumption when the GOA driving unit is driven. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;
[0025] Figure 2 It is a partial schematic diagram of the auxiliary connecting line and the second connecting line provided in an embodiment of the present application. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.
[0027] The embodiments of the present application provide an array substrate and a display panel thereof. The following are detailed descriptions. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.
[0028] Reference Figure 1 The first embodiment of the present application provides an array substrate 100, comprising at least one clock signal line 10, a first connection line 20, at least one auxiliary signal line 30, at least one second connection line 40 and at least one GOA driving unit 50. At least one auxiliary signal line 30 is arranged on one side of at least one clock signal line 10. One end of the first connection line 20 is connected to a clock signal line 10, and the other end of the first connection line 20 is connected to the auxiliary signal line 30. One end of the second connection line 40 is connected to the auxiliary signal line 30, and the GOA driving unit 50 is connected to the other end of the second connection line 40. The line width of the portion where the auxiliary signal line 30 overlaps with the second connection line 40 is smaller than the line width of the clock signal line 10. In this way, by additionally arranging the auxiliary signal line 30 to connect to the clock signal line 10 and the GOA driving unit 50 respectively, the electrical connection between the clock signal line 10 and the GOA driving unit 50 is ensured. At the same time, since the line width of the overlapping part of the auxiliary signal line 30 and the second connecting line 40 is smaller than the line width of the clock signal line 10, the overlapping area is reduced compared with the prior art GOA driving unit 50 and the clock signal line 10, thereby reducing the cross-over capacitance and saving power consumption when the GOA driving unit 50 is driven.
[0029] It should be noted that the material of the clock signal line 10 can be a metal material such as copper, aluminum, nickel, alloys thereof or mixtures thereof. The clock signal of the clock signal line 10 can be transmitted to the GOA driving unit 50 through the first connecting line 20, the auxiliary signal line 30 and the second connecting line 40 in sequence, so that the GOA driving unit 50 provides a scanning signal to the display panel, thereby controlling the switching state of the pixel thin film transistor. The first connecting line 20 and the second connecting line 40 are perpendicular to the auxiliary signal line 30, so as to reduce the design length of the first connecting line 20 and the second connecting line 40 to save costs, and the first connecting line 20 and the second connecting line 40 are staggered for early installation and later maintenance. In addition, the ratio of the line width of the overlapping part of the auxiliary signal line 30 and the second connecting line 40 to the line width of the clock signal line 10 is D, D < 1 / 2. That is, the D can be 1 / 3, 1 / 4, 1 / 5, 1 / 6, etc., and the smaller the D is, the further the cross-over capacitance can be reduced to further reduce the power consumption of the GOA driving unit 50.
[0030] Reference Figure 1 Optionally, the number of clock signal lines 10, auxiliary signal lines 30, first connection lines 20, second connection lines 40 and GOA drive units 50 are all multiple. Multiple clock signal lines 10 and multiple auxiliary signal lines 30 are arranged at intervals along the same direction, and multiple GOA drive units 50 are arranged at intervals along the extension direction of the clock signal line 10. A clock signal line 10 and an auxiliary signal line 30 are connected through a first connection line 20, and a GOA drive unit 50 is electrically connected to an auxiliary signal line 30 through a second connection line 40. Among them, the clock signal line 10 and the auxiliary signal line 30 have the same extension direction, that is, the auxiliary signal line 30 can be arranged in parallel with the clock signal line 10, and the multiple clock signal lines 10 and the multiple auxiliary signal lines 30 are arranged at intervals perpendicular to the extension direction, so that the multiple clock signal lines 10 and the multiple auxiliary signal lines 30 can be arranged more concentratedly to reduce the occupied space. This embodiment is described by taking the array substrate 100 of 4 clock signals as an example. The array substrate 100 provided in the present application does not limit the number of clock signals. For example, it can also be applied to array substrates 100 with 6, 8, 12, and 16 clock signals. In order to save space, the auxiliary signal lines 30 can be the same as the number of clock signal lines 10 so as to correspond one to one. Or in order to facilitate later testing and maintenance, the number of auxiliary signal lines 30 can also be more than the number of clock signal lines 10, so as to reserve auxiliary signal lines 30 for backup. It should be noted that a GOA drive unit 50 is connected to three auxiliary signal lines 30, so that a GOA drive unit 50 is connected to three clock signal lines 10, and the three auxiliary signal lines 30 connected to adjacent GOA drive units 50 are different, so that different control signals can be sent at different time periods.
[0031] Furthermore, in conjunction with reference Figure 2 The auxiliary signal line 30 includes a plurality of first segments 31 and a plurality of second segments 32. The first segments 31 and the second segments 32 are alternately connected in sequence along the extension direction of the auxiliary signal line 30. The line width of the first segment 31 is greater than the line width of the second segment 32. The line width of the second segment 32 is less than the line width of the clock signal line 10. The second connecting line 40 is connected to the second segment 32. Since the narrow line width will lead to a large impedance and affect the transmission of the signal, the auxiliary signal line 30 is designed to be the first segment 31 and the second segment 32 that are alternately connected, and the line width of the first segment 31 is greater than the line width of the second segment 32, so that the operator can easily identify and electrically connect the second connecting line 40 to the second segment 32. The line width of the second section 32 is greater than the line width of the clock signal line 10, that is, only the line width of the second section 32 connected to the second connecting line 40 is set to be narrower, so that the line width of the first section 31 can be set to be wider, so that the auxiliary signal line 30 can increase the line width of the part of the auxiliary signal line 30 that does not overlap with the second connecting line 40, thereby making the overall impedance of the auxiliary signal line 30 smaller, so as to facilitate the passage of the signal.
[0032] Furthermore, the second section 32 of the auxiliary signal line 30 and the two first sections 31 connected to the second section 32 define a containing space 30a, and a portion of the first section 31 of an auxiliary signal line 30 is located in the containing space 30a of an adjacent auxiliary signal line 30. In order to reduce the occupied space of multiple auxiliary signal lines 30, a portion of the first section 31 of the auxiliary signal line 30 is located in the containing space 30a of the adjacent auxiliary signal line 30, so that the distance between the adjacent auxiliary signal lines 30 can be closer, thereby reducing the cross-over capacitance and avoiding the volume of the array substrate 100 being too large.
[0033] Optional, see Figure 1, the number of the clock signal lines 10 and the number of the auxiliary signal lines 30 are at least m. In the arrangement direction of the clock signal lines 10 and the auxiliary signal lines 30, the nth clock signal line 10 is connected to the nth auxiliary signal line 30 through a first connecting line 20; n≤m, m and n are positive integers, and m>2. In this embodiment, m is equal to 4, that is, the number of the clock signal lines 10 and the auxiliary signal lines 30 are both 4. In this way, in the arrangement direction of the clock signal line 10 and the auxiliary signal line 30, the first clock signal line 10 is connected to the first auxiliary signal line 30 through a first connecting line 20, and the second clock signal line 10 is connected to the second auxiliary signal line 30 through a first connecting line 20, the third clock signal line 10 is connected to the third auxiliary signal line 30 through a first connecting line 20, and the fourth clock signal line 10 is connected to the fourth auxiliary signal line 30 through a first connecting line 20, so that the distances between the connected clock signal lines 10 and auxiliary signal lines 30 are close, so that the length of each first connecting line 20 is close, which is convenient for installation, and makes the overall design more regular, which is convenient for later maintenance.
[0034] Furthermore, the clock signal line 10 is provided with a connection hole 11, and the first connection line 20 passes through the connection hole 11 to be electrically connected to the clock signal line 10, and the connection hole 11 is located at the edge of the clock signal line 10 close to the auxiliary signal line 30. It should be noted that the first connection line 20 and the clock signal line 10 are connected through the connection hole 11, which means that a conductive material is provided in the connection hole 11, which is equivalent to being connected through a connection line. The connection hole 11 is located at the edge of the clock signal line 10 close to the auxiliary signal line 30, and this design is used to reduce the length of the second connection line 40, so as to further save costs.
[0035] Optionally, the line width of the portion where the second connection line 40 overlaps with the auxiliary signal line 30 is smaller than the line width of the portion where the second connection line 40 does not overlap with the auxiliary signal line 30. This can reduce the crossover capacitance between the auxiliary signal line 30 and the GOA driving unit 50, facilitate the connection of the second connection line 40, and effectively reduce the overall impedance of the second connection line 40 for signal transmission.
[0036] Optional, see Figure 1 , a plurality of first connecting lines 20 are provided for each k interval of GOA driving units 50, so as to connect a plurality of clock signal lines 10 and a plurality of auxiliary signal lines 30 one by one, and k is a positive integer. Among them, k can be a positive integer such as 4, 5, 6, 7, 8, etc. In this way, an auxiliary signal line 30 is connected to a clock signal line 10 through a plurality of first connecting lines 20, thereby shortening the path of the clock signal line 10 to be transmitted to a plurality of GOA driving units 50, so as to improve the signal transmission efficiency between the clock signal line 10 and the auxiliary signal line 30.
[0037] The embodiment of the present application also provides a display panel. The display panel provided in the embodiment of the present application includes an array substrate 100 and a color filter substrate. The array substrate 100 and the color filter substrate are arranged relative to each other. The array substrate 100 can be specifically referred to the above description of the array substrate 100, which will not be repeated here.
[0038] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. An array substrate, characterized in that: include: at least one clock signal line; A first connecting line, one end of which is connected to one of the clock signal lines; at least one auxiliary signal line, the at least one auxiliary signal line being arranged at one side of the at least one clock signal line, and the other end of the first connecting line being connected to the auxiliary signal line; at least one second connecting line, one end of the second connecting line being connected to the auxiliary signal line; as well as at least one GOA driving unit, wherein the GOA driving unit is connected to the other end of the second connecting line; Wherein, the line width of the portion where the auxiliary signal line overlaps with the second connecting line is smaller than the line width of the clock signal line.
2. The array substrate according to claim 1, characterized in that: The number of the clock signal line, the auxiliary signal line, the first connection line, the second connection line and the GOA driving unit are all multiple, the multiple clock signal lines and the multiple auxiliary signal lines are arranged at intervals along the same direction, and the multiple GOA driving units are arranged at intervals along the extension direction of the clock signal line; One of the clock signal lines and one of the auxiliary signal lines are connected via one of the first connection lines, and one of the GOA driving units is electrically connected to one of the auxiliary signal lines via one of the second connection lines.
3. The array substrate according to claim 2, characterized in that: The auxiliary signal line includes multiple first segments and multiple second segments, the first segments and the second segments are alternately connected in sequence along the extension direction of the auxiliary signal line, the line width of the first segment is larger than the line width of the second segment, the line width of the second segment is smaller than the line width of the clock signal line, and the second connecting line is connected to the second segment.
4. The array substrate according to claim 3, characterized in that: The second segment of the auxiliary signal line and the two first segments connected to the second segment define an accommodation space, and a portion of the first segment of one auxiliary signal line is located in the accommodation space of an adjacent auxiliary signal line.
5. The array substrate according to claim 2, characterized in that: The number of the clock signal lines and the number of the auxiliary signal lines are at least m; in the arrangement direction of the clock signal lines and the auxiliary signal lines, the nth clock signal line is connected to the nth auxiliary signal line through the first connecting line; n≤m, m and n are positive integers, and m>2.
6. The array substrate according to claim 5, characterized in that: The clock signal line is provided with a connection hole, the first connection line passes through the connection hole to be electrically connected to the clock signal line, and the connection hole is located at an edge of the clock signal line close to the auxiliary signal line.
7. The array substrate according to claim 5, characterized in that: A line width of a portion where the second connection line overlaps the auxiliary signal line is smaller than a line width of a portion where the second connection line does not overlap the auxiliary signal line.
8. The array substrate according to claim 2, wherein: A plurality of the first connecting lines are provided at intervals of k of the GOA driving units, so as to connect a plurality of clock signal lines and a plurality of auxiliary signal lines in a one-to-one correspondence, and k is a positive integer.
9. The array substrate according to any one of claims 1 to 8, characterized in that: The ratio of the line width of the portion where the auxiliary signal line overlaps with the second connection line to the line width of the clock signal line is D, and D<1 / 2.
10. A display panel, characterized in that: The display panel comprises a color filter substrate and the array substrate according to any one of claims 1 to 9, and the color filter substrate and the array substrate are arranged opposite to each other.