Group III nitride enhanced HEMT device and manufacturing method thereof

Abstract

The present invention discloses a III-nitride enhanced HEMT device and a method for manufacturing the same. The III-nitride enhanced HEMT device comprises an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure. The epitaxial structure comprises a channel layer, a barrier layer and a p-type semiconductor stacked in sequence. The epitaxial structure also comprises an Al2O3 layer stacked on the p-type semiconductor. y Ga 1‑y N layer, the gate is set on Al y Ga 1‑y The Al content at the contact interface between the barrier layer and the p-type semiconductor is lower than the Al content in the remaining areas of the barrier layer. y Ga 1‑y The concentration of the doping element contained in the N layer is lower than the concentration of the doping element contained in the p-type semiconductor; wherein 0 < x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ m ≤ 1. The III-nitride-enhanced HEMT device provided by the present invention has a longer gate operating life and a smaller gate dynamic threshold voltage drift, which can significantly improve the reliability of the device.

Description

Technical Field

[0001] The present invention relates to a novel nitride-enhanced high electron mobility transistor (HEMT) and a preparation method thereof, and in particular to a novel group III nitride-enhanced HEMT with high reliability and stability and a preparation method thereof, belonging to the technical field of semiconductor electronic devices. Background Art

[0002] Group III nitride semiconductors are known as third-generation semiconductors, with advantages such as wide bandgap, good chemical stability, and high breakdown voltage. High electron mobility transistors (HEMTs) composed of heterostructures such as AlGaN / GaN have the advantages of high electron concentration and mobility, and perform excellently in high frequency, high voltage resistance, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in power supply applications such as consumer electronics, 5G base stations, and servers.

[0003] Typically, the gate of a III-nitride enhancement-mode HEMT utilizes a metal / p-GaN / AlGaN / GaN stack structure. Mg acceptors are doped in the p-GaN layer to raise the energy band of the AlGaN / GaN layer and deplete the 2DEG, thereby achieving enhancement mode. These devices are often referred to as p-GaN gate enhancement-mode HEMTs (p-GaN E-HEMTs). In practical applications, the p-GaN gate voltage undergoes rapid high-to-low voltage switching, which can cause gate voltage overshoot due to inductive loads. Furthermore, high-frequency switching requires synchronized high-frequency response for carrier transport within the gate stack. Therefore, the performance, and particularly reliability, of these applications is crucial to the commercialization of p-GaN E-HEMTs.

[0004] The common gate structure is the "metal / p-GaN / AlGaN / GaN" stack structure, such as Figure 1a The gate metal layer is usually deposited by evaporation, sputtering and other processing methods, and the work function is in the range of 4-6eV, such as Ti, Ni, Pd, etc. The p-GaN / AlGaN / GaN stack is usually grown by MOCVD epitaxial growth, and the p-GaN layer is almost uniformly doped with Mg, with a doping concentration of 1-3×10 19 cm -3 The AlGaN layer is a single-layer structure with a thickness of 70-150nm; the AlGaN layer is a uniform single-layer structure with an Al content of 10%-30% and a thickness of 10-30nm; and the GaN channel layer is a single-layer structure with a thickness of 50-500nm.

[0005] like Figure 1a 、 Figure 1bAs shown in Figure 2, the gate of the metal / p-GaN / AlGaN / GaN stack can be equivalent to a "Schottky junction" (JS) composed of metal / p-GaN and a "bilateral heterojunction" (JP) composed of p-GaN / AlGaN / GaN. When the gate is working in the forward direction, the Schottky junction is in a reverse bias state and bears most of the voltage. Since the effective acceptor concentration of the surface p-GaN is usually around 10 19 cm -3 There is a very large electric field in the Schottky depletion region. The tunneling and acceleration of carriers under the high electric field will cause the original defects in the region to be activated or new defects to form. The greatly increased defect state density will cause the Schottky junction to S Failure: When dynamically turned on, the energy band barrier between p-GaN / AlGaN (usually around 0.2-0.4eV) blocks carrier injection into the GaN channel, causing carrier accumulation at the p-GaN / AlGaN interface, which in turn leads to degradation of the gate dynamic threshold voltage (typically, the threshold voltage drift can reach ±2V). In addition, the p-GaN gate contains a large number of C, H impurities, and point defects such as vacancies, which can easily cause reliability degradation of the p-GaN gate.

[0006] The gates of existing III-nitride enhanced-mode HEMTs are mostly metal / p-GaN / AlGaN / GaN stack structures. The p-GaN epitaxial growth uses Mg doping as an acceptor to provide holes, which has the following defects:

[0007] First, the p-GaN layer in the existing technology is mostly doped almost uniformly with a concentration of about 10 19 cm -3 In order to achieve a high Mg doping concentration, certain compromises need to be made in the growth conditions during the MOCVD epitaxial growth process. As a result, there are high levels of C, H impurities and point defects such as vacancies in the p-GaN layer. These defect states are easily activated or expanded under high electric fields to form new defects, which can also affect carrier transport in p-GaN and lead to gate reliability degradation. In addition, the high Mg doping concentration in the surface layer will cause the electric field strength in the Schottky junction composed of metal / p-GaN to be too large under forward gate voltage, further causing failure and other problems.

[0008] Secondly, the AlGaN layer in the existing technology is a single-layer structure with a uniform Al component, usually between 10% and 30%. Since the band gap of AlGaN is wider than that of GaN, whether it is the injection of holes from p-GaN into the GaN channel or the injection of electrons from the GaN channel into p-GaN, it is necessary to overcome the potential barrier of AlGaN in the valence band or conduction band. During the dynamic switching process, due to the blocking of holes in p-GaN by the valence band barrier, a large number of holes will accumulate at the p-GaN / AlGaN interface, resulting in dynamic reliability issues such as dynamic threshold voltage drift. Summary of the Invention

[0009] The main purpose of the present invention is to provide a III-nitride enhanced HEMT device and a method for manufacturing the same, so as to overcome the deficiencies in the prior art.

[0010] To achieve the aforementioned object of the invention, the technical solutions adopted by the present invention include:

[0011] In one aspect, an embodiment of the present invention provides a III-nitride enhanced-mode HEMT device, comprising an epitaxial structure and a source, a drain, and a gate coordinated with the epitaxial structure, wherein the epitaxial structure comprises a channel layer, a barrier layer, and a p-type semiconductor stacked in sequence.

[0012] The epitaxial structure further includes an Al stacked on the p-type semiconductor. y Ga 1-y N layer, the gate is set on Al y Ga 1-y On the Nth floor;

[0013] Wherein, the barrier layer is Al x Ga 1-x N barrier layer or In x Al 1-x N barrier layer, the p-type semiconductor is p-type Al m Ga 1-m N-layer or p-type In m Al 1-m N layer, the Al content at the contact interface between the barrier layer and the p-type semiconductor is lower than the Al content in the remaining areas of the barrier layer, and the Al y Ga 1-y The concentration of the doping element contained in the N layer is lower than the concentration of the doping element contained in the p-type semiconductor; wherein, 0<x≤1, 0≤y≤1, 0≤m≤1.

[0014] Furthermore, the Al content at the contact interface between the barrier layer and the p-type semiconductor is 0-10%.

[0015] Furthermore, the Al content in the barrier layer decreases in a direction away from the channel layer.

[0016] Furthermore, the Al content in the barrier layer changes gradually or in a stepwise manner in a direction away from the channel layer.

[0017] Furthermore, the average Al content in the barrier layer is 5-50%.

[0018] Furthermore, the thickness of the barrier layer is 1-100 nm, preferably 5-50 nm.

[0019] In some more specific embodiments, the p-type semiconductor and Al y Ga 1-y The N layer only covers the gate region under the barrier layer.

[0020] In some more specific embodiments, a groove is formed in the gate-under-gate region of the barrier layer, and the groove is filled with a local region of the p-type semiconductor.

[0021] In some more specific embodiments, the barrier layer includes a first barrier layer and a second barrier layer disposed on the channel layer, the second barrier layer is distributed between the first barrier layer and the p-type semiconductor, and the Al content in the second barrier layer decreases in a direction away from the channel layer.

[0022] Furthermore, the Al content in the second barrier layer changes gradually or in a step-like manner in a direction away from the channel layer.

[0023] Furthermore, the Al component in the first barrier layer is uniformly distributed.

[0024] In some more specific embodiments, the second barrier layer continuously covers the first barrier layer; or, the second barrier layer only covers the gate-under-region of the first barrier layer; or, the gate-under-region of the first barrier layer is at least partially removed to form a groove-like structure, and the groove-like structure is filled with the second barrier layer.

[0025] Furthermore, the second barrier layer has the same conductivity type as the p-type semiconductor.

[0026] In some more specific embodiments, the first barrier layer includes a first Al z Ga 1-z N layer, GaN intermediate layer and second Al z Ga 1-z N layers, 0<z≤1.

[0027] Furthermore, the GaN intermediate layer and the second Al z Ga 1-z The regions under the gate of the N layer are all removed to form the trench structure.

[0028] In some more specific embodiments, a groove is formed in the sub-gate region of the second barrier layer, and the groove is filled with a local region of the p-type semiconductor.

[0029] Furthermore, the Al y Ga 1-y The N layer is p-type, where the acceptor concentration is ≤5×10 18 cm -3 ; Or, the Al y Ga 1-y The N layer is U-shaped; or, the Al y Ga 1-y The N layer is n-type, where the donor concentration is ≤5×10 17 cm -3 .

[0030] Furthermore, the Al y Ga 1-y The thickness of the N layer is 5-100 nm.

[0031] Furthermore, the barrier layer is an unintentionally doped layer.

[0032] Furthermore, the thickness of the p-type semiconductor is 10-300 nm.

[0033] Furthermore, the acceptor doping concentration of the p-type semiconductor is (1-8)×10 19 cm -3 .

[0034] In some more specific embodiments, the III-nitride enhanced HEMT device further includes a substrate, on which a transition layer and a high resistance layer are sequentially stacked, and the channel layer is stacked on the high resistance layer.

[0035] An embodiment of the present invention further provides a method for manufacturing the III-nitride enhanced HEMT device, which comprises:

[0036] The epitaxial structure includes a channel layer, a barrier layer, a p-type semiconductor and an Al y Ga 1-y N layers; and,

[0037] A source electrode, a drain electrode and a gate electrode are manufactured to match the epitaxial structure.

[0038] In some specific embodiments, the manufacturing method specifically includes: sequentially growing a channel layer, a barrier layer, a p-type semiconductor and an Al y Ga 1-y After the N layer, the p-type semiconductor and Al y Ga 1-yThe N layer is completely removed except for the area under the gate, and then the remaining Al y Ga 1-y A gate is fabricated on the N layer.

[0039] In some more specific embodiments, the manufacturing method specifically includes: sequentially growing a channel layer and a barrier layer on a substrate, and removing a portion of the gate region under the barrier layer to form a groove in the barrier layer; then continuing to grow a p-type semiconductor and an Al2O3 layer on the barrier layer. y Ga 1-y N layer, and the groove is filled with a local area of the p-type semiconductor.

[0040] Furthermore, the manufacturing method specifically includes: y Ga 1-y The N layer is completely removed except for the area under the gate, and then the remaining Al y Ga 1-y A gate is fabricated on the N layer.

[0041] In some more specific embodiments, the manufacturing method specifically includes: sequentially growing a first barrier layer and a second barrier layer on the channel layer, thereby forming the barrier layer.

[0042] Furthermore, the manufacturing method specifically includes: y Ga 1-y The N layer, the p-type semiconductor and the second barrier layer are completely removed except for the area under the gate.

[0043] In some more specific embodiments, the manufacturing method specifically includes: after growing a first barrier layer on the channel layer, removing the gate area of the first barrier layer to form a groove structure, then growing a second barrier layer on the first barrier layer, and filling the groove structure with the second barrier layer to form the barrier layer.

[0044] In some more specific embodiments, the manufacturing method specifically includes: growing a first Al z Ga 1-z N layer, GaN intermediate layer and second Al z Ga 1-z N layer, thereby forming the first barrier layer.

[0045] In some more specific embodiments, the manufacturing method specifically includes: z Ga 1-z The gate-under-region of the N layer is removed to form the groove structure, and then a second barrier layer is grown on the first barrier layer, and the groove structure is filled with the second barrier layer, thereby forming the barrier layer.

[0046] In some more specific embodiments, the manufacturing method specifically includes: removing part of the gate area of the second barrier layer to form a groove, or continuously growing the second barrier layer along the surface of the first barrier layer and its groove structure, so that the part of the second barrier layer located in the groove structure forms a groove, and then growing a p-type semiconductor on the second barrier layer, and filling the groove with a local area of the p-type semiconductor.

[0047] Furthermore, the manufacturing method specifically includes: y Ga 1-y The N layer and the second barrier layer are completely removed except for the area under the gate.

[0048] Compared with the prior art, the advantages of the present invention include:

[0049] 1) An embodiment of the present invention provides a highly reliable and stable III-nitride enhanced-mode HEMT device. By adding a low-doping (Al)GaN layer to the p-type semiconductor under the gate, the crystal quality of the p-type semiconductor is improved, the electric field strength of the Schottky junction formed by the metal / semiconductor is reduced, and the failure probability of the Schottky junction is reduced.

[0050] 2) The present invention also provides an AlGaN barrier layer with a variable Al composition below the p-type semiconductor, thereby reducing or even eliminating the valence band step difference between p-GaN and AlGaN, overcoming reliability issues such as threshold voltage drift caused by hole accumulation during dynamic turn-on.

[0051] 3) The III-nitride enhanced HEMT device provided by the present invention has a longer gate operating life and a smaller gate dynamic threshold voltage drift, and the reliability of the device can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1a This is a schematic diagram of the structure and gate equivalent structure of a conventional III-nitride enhanced HEMT device;

[0053] Figure 1b This is a schematic diagram of the energy band structure of a conventional III-nitride enhanced HEMT device;

[0054] Figure 2 1 is a schematic structural diagram of an epitaxial structure of a III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0055] Figure 31 is a schematic structural diagram of an epitaxial structure of a III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0056] Figure 4a 1 is a schematic structural diagram of a III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0057] Figure 4b 1 is a schematic structural diagram of another III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0058] Figure 4c 1 is a schematic structural diagram of another III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0059] Figure 4d Schematic diagram of the structure of a III-nitride enhanced HEMT device provided in Comparative Example 1;

[0060] Figure 4e 2 is a schematic structural diagram of another III-nitride enhanced HEMT device provided in Comparative Example 2;

[0061] Figure 5 1 is a schematic structural diagram of an epitaxial structure of a III-nitride depletion-mode HEMT device provided in a typical embodiment of the present invention;

[0062] Figure 6 1 is a schematic structural diagram of an epitaxial structure of a III-nitride depleted HEMT device provided in a typical embodiment of the present invention;

[0063] Figure 7 1 is a schematic structural diagram of an epitaxial structure of a III-nitride depleted HEMT device provided in a typical embodiment of the present invention;

[0064] Figure 8 1 is a schematic structural diagram of an epitaxial structure of a III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0065] Figure 9a 1 is a schematic structural diagram of a III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0066] Figure 9b 1 is a schematic structural diagram of another III-nitride enhanced HEMT device provided in a typical embodiment of the present invention;

[0067] Figure 9cThis is a schematic structural diagram of another III-nitride enhanced HEMT device provided in a typical embodiment of the present invention. DETAILED DESCRIPTION

[0068] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. The following will further explain this technical solution, its implementation process and principles.

[0069] In response to the problems existing in the prior art, the inventors of this case have discovered that simply improving the acceptor doping concentration of the p-(Al)GaN or p-(In)AlN surface layer cannot improve the device's performance such as dynamic threshold voltage drift; simply improving the band structure of the AlGaN barrier layer or InAlN barrier layer cannot increase the device's service life; based on this, the inventors of this case proposed to simultaneously epitaxially grow a low-doped (Al)GaN layer above the p-(Al)GaN layer or p-(In)AlN layer, and epitaxially grow a variable Al composition AlGaN barrier layer or InAlN barrier layer below the p-(Al)GaN layer or p-(In)AlN layer, so as to enhance the service life of the gate and improve the stability of the gate control performance.

[0070] Specifically, the present invention reduces the doping concentration of the (Al)GaN layer above the p-(Al)GaN layer or the p-(In)AlN layer, which means a reduction in the effective acceptor (or donor) concentration. This increases the width of the depletion region of the Schottky junction when reverse biased, reduces the electric field strength, and makes it less likely for carriers to tunnel or gain excessive energy to deactivate existing defects or create new ones. Furthermore, the conditions for growing a low-doping (Al)GaN layer using MOCVD help improve the crystal quality of the epitaxial layer (or epitaxial structure), reducing the incorporation of impurities such as C and the generation of defects such as vacancies. Furthermore, the high-quality (Al)GaN layer is less likely to form defects, significantly improving the reliability of the Schottky junction and enhancing the service life of the device gate.

[0071] Furthermore, the present invention reduces the Al composition in the lower AlGaN barrier layer in contact with the p-(Al)GaN layer, or adopts an AlGaN barrier layer with a gradient Al composition or a step-change Al composition, so as to reduce or even eliminate the valence band gap between the p-(Al)GaN and AlGaN barrier layers, eliminate the large accumulation of holes during the dynamic turn-on process, thereby alleviating the problem of dynamic threshold voltage drift of the device and improving the dynamic stability and reliability of the p-GaN E-HEMT.

[0072] The technical solution, its implementation process and principles will be further explained below in conjunction with specific implementation cases and accompanying drawings. Unless otherwise specified, the epitaxial growth, patterning process, etching process, etc. used in the embodiments of this case can adopt existing processes. It should be noted that the technical solution of the present invention is introduced below using the AlGaN barrier layer and its corresponding p-(Al)GaN layer as examples. Accordingly, the barrier layer can also be an InAlN barrier layer, and accordingly, the p-type semiconductor can also be a p-(In)AlN layer.

[0073] To achieve the above-mentioned purpose, the present invention mainly provides two technical solutions:

[0074] In a specific embodiment, see Figure 2-4a A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0075] 1) Please refer to Figure 2 A III-nitride enhanced-mode HEMT epitaxial structure is grown on a substrate 101. The epitaxial structure specifically includes a transition layer 102, a high-resistance voltage-withstand layer (hereinafter referred to as a high-resistance layer) 103, a conductive channel layer (hereinafter referred to as a channel layer) 104, a barrier layer 105A with a variable Al composition, a p-type (Al)GaN layer 106, and a low-doping concentration (Al)GaN layer 107, which are stacked in sequence.

[0076] 2) Please refer to Figure 3 After photolithographic patterning of the gate region (i.e., the aforementioned under-gate region, i.e., the region directly below the gate, or the region used to grow the gate, the same below), dry etching or other methods are used to remove the (Al)GaN layer 107 and the p-type (Al)GaN 106 in the non-gate region, so that the etching stops at the surface of the AlGaN barrier layer 105A; and a certain surface treatment is performed on the AlGaN barrier layer 105A in the non-gate region (the surface treatment process may be: first acid cleaning with HF, then alkaline wet etching with KOH, and then acid cleaning with HF. This process is only one specific method. Of course, those skilled in the art may also use other surface treatment processes to achieve the same effect, the same below), to remove the surface oxide layer and the damaged layer;

[0077] 3) Depositing gate metal 108 in the gate region of the (Al)GaN layer 107 and annealing to form a gate contact (i.e., Schottky contact, the same below); depositing source metal 109 and drain metal 110 in the source and drain regions, respectively, and annealing to form ohmic contacts; the resulting device structure is as follows: Figure 4a-4c shown.

[0078] In another specific embodiment, see Figure 5-Figure 8 A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0079] 1) Please refer to Figure 5 and Figure 6 A III-nitride depletion-mode HEMT epitaxial structure is grown on a substrate 201. The epitaxial structure specifically includes a transition layer 202, a high-resistance voltage layer 203, a conductive channel layer 204, and a barrier layer 205A with a variable Al composition stacked in sequence. After photolithographic patterning of the gate region, a portion of the variable AlGaN barrier layer located in the gate region is removed by dry etching or other methods.

[0080] 2) Please refer to Figure 7 , a p-type (Al)GaN layer 206 and a low-doping concentration (Al)GaN layer 207 are sequentially grown on the barrier layer 205A using a secondary epitaxial growth method;

[0081] 3) Please refer to Figure 8 After the gate region is patterned by photolithography, the p-type (Al)GaN layer 206 and the (Al)GaN layer 207 in the non-gate region are removed by dry etching or other methods, so that the etching stops at the surface of the AlGaN barrier layer 205A to restore the two-dimensional electron gas in the non-gate region; then, a certain surface treatment is performed on the AlGaN barrier layer 205A in the non-gate region to remove the surface oxide layer and the damaged layer;

[0082] 4) Depositing gate metal 208 on the (Al)GaN layer 207 and annealing to form a stable gate contact; depositing source metal 209 and drain metal 210 in the source region and drain region respectively, and annealing to form ohmic contacts. The device structure formed is as follows: Figure 9a-9c shown.

[0083] It should be noted that the above two solutions may also include more subsequent device processing techniques, such as forming a surface passivation layer and depositing a dielectric layer on the AlGaN barrier layer 106A / B, and then further forming a field plate structure on the gate 208 and the source 209.

[0084] It should be noted that the key points of the above two solutions are that a barrier layer with variable Al composition and a (Al)GaN layer with low doping concentration are introduced into the p-type gate stack structure, that is, the p-type gate stack structure can be understood as a p-type gate, and the p-type gate stack structure or p-type gate includes stacked p-type semiconductors, Al y Ga 1-y N layer and gate (gate metal).

[0085] Specifically, the characteristics and functions of the variable Al composition barrier layer are: the Al composition of the layer at the contact point (i.e., the contact interface) with the p-type semiconductor (e.g., p-type (Al)GaN layer 106 / 206) is consistent, and the Al composition at this contact point is adjustable from 0-100%, specifically, primarily controlled at 0-10%. Of course, the barrier layer can have a variable Al composition within the portion in contact with the p-type semiconductor, or the entire barrier layer can be grown using a gradient Al composition. In this way, there is no significant band gap from the p-type semiconductor to the barrier layer. This makes it difficult for holes to be blocked on the surface of the AlGaN barrier layer under a forward gate voltage, thereby reducing degradation phenomena such as the negative shift of the dynamic threshold voltage. The thickness of the variable Al composition barrier layer is controlled to be 5-50 nm, and the average Al composition is controlled to be 5-50%.

[0086] Specifically, the characteristics and functions of the low-doping concentration (Al)GaN layer (i.e., the aforementioned second semiconductor, the same below) are: the layer has a low doping concentration and a high crystal quality, the layer can be GaN or AlGaN with an Al component of no more than 10%, the layer can be a p-type material (acceptor concentration ≤ 5×10 18 cm -3 ), which can be either undoped material (i.e. not intentionally doped) or n-type material (donor concentration ≤ 5×10 17 cm -3 ), the thickness of this layer is 5-100nm; among them, the introduction of low-doping concentration (Al)GaN can reduce the junction electric field of the junction formed by the metal / semiconductor, thereby reducing the possibility of failure in this area, and thus improving the life and reliability of the device.

[0087] Example 1

[0088] See also Figure 2 、 Figure 3 and Figure 4a A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0089] 1) Using metal organic vapor deposition (MOCVD) method, a 300nm AlN / AlGaN transition layer 102 is deposited on the Si<111> substrate 101, and then a 4μm C-doped Al 0.07 Ga 0.93The N high-resistance layer 103, the 150nm high-quality, low-electron-concentration unintentionally doped GaN layer 104, the 20nm AlGaN barrier layer 105A in which the Al composition gradually changes from 30% to 0% from bottom to top (the "bottom to top" refers to the thickness direction of the layer, where "bottom" refers to the side close to the unintentionally doped GaN layer 104) and the average Al composition is controlled at about 20%, and the 70nm Mg doping concentration is uniformly (2-3)×10 19 cm -3 The p-type GaN layer 106 is 50nm high quality and the Mg doping concentration is reduced to 1×10 18 cm -3 A low-doping concentration p-type GaN layer 107;

[0090] 2) Using a photoresist as a mask, a pattern is formed on the surface of the unintentionally doped GaN layer 107. Then, an inductively coupled plasma (ICP) etching method is used to remove the low-doping concentration p-GaN layer 107 and the uniformly doped p-GaN layer 106 in the non-gate region. The etching is stopped at the AlGaN barrier layer 105A with a variable Al composition to restore the two-dimensional electron gas.

[0091] 3) Acetone or the like is used as a cleaning agent to remove the photoresist, and then hydrofluoric acid (HF) or the like is used to remove the oxide layer on the surface of the AlGaN barrier layer. The epitaxial structure is subjected to a rapid annealing treatment at 500° C. in an N 2 atmosphere to restore the two-dimensional electron gas in the AlGaN / GaN heterojunction. Ti / Au is then deposited as a gate metal 108 on the low-doped p-type GaN layer 107 in the gate region. After annealing, a stable gate contact is formed between the gate metal 108 and the low-doped p-type GaN layer 107. Ti / Al / Ti / Au is deposited as a source metal 109 and a drain metal 110 in the source region and the drain region, respectively. After annealing, ohmic contacts are formed, thereby forming a III-nitride enhancement-mode HEMT device.

[0092] Gate failure tests were conducted on the fabricated devices using IV and It methods, and it was estimated that the operating voltage at which 1% of the devices fail after 10 years of gate operation reached 7.5V. Dynamic threshold voltage drift testing of the obtained III-nitride-enhanced HEMT device using the pulsed IV method revealed a threshold voltage drift of 0.15V (compared to the two sets of data for conventional devices: ≤6.5V and ≥0.4V, respectively). This demonstrates that the p-type gate-enhanced HEMT fabricated by the present invention has high gate reliability and stability.

[0093] Example 2

[0094] See also Figure 2 、 Figure 3 and Figure 4bA method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0095] 1) A 300nm AlN / AlGaN transition layer 102 is deposited on a Si<111> substrate 101 by metal organic vapor deposition (MOCVD) or other methods, and then a 4μm C-doped Al layer is epitaxially grown on the AlN / AlGaN transition layer 102. 0.07 Ga 0.93 N high resistance layer 103, 150nm high quality low electron concentration unintentionally doped GaN layer 104, 10nm Al with uniform Al composition 0.25 Ga 0.75 N barrier layer 105B, 10nm AlGaN barrier layer 105A with variable Al composition (the Al composition in the AlGaN barrier layer 105A gradually changes from 25% to 0% from bottom to top, and the average Al composition is controlled at about 15%), 70nm Mg doping concentration uniformly at (2-3)×10 19 cm -3 p-type GaN layer 106, 50nm high-quality, non-intentionally doped GaN layer 107;

[0096] 2) Using a photoresist as a mask, patterning is performed on the surface of the unintentionally doped GaN layer 107. Subsequently, the unintentionally doped GaN layer 107 and the p-GaN layer 106 in the non-gate region are removed by ICP etching or other methods, with the etching stopping at the variable Al composition AlGaN barrier layer 105A to restore the two-dimensional electron gas.

[0097] 3) The photoresist is removed using an organic cleaning method such as acetone, and then the surface oxide layer of the AlGaN barrier layer is removed using hydrofluoric acid (HF) or the like. Rapid annealing is performed at 500° C. in an N2 atmosphere for a period of time to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction. Ti / Au is then deposited in the gate region as a gate metal 108. After annealing, the gate metal 108 forms a stable gate contact with the unintentionally doped GaN layer 107. Ti / Al / Ti / Au is deposited in the source region and the drain region as a source metal 109 and a drain metal 110, respectively. After annealing, ohmic contacts are formed, thereby forming a III-nitride enhancement-mode HEMT device.

[0098] Gate failure tests were conducted on the fabricated devices using IV and It methods, and it was estimated that the operating voltage at which 1% of the devices fail after 10 years of gate operation is 7.8 V. Dynamic threshold voltage drift testing was conducted on the fabricated III-nitride-enhanced HEMT devices using a pulsed IV method, and the threshold voltage drift of the devices was 0.12 V (compared to the two sets of data for conventional devices: ≤6.5 V and ≥0.4 V, respectively). This demonstrates that the p-type gate-enhanced HEMT fabricated by the present invention has high gate reliability and stability.

[0099] Example 3

[0100] See also Figure 2 、 Figure 3 and Figure 4c A method for preparing a III-nitride enhanced-mode HEMT with high reliability and stability is basically the same as that in Example 2, except that: in this embodiment, the AlGaN barrier layer 105A with a variable Al composition is a p-type semiconductor material, and the AlGaN barrier layer 105A with a variable Al composition is only distributed in the gate region.

[0101] Example 4

[0102] See also Figure 5-8 and Figure 9a A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0103] 1) A 300nm AlN / AlGaN transition layer 202 is deposited on a Si<111> substrate 201 by metal organic vapor deposition (MOCVD) or other methods, and then a 4μm C-doped Al layer is epitaxially grown on the AlN / AlGaN transition layer 202. 0.07 Ga 0.93 N high-resistance layer 203, 150nm high-quality, low-electron-concentration, unintentionally doped GaN layer 204, 50nm AlGaN barrier layer 205A with variable Al composition, wherein the Al composition in the AlGaN barrier layer 205A gradually changes from 30% to 0% along the thickness direction, and the average Al composition of the AlGaN barrier layer 205A is about 15%;

[0104] 2) Using a photoresist as a mask, the AlGaN barrier layer 205A is patterned on the surface of the AlGaN barrier layer 205A by photolithography, and then the AlGaN barrier layer 205A with a thickness of 35 nm in the gate region is removed by etching methods such as ICP to form a pattern structure; then, the AlGaN barrier layer 205A is heat-treated by wet surface treatment and MOCVD high-temperature process, and then a secondary epitaxial layer of 70 nm is sequentially grown on the AlGaN barrier layer 205A with a uniform Mg doping concentration of (2-3)×10 19 cm-3 The p-type GaN layer 206, 50nm high quality, Mg doping concentration reduced to 1×10 18 cm -3 A low-doping concentration p-type GaN layer 207;

[0105] 3) Using a photoresist as a mask, patterning is performed on the p-type GaN layer 207 , and then the low-doping concentration p-GaN layer 207 and the uniformly doped p-GaN layer 206 in the non-gate region are removed by ICP etching or other methods, with the etching stopping at the AlGaN barrier layer 205A with variable Al composition to restore the two-dimensional electron gas;

[0106] 4) using acetone or the like as a cleaning agent to remove the photoresist; then using hydrofluoric acid (HF) or the like to remove the oxide layer on the surface of the AlGaN barrier layer 205A, and rapidly annealing for a period of time at 500° C. in an N 2 atmosphere to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction;

[0107] Ti / Au is deposited in the gate region as the gate metal 208. After annealing, the gate metal 208 forms a stable gate contact with the low-doping concentration p-type GaN layer 207. Ti / Al / Ti / Au are deposited in the source region and the drain region as the source metal 209 and the drain metal 210, respectively. After annealing, ohmic contacts are formed, thereby forming a III-nitride enhancement-mode HEMT device.

[0108] Gate failure tests were conducted on the fabricated devices using IV and It methods, and it was estimated that the operating voltage at which 1% of the devices fail after 10 years of gate operation is 7.5V. Dynamic threshold voltage drift testing of the fabricated III-nitride-enhanced HEMT devices using a pulsed IV method revealed a threshold voltage drift of 0.16V (compared to the two sets of data for conventional devices: ≤6.5V and ≥0.4V, respectively). This demonstrates that the p-type gate-enhanced HEMT fabricated by the present invention has high gate reliability and stability.

[0109] Example 5

[0110] See also Figure 5-8 and Figure 9c A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0111] 1) A 300nm AlN / AlGaN transition layer 202 is deposited on a Si<111> substrate 201 by metal organic vapor deposition (MOCVD) or other methods, and then a 4μm C-doped Al layer is epitaxially grown on the AlN / AlGaN transition layer 202. 0.07 Ga 0.93N high resistance layer 203, 150nm high quality, low electron concentration unintentionally doped GaN layer 204, 10nm Al 0.2 Ga 0.8 N barrier layer 205B, 10nm GaN barrier layer 205D, 25nm Al 0.2 Ga 0.8 N barrier layer 205C;

[0112] 2) Use photoresist as mask, on Al 0.2 Ga 0.8 The N barrier layer 205C is patterned by photolithography, and the Al 0.2 Ga 0.8 The gate region of the N barrier layer 205C is etched to a depth of about 30nm. The surface of the epitaxial structure is sequentially HF pickled, KOH alkaline washed, and HF pickled. Then, it is loaded into MOCVD and thermally decomposed in NH3 atmosphere at 870℃ for 2min. 0.2 Ga 0.8 The N barrier layer 205C and the secondary epitaxial 10nm Al composition variable barrier layer 205A on the gate trench surface, and the 70nm Mg doping concentration are uniformly (2-3)×10 19 cm -3 p-type Al 0.05 Ga 0.95 N layer 206, 50nm high quality, Si doping concentration controlled at about 2×10 17 cm -3 Low doping concentration n-type Al 0.05 Ga 0.95 N layer 207, wherein the Al composition in the Al composition variable barrier layer 205A gradually changes from 20% to 5% along the thickness direction thereof from bottom to top; it should be noted that the Al composition variable barrier layer 205A may be distributed along the inner wall of the gate trench, that is, the surface of the formed Al composition variable barrier layer 205A may be formed with grooves or other pattern structures;

[0113] 3) Use photoresist as a mask to form an n-type Al 0.05 Ga 0.95 The N layer 207 is patterned by photolithography, and the n-type Al in the non-gate area is removed by ICP etching or other methods. 0.05 Ga 0.95 N layer 207, uniformly doped p-type Al 0.05 Ga 0.95 N layer 206, so that the etching stops at the Al composition variable AlGaN barrier layer 205A to restore the two-dimensional electron gas;

[0114] 4) using acetone or the like as a cleaning agent to remove the photoresist; then using hydrofluoric acid (HF) or the like to remove the oxide layer on the surface of the Al component variable barrier layer 205A, and rapidly annealing for a period of time at 500° C. in an N 2 atmosphere to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction;

[0115] Ti / Au is deposited in the gate region as the gate metal 208, and after annealing, the gate metal 208 is bonded to the n-type Al 0.05 Ga 0.95 The N layer 207 forms a stable gate contact, and Ti / Al / Ti / Au is deposited in the source region and the drain region as the source metal 209 and the drain metal 210, respectively. After annealing, an ohmic contact is formed, thereby forming a III-nitride enhanced HEMT device;

[0116] Gate failure tests were conducted on the fabricated devices using IV and It methods, and it was estimated that the operating voltage at which 1% of the devices fail after 10 years of gate operation is 8.0 V. Dynamic threshold voltage drift testing was conducted on the fabricated III-nitride-enhanced HEMT devices using a pulsed IV method, and the threshold voltage drift of the devices was 0.15 V (compared to the two sets of data for conventional devices: ≤6.5 V and ≥0.4 V, respectively). This demonstrates that the p-type gate-enhanced HEMT fabricated by the present invention has high gate reliability and stability.

[0117] Example 6

[0118] See also Figure 5-8 and Figure 9b A method for preparing a III-nitride enhanced HEMT with high reliability and stability comprises the following steps:

[0119] 1) A 300nm AlN / AlGaN transition layer 202 is deposited on a Si<111> substrate 201 by metal organic vapor deposition (MOCVD) or other methods, and then a 4μm C-doped Al layer is epitaxially grown on the AlN / AlGaN transition layer 202. 0.07 Ga 0.93 N high resistance layer 203, 150nm high quality, low electron concentration unintentionally doped GaN layer 204, Al uniform AlGaN barrier layer 205B;

[0120] 2) Using a photoresist as a mask, a pattern is formed on the AlGaN barrier layer 205B. The AlGaN barrier layer 205B in the gate region is removed by ICP etching. The surface of the epitaxial structure is sequentially subjected to HF pickling, KOH alkaline pickling, and HF pickling. After that, the epitaxial structure is loaded into MOCVD and thermally decomposed in an NH3 atmosphere at 870°C for 2 minutes. Then, a secondary epitaxial Al composition variable barrier layer 205A and a 70nm Mg doping concentration uniformly at (2-3)×10 19 cm -3 p-type Al 0.05 Ga 0.95 N layer 206, 50nm high quality, Si doping concentration controlled at about 2×10 17 cm -3 Low doping concentration n-type Al 0.05 Ga 0.95 N layer 207; wherein the Al composition in the Al composition variable barrier layer 205A gradually changes from 20% to 5% along the thickness direction from bottom to top. It should be noted that the Al composition variable barrier layer 205A may be distributed along the surface of the AlGaN barrier layer 205B and the unintentionally doped GaN layer 204, that is, the surface of the formed Al composition variable barrier layer 205A may be formed with grooves or other pattern structures;

[0121] 3) Use photoresist as a mask to form an n-type Al 0.05 Ga 0.95 The N layer 207 is patterned by photolithography, and the n-type Al in the non-gate area is removed by ICP etching or other methods. 0.05 Ga 0.95 N layer 207, uniformly doped p-type Al 0.05 Ga 0.95 N layer 206, so that the etching stops at the Al composition variable AlGaN barrier layer 205A;

[0122] 4) using acetone or the like as a cleaning agent to remove the photoresist; then using hydrofluoric acid (HF) or the like to remove the oxide layer on the surface of the Al component variable barrier layer 205A, and rapidly annealing for a period of time at 500° C. in an N 2 atmosphere to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction;

[0123] Ti / Au is deposited in the gate region as the gate metal 208, and after annealing, the gate metal 208 is bonded to the n-type Al 0.05 Ga 0.95 The N layer 207 forms a stable gate contact, and Ti / Al / Ti / Au is deposited in the source region and the drain region as the source metal 209 and the drain metal 210, respectively. After annealing, an ohmic contact is formed, thereby forming a III-nitride enhanced HEMT device.

[0124] Gate failure tests were conducted on the fabricated devices using IV and It methods, and it was estimated that the operating voltage at which 1% of the devices fail after 10 years of gate operation reached 8.2V. Dynamic threshold voltage drift testing of the fabricated III-nitride-enhanced HEMT devices using the pulsed IV method revealed a threshold voltage drift of 0.12V (compared to the two sets of data for conventional devices, which were ≤6.5V and ≥0.4V, respectively). This demonstrates that the p-type gate-enhanced HEMT fabricated by the present invention has high gate reliability and stability.

[0125] It should be noted that the Al composition variable barrier layer (105A, 205A) in the embodiment of the present invention can be varied in the following ways: i) gradual variation, including linear gradual variation and nonlinear gradual variation; ii) step variation, including equal composition step and non-equal composition step; the doping of the low doping concentration (Al)GaN layer (107, 207) can be: i) p-type, with the surface Mg doping concentration not exceeding 5×10 18 / cm 3 ii) u-type, i.e., unintentional doping, which may be the result of shutting off the Mg source during the growth process; or it may be an unintentional doping layer that grows again after the p-type GaN layer has stopped growing for a period of time; iii) n-type, the Si doping concentration does not exceed 5×10 17 / cm 3 .

[0126] Comparative Example 1

[0127] See also Figure 4d The preparation method of a III-nitride enhanced HEMT is basically the same as that of Example 2, except that the barrier layer in this embodiment only has a 20 nm thick AlGaN 105B layer with a uniform Al composition, wherein the Al content is 0.2.

[0128] The prepared devices were tested for gate failure using IV and It methods. Based on the results, it was calculated that the operating voltage at which 1% of the devices fail after 10 years of gate operation is 7.41V. The prepared III-nitride enhanced HEMT devices were tested for dynamic threshold voltage drift using the pulse IV method, and the threshold voltage drift was 0.65V.

[0129] By comparing Example 1 or Example 2, it can be found that: with the single improvement of the p-GaN surface acceptor doping concentration, the gate operating voltage is greatly improved compared with the conventional device (≤6.5V), indicating that the gate life is extended, but the threshold voltage drift (conventional device ≥0.4V) is not improved.

[0130] Comparative Example 2

[0131] See also Figure 4eThe preparation method of a III-nitride enhanced HEMT is basically the same as that of Example 2, except that: in this embodiment, there is no 50nm Mg 107 layer, and instead, a 120nm Mg doping concentration of (2-3)×10 19 cm -3 106 layers of p-type GaN.

[0132] The prepared devices were subjected to gate failure tests using IV, It and other methods. Based on the results, it was calculated that the operating voltage at which 1% of the devices fail after 10 years of gate operation is 6.02V. The prepared III-nitride enhanced HEMT devices were subjected to dynamic threshold voltage drift tests using the pulse IV method, and the threshold voltage drift was 0.17V.

[0133] By comparing Example 1 or Example 2, it can be found that: for the single improved AlGaN layer band structure, the gate threshold voltage drift of 0.17V is greatly improved compared with conventional devices (≥0.4V), but the gate operating voltage (conventional devices ≤6.5V) is not improved, that is, the gate life is not extended.

[0134] Embodiments of the present invention provide a novel III-nitride enhanced-mode HEMT with high reliability and stability, and a method for preparing the same. A low-doping (Al)GaN layer (i.e., a second semiconductor) is added above a p-GaN layer (i.e., a first semiconductor) to reduce the electric field strength in the metal / semiconductor junction region. Simultaneously, the crystal quality of the surface semiconductor can be improved by changing MOCVD growth conditions, ultimately achieving the preparation of a high-quality metal / semiconductor Schottky junction and improving performance such as the device gate life. Furthermore, the present invention reduces the Al content in the AlGaN barrier layer below the p-GaN layer, or employs a barrier layer with a graded Al content, to reduce or even eliminate the p-GaN / AlGaN band gap. This reduces the hole accumulation effect at the p-GaN / AlGaN interface during dynamic turn-on, thereby improving the dynamic stability and reliability of the device.

[0135] The present invention also adds a low-doping concentration (Al)GaN layer above the p-GaN, and reduces the low Al composition of the AlGaN barrier layer below the p-GaN or adopts a barrier layer with a gradient Al composition, so as to comprehensively improve the service life, dynamic threshold voltage stability and reliability of the p-GaN gate.

[0136] Embodiments of the present invention provide a highly reliable and stable III-nitride-enhanced HEMT device. By adding a low-doping (Al)GaN layer to the p-type semiconductor beneath the gate, the crystal quality of the p-type semiconductor is improved, the electric field strength of the metal / semiconductor Schottky junction region is reduced, and the failure probability of the Schottky junction is reduced. Furthermore, an AlGaN barrier layer with a variable Al composition is provided beneath the p-type semiconductor, thereby reducing or even eliminating the valence band step difference between the p-GaN and AlGaN layers. This overcomes reliability issues such as threshold voltage drift caused by hole accumulation during the dynamic turn-on process. Furthermore, the III-nitride-enhanced HEMT device provided by the present invention has a longer gate operating life and a smaller gate dynamic threshold voltage drift, significantly improving device reliability.

[0137] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent variations or modifications made in accordance with the spirit and substance of the present invention are intended to be encompassed within the scope of protection of the present invention.

Claims

1. A III-nitride enhanced-mode HEMT device comprising an epitaxial structure and a source, a drain, and a gate coordinated with the epitaxial structure, wherein the epitaxial structure comprises a channel layer, a barrier layer, and a p-type semiconductor stacked in sequence, characterized in that: The epitaxial structure further includes an Al stacked on the p-type semiconductor. y Ga 1-y N layer, the gate is set on Al y Ga 1-y On the Nth floor; Wherein, the barrier layer is Al x Ga 1-x N barrier layer or In x Al 1-x N barrier layer, the p-type semiconductor is p-type Al m Ga 1-m N-layer or p-type In m Al 1-m N layer, the Al content at the contact interface between the barrier layer and the p-type semiconductor is lower than the Al content in the remaining areas of the barrier layer, and the Al y Ga 1-y The concentration of the doping element contained in the N layer is lower than the concentration of the doping element contained in the p-type semiconductor; wherein, 0<x≦1, 0≦y≦1, and 0≦m≦1.

2. The III-nitride enhanced HEMT device according to claim 1, wherein: The Al content at the contact interface between the barrier layer and the p-type semiconductor is 0-10%.

3. The III-nitride enhanced HEMT device according to claim 1 or 2, wherein: The Al content in the barrier layer decreases in a direction away from the channel layer.

4. The III-nitride enhanced HEMT device according to claim 3, wherein: The Al content in the barrier layer changes gradually or in a step-like manner in a direction away from the channel layer.

5. The III-nitride enhanced HEMT device according to claim 3, wherein: The average Al content in the barrier layer is 5-50%.

6. The III-nitride enhanced HEMT device according to claim 3, wherein: The thickness of the barrier layer is 1-100 nm.

7. The III-nitride enhanced HEMT device according to claim 1, wherein: The p-type semiconductor and Al y Ga 1-y The N layer only covers the gate region under the barrier layer.

8. The III-nitride enhanced HEMT device according to claim 1, wherein: A groove is formed in the gate-under-gate region of the barrier layer, and the groove is filled with a local region of the p-type semiconductor.

9. The III-nitride enhanced HEMT device according to claim 1, 7 or 8, wherein: The barrier layer includes a first barrier layer and a second barrier layer disposed on the channel layer. The second barrier layer is distributed between the first barrier layer and the p-type semiconductor, and Al content in the second barrier layer decreases in a direction away from the channel layer.

10. The III-nitride enhanced HEMT device according to claim 9, wherein: The Al content in the second barrier layer changes gradually or in a stepwise manner in a direction away from the channel layer.

11. The III-nitride enhanced HEMT device according to claim 9, wherein: The Al component in the first barrier layer is uniformly distributed.

12. The III-nitride enhanced HEMT device according to claim 9, wherein: The second barrier layer continuously covers the first barrier layer; or, the second barrier layer only covers the gate-under-region of the first barrier layer; or, the gate-under-region of the first barrier layer is at least partially removed to form a groove-shaped structure, and the groove-shaped structure is filled with the second barrier layer.

13. The III-nitride enhanced HEMT device according to claim 9, wherein: The second barrier layer has the same conductivity type as the p-type semiconductor.

14. The III-nitride enhanced HEMT device according to claim 12, wherein: The first barrier layer includes a first Al z Ga 1-z N layer, GaN intermediate layer and second Al z Ga 1-z N layers, 0<z≦1.

15. The III-nitride enhanced HEMT device according to claim 14, wherein: The GaN intermediate layer and the second Al z Ga 1-z The regions under the gate of the N layer are all removed to form the trench structure.

16. The III-nitride enhanced HEMT device according to claim 9, wherein: A groove is formed in the lower gate region of the second barrier layer, and the groove is filled with a local region of the p-type semiconductor.

17. The III-nitride enhanced HEMT device according to claim 1, wherein: The Al y Ga 1-y The N layer is p-type, where the acceptor concentration is ≤5×10 18 cm -3 ; Or, the Al y Ga 1-y The N layer is U-shaped; or, the Al y Ga 1- y The N layer is n-type, where the donor concentration is ≤5×10 17 cm -3 .

18. The III-nitride enhanced HEMT device according to claim 17, wherein: The Al y Ga 1-y The thickness of the N layer is 5-100 nm.

19. The III-nitride enhanced HEMT device according to claim 1, wherein: The barrier layer is an unintentionally doped layer.

20. The III-nitride enhanced HEMT device according to claim 1, wherein: The thickness of the p-type semiconductor is 10-300 nm.

21. The III-nitride enhanced HEMT device according to claim 1, wherein: The acceptor doping concentration of the p-type semiconductor is (1-8)×10 19 cm -3 .

22. The III-nitride enhanced HEMT device according to claim 1, characterized in that It also includes a substrate, on which a transition layer and a high-resistance layer are stacked in sequence, and the channel layer is stacked on the high-resistance layer.

23. A method for manufacturing a III-nitride enhanced HEMT device according to any one of claims 1 to 22, characterized in that include: The epitaxial structure includes a channel layer, a barrier layer, a p-type semiconductor and an Al y Ga 1-y N layers; and, A source electrode, a drain electrode and a gate electrode are manufactured to match the epitaxial structure.

24. The production method according to claim 23, characterized in that Specifically include: The channel layer, barrier layer, p-type semiconductor and Al are grown on the substrate in sequence. y Ga 1-y After the N layer, the p-type semiconductor and Al y Ga 1-y The N layer is completely removed except for the area under the gate, and then the remaining Al y Ga 1-y A gate is fabricated on the N layer.

25. The production method according to claim 23, characterized in that Specifically include: A channel layer and a barrier layer are sequentially grown on the substrate, and a portion of the gate region under the barrier layer is removed to form a groove in the barrier layer; then a p-type semiconductor and an Al2O3 layer are continuously grown on the barrier layer. y Ga 1-y N layer, and the groove is filled with a local area of the p-type semiconductor.

26. The production method according to claim 25, characterized in that Specifically include: The p-type semiconductor and Al y Ga 1-y The N layer is completely removed except for the area under the gate, and then the remaining Al y Ga 1-y A gate is fabricated on the N layer.

27. The production method according to claim 23, characterized in that Specifically include: A first barrier layer and a second barrier layer are sequentially grown on the channel layer, thereby forming the barrier layer.

28. The production method according to claim 27, characterized in that Specifically include: Al y Ga 1-y The N layer, the p-type semiconductor and the second barrier layer are completely removed except for the area under the gate.

29. The production method according to claim 27, characterized in that Specifically include: After growing a first barrier layer on the channel layer, the gate-under-region of the first barrier layer is removed to form a groove structure, and then growing a second barrier layer on the first barrier layer and filling the groove structure with the second barrier layer to form the barrier layer.

30. The production method according to claim 29, characterized in that Specifically include: The first Al layer is grown on the channel layer z Ga 1-z N layer, GaN intermediate layer and second Al z Ga 1-z N layer, thereby forming the first barrier layer.

31. The production method according to claim 30, characterized in that Specifically include: The GaN intermediate layer and the second Al z Ga 1-z The gate-under-region of the N layer is removed to form the groove structure, and then a second barrier layer is grown on the first barrier layer, and the groove structure is filled with the second barrier layer, thereby forming the barrier layer.

32. The production method according to claim 30, characterized in that Specifically include: A portion of the second barrier layer in the area below the gate is removed to form a groove, or the second barrier layer is continuously grown along the surface of the first barrier layer and its groove-like structure, so that a groove is formed in the portion of the second barrier layer located within the groove-like structure, and then a p-type semiconductor is grown on the second barrier layer, and the groove is filled with a local area of the p-type semiconductor.

33. The production method according to claim 30, characterized in that Specifically include: P-type semiconductor, Al y Ga 1-y The N layer and the second barrier layer are completely removed except for the area under the gate.

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