A Low Phase Noise and Low Mismatch Current Charge Pump and Its Implementation Method

Abstract

The present invention belongs to the field of integrated circuit design, and discloses a low-phase-noise and low-mismatch current charge pump and an implementation method. The circuit includes a charge and discharge control and voltage regulation circuit, a current mirror replication circuit, and a gain bootstrap circuit. The charge and discharge control and voltage regulation circuit stabilizes the bias voltage of the current mirror and provides a stable charge and discharge current. The current mirror circuit adopts a cascode structure, and together with the voltage regulation circuit, improves the anti-PVT ability. The gain bootstrap circuit can compensate for the current reduction of the current mirror when the output voltage approaches the power supply and ground and enters the linear region, thereby increasing the linear charge and discharge range. The overall circuit achieves low phase noise and low mismatch current, and improves the performance of the charge pump circuit.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and particularly relates to a low-phase-noise and low-mismatch current charge pump and an implementation method thereof. Background Art

[0002] Wired and wireless transceivers have been steadily advancing towards higher speeds. For wired transceivers, the current PAM4 signal rate is as high as 112 Gb / s, and it is expected to rise to 224 Gb / s in the next generation. Using 256QAM in 5G radios operating around 30 GHz poses new challenges. In wired and wireless transceiver systems, the clock is an essential part, so phase-locked loops are also developing towards high speed, low spurs, and low jitter. As an important module in the charge-pump phase-locked loop, the phase-noise performance of the charge pump affects the in-band phase noise of the overall phase-locked loop, thus affecting the jitter performance. And the matching of its charge and discharge currents affects the reference spurs of the clock. Therefore, in high-speed systems, a low-phase-noise and low-mismatch current charge pump has a very important impact on system performance.

[0003] Jae-Shin Lee et al. proposed a high-matching charge pump that uses an operational amplifier to clamp the source-drain voltages of the current sources in the charge path and the discharge path, making the charge and discharge currents match. However, this method requires the use of a high-gain operational amplifier with a wide input range.

[0004] Tsung-Hsien Lin et al. proposed a dynamic current compensation charge pump, which adds two MOS transistors with their gates connected to the output of the charge pump in the circuit to compensate for the current reduction caused by the channel length modulation effect. The magnitude of the compensated current changes with the change of the output voltage. When the voltage increases, the compensated charge current decreases and the compensated discharge current increases. When the voltage decreases, the compensated charge current increases and the discharge current decreases. This method requires setting appropriate transistor sizes to achieve the best compensation effect, with high design difficulty and the need for repeated adjustment.

[0005] Joung-Wook Moon et al. proposed an ultra-low-voltage charge pump that uses the charge pump in combination with an active filter. By providing a bias to the non-inverting input terminal of the active filter with a fixed voltage, the influence of PVT on the charge and discharge currents is reduced. However, this method can only be used in phase-locked loops using active filters and requires cooperation with a calibration module. Summary of the Invention

[0006] The purpose of the present invention is to provide a low-phase-noise and low-mismatch current charge pump and an implementation method thereof to solve the problems of high design difficulty, complex circuit, or limited application scenarios in the above-mentioned existing technologies.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions:

[0008] A low-phase-noise and low-mismatch current charge pump, including a charge pump phase-locked loop, which includes a charge and discharge control and voltage stabilization circuit, a current mirror replication circuit, and a gain bootstrap circuit. The input end of the charge and discharge control and voltage stabilization circuit is connected to a control signal, the output end of the charge and discharge control and voltage stabilization circuit is connected to the input end of the current mirror replication circuit, the output end of the current mirror replication circuit is connected to the input end of the gain bootstrap circuit, and the output end of the gain bootstrap circuit is connected to an output signal.

[0009] Furthermore, the charge and discharge control and voltage stabilization circuit includes a charge and discharge control circuit and a voltage stabilization circuit.

[0010] Furthermore, the current mirror replication circuit includes a current mirror, and the current mirror adopts a cascode structure.

[0011] A method for implementing a low-phase-noise and low-mismatch current charge pump. The charge and discharge control and voltage stabilization circuit is biased by Vbias and controlled by control signals UP and DN for charging and discharging; the output of the charge and discharge control and voltage stabilization circuit provides a stable current and a bias voltage for the current mirror replication circuit, and the current, through the replication effect of the cascode current mirror in the current mirror replication circuit, provides a current for the charge pump to resist the influence of PVT.

[0012] Furthermore, the UP and DN signals are generated by a frequency discriminator and phase detector.

[0013] Furthermore, the charge and discharge control and voltage stabilization circuit includes a charge and discharge control circuit and a voltage stabilization circuit, and the charge and discharge control circuit includes a five-transistor unit.

[0014] Furthermore, the control function of the charge and discharge control and voltage stabilization circuit is implemented by the five-transistor unit.

[0015] Furthermore, the control signal is at the positive input end of the five-transistor unit. When the control signal goes high, the positive input end is turned off, and all the current flows through the branch where the negative input end is located. The five-transistor unit outputs a high level to control the corresponding charge and discharge path of the charge pump to work;

[0016] When the control signal goes low, the positive input end goes low, and all the current flows through the branch of the positive input end. The five-transistor unit outputs a low level to control the corresponding charge and discharge path of the charge pump to be turned off.

[0017] Furthermore, the current mirror replication circuit includes a current mirror, and the current mirror adopts a cascode structure.

[0018] Furthermore, the gain bootstrap circuit is used to expand the linear range of the charge and discharge current of the charge and discharge control and voltage stabilization circuit.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] In the present invention, a charge and discharge control and voltage regulation circuit, a current mirror replication circuit, and a gain bootstrap circuit are provided. The charge and discharge control and voltage regulation circuit stabilizes the bias voltage of the current mirror and provides a stable charge and discharge current. The current mirror circuit adopts a cascode structure, which together with the voltage regulation circuit improves the anti-PVT ability. The gain bootstrap circuit can compensate for the current reduction of the current mirror when the output voltage approaches the power supply and the ground and enters the linear region, thereby increasing the linear charge and discharge range. The overall circuit achieves low phase noise and low mismatch current, improving the performance of the charge pump circuit. Brief Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the low-mismatch charge pump of the present invention;

[0022] Figure 2 It is the transient simulation result of the output voltage of the low-mismatch charge pump of the present invention;

[0023] Figure 3 It is the phase noise simulation result of the low-mismatch charge pump of the present invention;

[0024] Figure 4 It is the simulation result of the charge and discharge current of the low-mismatch charge pump of the present invention at three process corners;

[0025] Figure 5 It is the simulation result of the charge and discharge current mismatch of the low-mismatch charge pump of the present invention at three process corners;

[0026] Figure 6 It is the result of 1000 - time Monte Carlo simulation of the mismatch current of the low-mismatch charge pump of the present invention. Detailed Description of the Invention

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings.

[0030] A method for realizing a low-phase-noise and low-mismatch-current charge pump for a charge pump phase-locked loop according to the present invention. The circuit includes a charge and discharge control and voltage stabilization circuit, a current mirror replication circuit, and a gain bootstrap circuit; the charge and discharge control and voltage stabilization circuit is biased by Vbias, and the charging and discharging are controlled by the control signals UP and DN signals. In the phase-locked loop, the UP and DN signals are generated by a frequency discriminator and phase detector; the output of the charge and discharge control and voltage stabilization circuit provides a stable current and bias voltage for the current mirror circuit, and through the replication function of the cascode current mirror, provides a current for the charge pump to resist the influence of PVT; the gain bootstrap circuit increases the linear charge and discharge range, and reduces the charge and discharge mismatch current of the charge pump.

[0031] The control function of the charge and discharge control and voltage stabilization circuit is realized by a five-transistor unit in the circuit. The control signal is at the positive input terminal of the five-transistor unit. When the control signal goes high, the positive input terminal is turned off, and all the current flows through the branch where the inverting input terminal is located. The five-transistor unit outputs a high level to control the corresponding charge and discharge path of the charge pump to work; conversely, when the control signal goes low, the positive input terminal goes low, and all the current flows through the branch of the positive input terminal. The five-transistor unit outputs a low level to control the corresponding charge and discharge path of the charge pump to be turned off. The principle of the voltage stabilization circuit is similar to that of a low-dropout linear regulator. The two-stage operational amplifier is used as the error amplifier of the low-dropout linear regulator. By comparing the control signal and the feedback signal, the error is fed back to the power transistor. Therefore, when PVT changes, due to the action of the low-dropout linear regulator, the level of point S will always be constant. And the power supply voltage and the resistor are also constant. Therefore, the output of the low-dropout linear regulator will generate a constant current to provide a stable current and operating point for the current mirror.

[0032] The current mirror replicates the current generated by the voltage stabilization circuit, and at the same time, point S in the circuit is less affected by PVT. And the cascode current mirror can also resist the influence of PVT changes. The stability of point S and the use of the cascode current mirror both improve the ability of the current mirror to resist PVT.

[0033] The gain bootstrap circuit can expand the linear range of the charge and discharge current. Since when the voltage of the charge pump output Vout is too large or too small, the MOS transistor in the output path will enter the linear region, resulting in a decrease in the charge and discharge current, and the trend of increasing or decreasing the output voltage is no longer linear. The gain bootstrap circuit can supplement the current reduced when the MOS transistor enters the linear region, thereby increasing the linear charge and discharge range.

[0034] See Figure 1 , for the charging circuit, the charge and discharge control and voltage stabilizing circuit consists of several MOS transistors, compensation unit C c0 and R z0 as well as the feedback network R0, R1, R fb .

[0035] The several MOS transistors include the first MOS transistor M0, the second MOS transistor M1, the third MOS transistor M2, the fourth MOS transistor M3, the fifth MOS transistor M4, the sixth MOS transistor M5, the seventh MOS transistor M6, the eighth MOS transistor M7, the ninth MOS transistor M8, the tenth MOS transistor M9, and the eleventh MOS transistor M10.

[0036] The compensation unit includes a compensation capacitor C c0 and a compensation resistor R z0 .

[0037] The feedback network includes a first resistor R0, a second resistor R1, and a third resistor R fb .

[0038] The sources of the second MOS transistor M1, the seventh MOS transistor M6, the ninth MOS transistor M8, and the eleventh MOS transistor M10 are connected to VDD, and one end of the compensation capacitor C c0 is connected to VDD.

[0039] The gate of the first MOS transistor M0 is connected to Vbias, the drain of the first MOS transistor M0 is connected to the drain of the second MOS transistor M1, the drain of the first MOS transistor M0 is also connected to the gate of the seventh MOS transistor M6, and the gate of the first MOS transistor M0 is connected to the gate of the seventh MOS transistor M6.

[0040] The gate of the fifth MOS transistor M4 is connected to the control signal, and the sources of the fifth MOS transistor M4 and the sixth MOS transistor M5 are both connected to the drain of the seventh MOS transistor M6. The drain of the fifth MOS transistor M4 is connected to the gate and drain of the third MOS transistor M2. The drain of the fourth MOS transistor M3 and the gate of the eighth MOS transistor M7 are both connected to the drain of the sixth MOS transistor M5. The gate of the sixth MOS transistor M5 is connected to one end of the third resistor R fb and the third resistor R fbThe other end of and one end of the first resistor R0 are both connected to the drain of the tenth MOS transistor M9. The third resistor R fb The connection point of the other end of and one end of the first resistor R0 to the drain of the tenth MOS transistor M9 is point S.

[0041] Compensation capacitor C c0 The other end of is connected to the compensation resistor R z0 One end of the compensation resistor R z0 The other end of, the drain of the ninth MOS transistor M8, and the drain of the eighth MOS transistor M7 are connected to the gate of the eleventh MOS transistor M10. The drain of the eleventh MOS transistor M10 is connected to the source of the tenth MOS transistor M9. The gate of the tenth MOS transistor M9 is also connected to one end of the second resistor R1.

[0042] The other end of the first resistor R0 is connected to one end of the second resistor R1. The other end of the second resistor R1, the source of the first MOS transistor M0, the source of the third MOS transistor M2, and the source of the fourth MOS transistor M3 are connected to the source of the eighth MOS transistor M7. The source of the eighth MOS transistor M7 is also connected to the connected current mirror replication circuit.

[0043] The current mirror replication circuit includes the twelfth MOS transistor M11, the thirteenth MOS transistor M12, the fourteenth MOS transistor M13, the fifteenth MOS transistor M14, the sixteenth MOS transistor M15, the seventeenth MOS transistor M16, the eighteenth MOS transistor M17, the twenty-first MOS transistor M20, the twenty-second MOS transistor M21, and the twenty-third MOS transistor M22.

[0044] The gain bootstrap circuit includes the nineteenth MOS transistor M18 and the twentieth MOS transistor M19.

[0045] The source of the eighteenth MOS transistor M17, the source of the seventeenth MOS transistor M16, the source of the twentieth MOS transistor M19, the source of the twenty-third MOS transistor M22, the gate of the twenty-third MOS transistor M22, and the source of the twenty-second MOS transistor M21 are connected to VDD.

[0046] The drain of the eighteenth MOS transistor M17 and the drain of the seventeenth MOS transistor M16 are connected to the source of the sixteenth MOS transistor M15. The drain of the fourteenth MOS transistor M13 and the gate of the twelfth MOS transistor M11 are connected to the drain of the sixteenth MOS transistor M15. The source of the fourteenth MOS transistor M13 and the drain of the twelfth MOS transistor M11 are connected.

[0047] The drain of the twenty-third MOS transistor M22 and the drain of the twenty-second MOS transistor M21 are connected to the source of the twenty-first MOS transistor M20. The gate of the twenty-first MOS transistor M20 is connected to the gate of the seventeenth MOS transistor M16. The drain of the twenty-first MOS transistor M20 and the gate of the twentieth MOS transistor M19 are connected to the source of the nineteenth MOS transistor M18. The drain of the nineteenth MOS transistor M18 is connected to the signal Vout. The drain of the twentieth MOS transistor M19 and the drain of the fifteenth MOS transistor M14 are connected to the gate of the nineteenth MOS transistor M18. The source of the fifteenth MOS transistor M14 is connected to the drain of the thirteenth MOS transistor M12. The sources of the thirteenth MOS transistor M12 and the twelfth MOS transistor M11 are connected to the source of the eighth MOS transistor M7.

[0048] When the UP signal is at a high level, the drain of the fourth MOS transistor M3 is at a high level, and the drain of the eighth MOS transistor M7 is at a low level. The eleventh MOS transistor M10 can operate normally, so it will provide current and bias voltage for the current mirror circuit, and the charging circuit starts to charge normally.

[0049] When the UP signal is at a low level, the eleventh MOS transistor M10 is turned off or conducts a very small current, and the tenth MOS transistor M9 cannot conduct, so the charging circuit stops charging. Since the UP signal is provided by the phase frequency detector, its high level remains constant under PVT. Due to the negative feedback of the voltage regulator circuit, no matter how PVT changes, the voltage at point S can be maintained stable, so the mismatch of the current mirror circuit can be reduced. The current mirrors all adopt the cascode structure, which further reduces the mismatch. The function of the gain bootstrap circuit is to increase the linear range of charge and discharge.

[0050] Similarly, for the discharging circuit, when the output voltage Vout is too low, the forty-third MOS transistor M42 and the forty-fourth MOS transistor M43 will enter the linear region, resulting in the discharging current decreasing as the output voltage Vout decreases. And the voltage at point A (the connection point of the source of the forty-fifth MOS transistor M44, the gate of M45, and the drain of the forty-fourth MOS transistor M43) also decreases. Therefore, the voltage at point B (the connection point of the drain of the thirty-eighth MOS transistor M37, the drain of M45, and the gate of the forty-fifth MOS transistor M44) increases. The increase in the gate voltage of the forty-fifth MOS transistor M44 ensures that the discharging current continues to remain constant, thereby increasing the linear range of discharging.

[0051] See Figure 2 , the output voltage of the charge pump has good linearity during the charging and discharging processes, and the charge and discharge are symmetric.

[0052] See Figure 3, The phase noise curve of the charge pump output has a phase noise lower than -98 dBc / Hz in the range of 10 kHz to 100 MHz. As the control frequency increases, the poles at high frequencies also shift towards higher frequencies, thus weakening the influence of the spikes.

[0053] See Figure 4 , The charge and discharge current curves at three process corners are matched, and the charge and discharge currents are linear within the output voltage range of 0.6 - 2.3V.

[0054] See Figure 5 , The charge and discharge mismatch currents at three process corners are very small and have a large linear range.

[0055] See Figure 6 , The Monte Carlo simulation results of 1000 points of the mismatch current show that the mean value of the mismatch current is as low as 83 nA, and the standard deviation is only 6.2 μA. Within 3σ, the mismatch current is lower than 19 μA, that is, lower than 19%.

Claims

1. A low-phase-noise and low-mismatch current charge pump, characterized in that, including several MOS transistors and compensation unit C c0 and R z0 and feedback network R0, R1, R fb components; A number of MOS transistors include a first MOS transistor M0, a second MOS transistor M1, a third MOS transistor M2, a fourth MOS transistor M3, a fifth MOS transistor M4, a sixth MOS transistor M5, a seventh MOS transistor M6, an eighth MOS transistor M7, a ninth MOS transistor M8, a tenth MOS transistor M9, and an eleventh MOS transistor M10; The compensation unit includes a compensation capacitor C c0 and a compensation resistor R z0 ; The feedback network includes a first resistor R0, a second resistor R1, and a third resistor R fb ; The sources of the second MOS transistor M1, the seventh MOS transistor M6, the ninth MOS transistor M8, and the eleventh MOS transistor M10 are connected to VDD, and one end of the compensation capacitor C c0 is connected to VDD; The gate of the first MOS transistor M0 is connected to Vbias, the drain of the first MOS transistor M0 is connected to the drain of the second MOS transistor M1, the drain of the first MOS transistor M0 is also connected to the gate of the seventh MOS transistor M6, and the gate of the first MOS transistor M0 is connected to the gate of the seventh MOS transistor M6; The gate of the fifth MOS transistor M4 is connected to the control signal. The sources of the fifth MOS transistor M4 and the sixth MOS transistor M5 are both connected to the drain of the seventh MOS transistor M6. The drain of the fifth MOS transistor M4 is connected to the gate and the drain of the third MOS transistor M2. The drains of the fourth MOS transistor M3 and the eighth MOS transistor M7 are both connected to the drain of the sixth MOS transistor M5. The gate of the sixth MOS transistor M5 is connected to one end of the third resistor R fb One end of the third resistor R fb And one end of the first resistor R0 are both connected to the drain of the tenth MOS transistor M9. The connection point of the other end of the third resistor R fb And one end of the first resistor R0 to the drain of the tenth MOS transistor M9 is point S; Compensation capacitor C c0 The other end of which is connected to one end of compensation resistor R z0 One end of compensation resistor R z0 The other end, the drain of the ninth MOS transistor M8, and the drain of the eighth MOS transistor M7 are connected to the gate of the eleventh MOS transistor M10. The drain of the eleventh MOS transistor M10 is connected to the source of the tenth MOS transistor M9. The gate of the tenth MOS transistor M9 is also connected to one end of the second resistor R1; The other end of the first resistor R0 is connected to one end of the second resistor R1, and the other end of the second resistor R1, the source of the first MOS transistor M0, the source of the third MOS transistor M2, and the source of the fourth MOS transistor M3 are connected to the source of the eighth MOS transistor M7, and the source of the eighth MOS transistor M7 is also connected to a connected current mirror replication circuit; The current mirror replication circuit includes a twelfth MOS transistor M11, a thirteenth MOS transistor M12, a fourteenth MOS transistor M13, a fifteenth MOS transistor M14, a sixteenth MOS transistor M15, a seventeenth MOS transistor M16, an eighteenth MOS transistor M17, a twenty - first MOS transistor M20, a twenty - second MOS transistor M21, and a twenty - third MOS transistor M22; The gain bootstrap circuit includes a nineteenth MOS transistor M18 and a twentieth MOS transistor M19; The source of the eighteenth MOS transistor M17, the source of the seventeenth MOS transistor M16, the source of the twentieth MOS transistor M19, the source of the twenty - third MOS transistor M22, the gate of the twenty - third MOS transistor M22, and the source of the twenty - second MOS transistor M21 are connected to VDD; The drain of the eighteenth MOS transistor M17 and the drain of the seventeenth MOS transistor M16 are connected to the source of the sixteenth MOS transistor M15, the drain of the fourteenth MOS transistor M13 and the gate of the twelfth MOS transistor M11 are connected to the drain of the sixteenth MOS transistor M15, and the source of the fourteenth MOS transistor M13 and the drain of the twelfth MOS transistor M11 are connected; The drain of the twenty - third MOS transistor M22 and the drain of the twenty - second MOS transistor M21 are connected to the source of the twenty - first MOS transistor M20, the gate of the twenty - first MOS transistor M20 is connected to the gate of the sixteenth MOS transistor M15, the gate of the seventeenth MOS transistor M16 is connected to the gate of the twenty - second MOS transistor M21, the drain of the twenty - first MOS transistor M20 and the gate of the twentieth MOS transistor M19 are connected to the source of the nineteenth MOS transistor M18, the drain of the nineteenth MOS transistor M18 is connected to the signal Vout, the drain of the twentieth MOS transistor M19 and the drain of the fifteenth MOS transistor M14 are connected to the gate of the nineteenth MOS transistor M18, the source of the fifteenth MOS transistor M14 is connected to the drain of the thirteenth MOS transistor M12, and the source of the thirteenth MOS transistor M12 and the source of the twelfth MOS transistor M11 are connected to the source of the eighth MOS transistor M7; The gate of the tenth MOS transistor M9 is connected to the gate of the sixteenth MOS transistor M15, and the gate of the eleventh MOS transistor M10 is connected to the other end of the gate of the seventeenth MOS transistor M16 and the compensation resistor R z0 ​ The gate of the eighteenth MOS transistor M17 is connected to VDD.

2. The low-phase-noise and low-mismatch current charge pump according to claim 1, wherein The current mirror replication circuit includes a current mirror, and the current mirror adopts a cascode structure.

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