A dual-phase dickson switched capacitor converter

Abstract

The application belongs to the technical field of switching power supply, and an auxiliary circuit is added between two branches of a traditional two-phase Dickson converter; in a dead time when all main power tubes are closed, the auxiliary circuit can transfer the charge of one branch to another branch, realizes zero-voltage turn-on of all main power tubes, and reduces switching loss.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, specifically relating to a two-phase Dickson switched capacitor converter. Background Technology

[0002] Traditional inductive DC-DC converters, such as buck, boost, and buck-boost converters, are widely used in 5G base stations, server power supplies, and mobile phone motherboards to convert between different voltages. However, due to significant switching and inductance losses, the conversion efficiency of inductive DC-DC converters is typically low. Applications such as high-energy-consuming 5G communication and high-power fast charging for mobile phones demand much higher conversion efficiency from inductive DC-DC converters. Traditional inductive DC-DC converters can no longer meet these efficiency requirements.

[0003] Compared to inductors, capacitors have a higher energy density. Therefore, switched-capacitor converters, which use capacitors for energy transfer, have a much higher conversion efficiency than inductive DC-DC converters and are widely used in various high-efficiency applications. Cascaded switched-capacitor converters are widely used due to their low equivalent impedance.

[0004] like Figure 1 As shown, the existing two-phase Dickson 4:1 switched capacitor converter includes 12 power transistors (Q1, Q2, Q3, Q4, Q5A, Q5B, Q6A, Q6B, Q7A, Q7B, Q8A, and Q8B); six capacitors (C1A, C1B, C2A, C2B, C3A, and C3B); an input capacitor CIN; an output capacitor COUT; and an output load IOUT. In terms of control, power transistors Q1, Q3, Q5A, Q7A, Q6B, and Q8B are driven by the same control signal, as are power transistors Q2, Q4, Q6A, Q8A, Q5B, and Q7B. Both control signals are 50% duty cycle square wave signals, and their waveforms are complementary. This two-phase Dickson 4:1 switched capacitor converter allows the output voltage VOUT to be 1 / 4 of the input voltage, i.e., VIN = 4 * VOUT. The voltage differences across the six capacitors are VC1A = VC1B = VOUT, VC2A = VC2B = 2 * VOUT, and VC3A = VC3B = 3 * VOUT.

[0005] While existing dual-phase 4:1 Dickson switched-capacitor converters have no turn-off or inductance losses, they still require overcoming the parasitic capacitances Cds and Cgd when the power transistors are turned on, resulting in some turn-on losses. In high-voltage, low-current applications, the higher the voltage difference between Cds and Cgd, the greater their proportion in turn-on losses, limiting further improvements in the conversion efficiency of dual-phase Dickson 4:1 switched-capacitor converters. Summary of the Invention

[0006] This application addresses the aforementioned problems by proposing a novel two-phase Dickson switched-capacitor converter. By adding auxiliary circuitry, zero-voltage turn-on of all main power transistors can be achieved, reducing switching losses. Furthermore, this two-phase Dickson switched-capacitor converter can be a two-phase N:1 Dickson switched-capacitor converter, where N is an integer greater than or equal to 3.

[0007] One aspect of this application provides a two-phase Dickson switched capacitor converter, including a first branch, a second branch, and an auxiliary circuit. The auxiliary circuit is connected between the first branch and the second branch. The power transistors of the first branch and the second branch are main power transistors. The auxiliary circuit is used to transfer the charge of one branch of the first branch to the other branch during the dead time when all main power transistors are turned off, so that the voltage difference across each main power transistor becomes zero, thereby enabling each main power transistor to turn on at zero voltage.

[0008] In some embodiments, the two-phase Dickson switched capacitor converter is a two-phase Dickson 4:1 switched capacitor converter, the first branch including a first power transistor, a second power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a first capacitor, a second capacitor, and a third capacitor; the second branch including a fourth power transistor, a third power transistor, a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, a fourth capacitor, a fifth capacitor, and a sixth capacitor.

[0009] The first terminals of the eighth and twelfth power transistors are connected to the input terminals of the two-phase Dickson switched capacitor converter, which are connected to the external input voltage. The second terminal of the eighth power transistor is connected to the first terminal of the seventh power transistor and the first terminal of the third capacitor, respectively. The second terminal of the twelfth power transistor is connected to the first terminal of the eleventh power transistor and the first terminal of the sixth capacitor, respectively.

[0010] The second terminal of the seventh power transistor is connected to the first terminal of the sixth power transistor and the first terminal of the fifth capacitor, respectively. The second terminal of the eleventh power transistor is connected to the first terminal of the tenth power transistor and the first terminal of the second capacitor, respectively.

[0011] The second terminal of the sixth power transistor is connected to the first terminal of the fifth power transistor and the first terminal of the first capacitor, respectively. The second terminal of the tenth power transistor is connected to the first terminal of the ninth power transistor and the first terminal of the fourth capacitor, respectively.

[0012] The second end of the fifth power transistor is connected to the first end of the second power transistor, and the second end of the ninth power transistor is connected to the first end of the third power transistor.

[0013] The second terminal of the second power transistor is connected to the first terminal of the first power transistor, the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the third capacitor, respectively; the second terminal of the third power transistor is connected to the first terminal of the fourth power transistor, the second terminal of the fourth capacitor, the second terminal of the fifth capacitor, and the second terminal of the sixth capacitor, respectively; the second terminals of the first power transistor and the second terminals of the fourth power transistor are grounded.

[0014] The connection point of the second terminal of the fifth power transistor, the first terminal of the second power transistor, the first terminal of the third power transistor, and the second terminal of the ninth power transistor is the output terminal of the two-phase Dickson switched capacitor converter.

[0015] The connection point of the first terminal of the first power transistor, the second terminal of the second power transistor, the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the third capacitor is the first node of the first branch. The connection point of the second terminal of the third power transistor, the first terminal of the fourth power transistor, the second terminal of the fourth capacitor, the second terminal of the fifth capacitor, and the second terminal of the sixth capacitor is the second node of the second branch.

[0016] In some embodiments, the auxiliary circuit includes a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor, and an inductor; the first terminal of the thirteenth power transistor is connected to a first node, the second terminal of the thirteenth power transistor is connected to the first terminal of the fourteenth power transistor and the first terminal of the inductor, and the second terminal of the fourteenth power transistor is grounded; the second terminal of the inductor is connected to the first terminal of the fifteenth power transistor and the first terminal of the sixteenth power transistor, the second terminal of the fifteenth power transistor is grounded, and the second terminal of the sixteenth power transistor is connected to a second node.

[0017] In some embodiments, the operating timing of the two-phase Dickson switched capacitor converter includes four stages, as described below.

[0018] Phase 1: The second, fourth, sixth, eighth, ninth, eleventh, fourteenth, and sixteenth power transistors are turned on, while the other power transistors are turned off; the first, second, and third capacitors are in a charging state, while the fourth, fifth, and sixth capacitors are in a discharging state, and the inductor current is 0.

[0019] Second stage: The thirteenth and sixteenth power transistors are turned on, while the other power transistors are turned off; the inductor current first rises and then falls, and the second stage ends when the inductor current drops to 0.

[0020] Phase 3: The first, third, fifth, seventh, tenth, twelfth, thirteenth, and fifteenth power transistors are turned on, while the other power transistors are turned off; the first, second, and third capacitors are in a discharging state, while the fourth, fifth, and sixth capacitors are in a charging state, and the inductor current is 0.

[0021] Phase 4: The thirteenth and sixteenth power transistors are turned on, while the other power transistors are turned off; the inductor current first rises and then falls, and when the inductor current drops to 0, Phase 4 ends and returns to Phase 1.

[0022] In some embodiments, the two-phase Dickson switched-capacitor converter is a two-phase N:1 Dickson switched-capacitor converter, where N is an integer greater than or equal to 5; the first branch includes a first power transistor, a second power transistor, N first sub-power transistors and N-1 first sub-capacitors, and the second branch includes a third power transistor, a fourth power transistor, N second sub-power transistors and N-1 second sub-capacitors; the two ends of the auxiliary circuit are respectively connected to a first node between the interconnected first power transistors and second power transistors and a second node between the interconnected third power transistors and fourth power transistors.

[0023] The input terminals of the two-phase Dickson switched capacitor converter are connected to the output terminals of the two-phase N:1 Dickson switched capacitor converter in sequence through N first sub-power transistors and N second sub-power transistors. The N first sub-power transistors are connected in sequence, and the N second sub-power transistors are connected in sequence.

[0024] Two adjacent first sub-power transistors form a first sub-power transistor pair, and two adjacent first sub-power transistor pairs include an identical first sub-power transistor; two adjacent second sub-power transistors form a second sub-power transistor pair, and two adjacent second sub-power transistor pairs include an identical second sub-power transistor.

[0025] Any two adjacent first sub-power transistor pairs include a first pair of first sub-power transistor pairs and a second pair of first sub-power transistor pairs. The first end of a first sub-capacitor is connected between the two first sub-power transistors of the first pair of first sub-power transistor pairs, and the first end of a second sub-capacitor is connected between the two first sub-power transistors of the second pair of first sub-power transistor pairs.

[0026] Any two adjacent pairs of second sub-power transistors include a first pair of second sub-power transistors and a second pair of second sub-power transistors. The first end of another first sub-capacitor is connected between the two second sub-power transistors of the first pair of second sub-power transistors, and the first end of another second sub-capacitor is connected between the two second sub-power transistors of the second pair of second sub-power transistors.

[0027] A first sub-capacitor is connected between the two first sub-power transistors of a first sub-power transistor pair connected to the output terminal, and a second sub-capacitor is connected between the two second sub-power transistors of a second sub-power transistor pair connected to the output terminal.

[0028] The second terminal of all first sub-capacitors is connected to the first node, and the second terminal of all second sub-capacitors is connected to the second node.

[0029] In some embodiments, the auxiliary circuit includes a thirteenth power transistor, a sixteenth power transistor, a first diode, a second diode, and an inductor; the first end of the thirteenth power transistor is connected to a first node, the second end of the thirteenth power transistor is connected to the first end of the first diode and the first end of the inductor, and the second end of the first diode is grounded; the second end of the inductor is connected to the first end of the second diode and the first end of the sixteenth power transistor, the second end of the second diode is grounded, and the second end of the sixteenth power transistor is connected to a second node.

[0030] In some embodiments, the auxiliary circuit includes a thirteenth power transistor, a sixteenth power transistor, and an inductor; wherein, the first end of the thirteenth power transistor is connected to a first node, the second end of the thirteenth power transistor is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the sixteenth power transistor, and the second end of the sixteenth power transistor is connected to a second node.

[0031] In some embodiments, the thirteenth, sixteenth, fifteenth, and sixteenth power transistors are all N-type power transistors; or, the thirteenth and sixteenth power transistors are both P-type power transistors, and the sixteenth and fifteenth power transistors are both N-type power transistors.

[0032] In some embodiments, the thirteenth power transistor and the sixteenth power transistor are both N-type power transistors or P-type power transistors.

[0033] The above scheme is one control timing sequence. Based on the above circuit structure, there are of course many other control timing sequences.

[0034] This application embodiment adds an auxiliary circuit (including four power transistors and one inductor) between the two branches of a traditional two-phase Dickson switched-capacitor converter. During the dead time when all main power transistors are off, the auxiliary circuit transfers charge from one branch to the other, achieving zero-voltage turn-on of all main power transistors and reducing switching losses. The on-resistance of the power transistors in the added auxiliary circuit is much larger than that of the main power transistors, while the inductance of the inductor in the auxiliary circuit is very small, resulting in low package size and cost. Therefore, this application embodiment, by adding a low-cost auxiliary circuit, can significantly reduce the switching losses of the switched-capacitor converter, improve conversion efficiency, and offers excellent performance benefits and commercial prospects. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the circuit structure of a traditional two-phase 4:1 Dickson switched capacitor converter.

[0036] Figure 2 This is a schematic diagram of the circuit structure of a dual-phase 4:1 Dickson switched-capacitor converter according to an embodiment of this application.

[0037] Figure 3 This is a schematic diagram of the operating timing of a two-phase 4:1 Dickson switched capacitor converter according to an embodiment of this application.

[0038] Figure 4 This is an equivalent circuit diagram of the dual-phase 4:1 Dickson switched capacitor converter operating in Stage 0 of this application embodiment.

[0039] Figure 5 This is an equivalent circuit diagram of the dual-phase 4:1 Dickson switched capacitor converter operating in Stage 1 according to an embodiment of this application.

[0040] Figure 6 This is an equivalent circuit diagram of the dual-phase 4:1 Dickson switched capacitor converter operating in Stage 2 according to an embodiment of this application.

[0041] Figure 7 This is an equivalent circuit diagram of the dual-phase 4:1 Dickson switched capacitor converter operating in Stage 3 according to an embodiment of this application.

[0042] Figure 8 This is a schematic diagram of a two-phase N:1 ZVS switched capacitor converter based on an embodiment of this application.

[0043] Figure 9 The diagram shows various auxiliary circuit structures according to embodiments of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this application are only for explaining this application and are not intended to limit this application.

[0045] like Figure 2 As shown in the embodiment of this application, the dual-phase 4:1 Dickson switched-capacitor converter includes a main power circuit and an auxiliary circuit. The main power circuit includes 12 main power transistors (i.e., the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5A, the ninth power transistor Q5B, the sixth power transistor Q6A, the tenth power transistor Q6B, the seventh power transistor Q7A, the eleventh power transistor Q7B, the eighth power transistor Q8A, and the twelfth power transistor Q8B), 6 capacitors (i.e., the first capacitor C1A, the fourth capacitor C1B, the fifth capacitor C2A, the second capacitor C2B, the third capacitor C3A, and the sixth capacitor C3B), an input capacitor CIN, an output capacitor COUT, and an output load IOUT. The auxiliary circuit includes 4 auxiliary power transistors (i.e., the thirteenth power transistor QX1A, the fourteenth power transistor QX2A, the sixteenth power transistor QX1B, and the fifteenth power transistor QX2B) and one auxiliary inductor L.

[0046] The main power circuit includes two branches, namely the first branch and the second branch. The first branch includes the first power transistor Q1, the second power transistor Q2, the fifth power transistor Q5A, the sixth power transistor Q6A, the seventh power transistor Q7A, the eighth power transistor Q8A, the first capacitor C1A, the second capacitor C2B, and the third capacitor C3A. The second branch includes the fourth power transistor Q4, the third power transistor Q3, the ninth power transistor Q5B, the tenth power transistor Q6B, the eleventh power transistor Q7B, the twelfth power transistor Q8B, the fourth capacitor C1B, the fifth capacitor C2A, and the sixth capacitor C3B.

[0047] The first terminal of the eighth power transistor Q8A and the first terminal of the twelfth power transistor Q8B are connected to the input terminal VIN of the two-phase Dickson switched capacitor converter, which is connected to the external input voltage. The second terminal of the eighth power transistor Q8A is connected to the first terminal of the third capacitor C3A and the first terminal of the seventh power transistor Q7A, respectively. The second terminal of the twelfth power transistor Q8B is connected to the first terminal of the sixth capacitor C3B and the first terminal of the eleventh power transistor Q7B, respectively.

[0048] The second terminal of the seventh power transistor Q7A is connected to the first terminal of the fifth capacitor C2A and the first terminal of the sixth power transistor Q6A, respectively. The second terminal of the eleventh power transistor Q7B is connected to the first terminal of the second capacitor C2B and the first terminal of the tenth power transistor Q6B, respectively.

[0049] The second terminal of the sixth power transistor Q6A is connected to the first terminal of the first capacitor C1A and the first terminal of the fifth power transistor Q5A, respectively. The second terminal of the tenth power transistor Q6B is connected to the first terminal of the fourth capacitor C1B and the first terminal of the ninth power transistor Q5B, respectively.

[0050] The second end of the fifth power transistor Q5A is connected to the first end of the second power transistor Q2, and the second end of the ninth power transistor Q5B is connected to the first end of the third power transistor Q3.

[0051] The second terminal of the second power transistor Q2 is connected to the first terminal of the first power transistor Q1, the second terminal of the first capacitor C1A, the second terminal of the second capacitor C2B, and the second terminal of the third capacitor C3A, respectively; the second terminal of the third power transistor Q3 is connected to the first terminal of the fourth power transistor Q4, the second terminal of the fourth capacitor C1B, the second terminal of the fifth capacitor C2A, and the second terminal of the sixth capacitor C3B, respectively; the second terminals of the first power transistor Q1 and the second terminals of the fourth power transistor Q4 are grounded.

[0052] The connection point of the second terminal of the fifth power transistor Q5A, the first terminal of the second power transistor Q2, the first terminal of the third power transistor Q3, and the second terminal of the ninth power transistor Q5B is the output terminal VOUT of the two-phase Dickson switched capacitor converter.

[0053] The connection point of the first terminal of the first power transistor Q1, the second terminal of the second power transistor Q2, the second terminal of the first capacitor C1A, the second terminal of the second capacitor C2B, and the second terminal of the third capacitor C3A is the first node CFLA of the first branch. The connection point of the second terminal of the third power transistor Q3, the first terminal of the fourth power transistor Q4, the second terminal of the fourth capacitor C1B, the second terminal of the fifth capacitor C2A, and the second terminal of the sixth capacitor C3B is the second node CFLB of the second branch.

[0054] The auxiliary circuit includes a thirteenth power transistor QX1A, a fourteenth power transistor QX2A, a fifteenth power transistor QX2B, a sixteenth power transistor QX1B, and an inductor L. The first terminal of the thirteenth power transistor QX1A is connected to the first node CFLAA of the first branch, and the second terminal of the thirteenth power transistor QX1A is connected to the first terminal of the fourteenth power transistor QX2A and the first terminal of the inductor L. The second terminal of the fourteenth power transistor QX2A is grounded. The second terminal of the inductor L is connected to the first terminal of the fifteenth power transistor QX2B and the first terminal of the sixteenth power transistor QX1B. The second terminal of the fifteenth power transistor QX2B is grounded. The second terminal of the sixteenth power transistor QX1B is connected to the second node CFLB of the second branch.

[0055] Under steady-state operation, VIN = 4 * VOUT, VC1A = VC1B = VOUT, VC2A = VC2B = 2 * VOUT, VC3A = VC3B = 3 * VOUT. Here, VIN represents the input voltage, VOUT represents the output voltage, VC1A represents the voltage difference across the first capacitor C1A, VC1B represents the voltage difference across the fourth capacitor C1B, VC2A represents the voltage difference across the fifth capacitor C2A, VC2B represents the voltage difference across the second capacitor C2B, VC3A represents the voltage difference across the third capacitor C3A, and VC3B represents the voltage difference across the sixth capacitor C3B.

[0056] Figure 3 This is the timing diagram for a novel two-phase 4:1 Dickson switched-capacitor converter during one switching cycle. There are four operating states sequentially within one cycle: stage0, stage1, stage2, and stage3. Signal PHA is the original clock signal with a 50% duty cycle; signal PHB is the inverted signal of PHA; signal PHA_DLY is the clock signal obtained by delaying signal PHA; and signal PHB_DLY is the clock signal obtained by delaying signal PHB. Signals Q1, Q3, Q5A, Q7A, Q6B, and Q8B represent the switching states of the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B, respectively. Signals Q2, Q4, Q6A, Q8A, Q5B, and Q7B represent the switching states of the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B, respectively. Signals QX1A, QX2A, QX1B, and QX2B represent the switching states of the thirteenth power transistor QX1A, the fourteenth power transistor QX2A, the sixteenth power transistor QX1B, and the fifteenth power transistor QX2B, respectively. Signals CFLA and CFLB represent the voltage waveforms of the first node CFLA in the first branch and the second node CFLB in the second branch, respectively. Signals LXA and LXB represent the voltage waveforms of nodes LXA and LXB, respectively. Signal iL represents the current waveform flowing through inductor L.

[0057] Stage 0 (t0-t1): such as Figure 4As shown, the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B are turned on, while the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B are turned off (i.e., disconnected or not conducting). The first capacitor C1A, the second capacitor C2B, and the third capacitor C3A are all in a charging state, while the fourth capacitor C1B, the fifth capacitor C2A, and the sixth capacitor C3B are all in a discharging state. In the auxiliary circuit section, the sixteenth power transistor QX1B and the fourteenth power transistor QX2A are turned on, while the thirteenth power transistor QX1A and the fifteenth power transistor QX2B are turned off. During this stage, the voltage at the first node CFLA of the first branch is equal to the output voltage VOUT, the voltage at the second node CFLB of the second branch is zero, the voltages at nodes LXA and LXB are zero, and the current flowing through the inductor L is zero.

[0058] Stage 1 (t1-t2): For example Figure 5 As shown, at time t1, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B remain off, while the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B are off. At this time, all 12 main power transistors are in the off state. The first capacitor C1A, the fourth capacitor C1B, the fifth capacitor C2A, the second capacitor C2B, the third capacitor C3A, and the sixth capacitor C3B stop charging or discharging, maintaining the current voltage difference unchanged. The load current is provided by the discharge of the output capacitor COUT. The fourteenth power transistor QX2A and the fifteenth power transistor QX2B are off, while the thirteenth power transistor QX1A and the sixteenth power transistor QX1B are on.

[0059] Before time t1, the voltage of the first node CFLA in the first branch is VOUT, and the voltage of the second node CFLB in the second branch is zero. Starting from time t1, inductor L is connected between the first node CFLA in the first branch and the second node CFLB in the second branch. At this time, the parasitic capacitance of the first node CFLA in the first branch, the parasitic capacitance of the second node CFLB in the second branch, and inductor L begin to resonate. The voltage of the first node CFLA in the first branch decreases resonantly, while the voltage of the second node CFLB in the second branch increases resonantly, and the current in inductor L gradually increases. When the voltage of the first node CFLA in the first branch is the same as the voltage of the second node CFLB in the second branch, the current flowing through inductor L reaches its positive peak. Afterward, the voltage of the first node CFLA in the first branch continues to decrease, the voltage of the second node CFLB in the second branch continues to increase, and the current in inductor L begins to decrease. By time t2, the voltage of the first node CFLA in the first branch resonates to zero, the voltage of the second node CFLB in the second branch resonates to the output voltage VOUT, and the current in inductor L decreases to zero. At this point, stage 2 begins.

[0060] As can be seen, during stage 1, the charge at the first node CFLA of the first branch can be transferred to the second node CFLB of the second branch by utilizing the resonance between the inductor and the parasitic capacitance. This provides the conditions for ZVS turn-on (i.e., conduction) for the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B to be turned on in the next stage.

[0061] Stage 2 (t2-t3): For example Figure 6 As shown, at time t2, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B are turned on (i.e., conducted) with zero voltage. The second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B remain off. The thirteenth power transistor QX1A and the fifteenth power transistor QX2B are turned on, while the fourteenth power transistor QX2A and the sixteenth power transistor QX1B are turned off. The system then enters stage 2. The first capacitor C1A, the second capacitor C2B, and the third capacitor C3A are in a discharging state, while the fourth capacitor C1B, the fifth capacitor C2A, and the sixth capacitor C3B are in a charging state. The voltage at the first node CFLA of the first branch is zero, the voltage at the second node CFLB of the second branch is equal to the output voltage VOUT, the voltages at nodes LXA and LXB are both zero, and the current flowing through inductor L is zero.

[0062] Stage 3 (t3-t4): For example Figure 7As shown, at time t3, the first power transistor Q1, the third power transistor Q3, the fifth power transistor Q5A, the seventh power transistor Q7A, the tenth power transistor Q6B, and the twelfth power transistor Q8B are off, while the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B remain off. At this time, all 12 main power transistors are in the off state. The first capacitor C1A, the second capacitor C2B, the third capacitor C3A, the fourth capacitor C1B, the fifth capacitor C2A, and the sixth capacitor C3B stop charging or discharging, maintaining the current voltage difference unchanged. The load current is provided by the discharge of the output capacitor COUT. The fourteenth power transistor QX2A and the fifteenth power transistor QX2B are off, while the thirteenth power transistor QX1A and the sixteenth power transistor QX1B are on.

[0063] Before time t3, the voltage of the first node CFLA in the first branch is zero, and the voltage of the second node CFLB in the second branch is the output voltage VOUT. Starting at time t3, inductor L is connected between the first node CFLA in the first branch and the second node CFLB in the second branch. At this time, the parasitic capacitance of the first node CFLA in the first branch, the parasitic capacitance of the second node CFLB in the second branch, and inductor L begin to resonate. The voltage of the first node CFLA in the first branch resonates and rises, while the voltage of the second node CFLB in the second branch resonates and falls, and the current in inductor L gradually increases negatively. When the voltage of the first node CFLA in the first branch and the voltage of the second node CFLB in the second branch are the same, the current flowing through inductor L reaches a negative peak. Afterward, the voltage of the first node CFLA in the first branch continues to rise, the voltage of the second node CFLB in the second branch continues to fall, and the current in inductor L begins to decrease negatively. By time t0, the voltage of the first node CFLA in the first branch resonates to the output voltage VOUT, the voltage of the second node CFLB in the second branch resonates to zero, and the current in inductor L drops to zero. At this point, stage 0 begins.

[0064] As can be seen, during stage 3, the charge at the second node CFLB of the second branch can be transferred to the first node CFLA of the first branch by utilizing the resonance between the inductor and the parasitic capacitance. This provides the zero-voltage turn-on condition for the second power transistor Q2, the fourth power transistor Q4, the sixth power transistor Q6A, the eighth power transistor Q8A, the ninth power transistor Q5B, and the eleventh power transistor Q7B to be turned on in the next stage.

[0065] According to the embodiments of this application, the dual-phase Dickson switched-capacitor converter controls the switching of the thirteenth power transistor QX1A, the fourteenth power transistor QX2A, the sixteenth power transistor QX1B, and the fifteenth power transistor QX2B through the above-mentioned control timing. During stage 1, the charge of the first node CFLA of the first branch is transferred to the second node CFLB of the second branch through the inductor L. During stage 3, the charge of the second node CFLB of the second branch is transferred to the first node CFLA of the first branch through the inductor L. This ensures that the voltage difference between the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5A, the ninth power transistor Q5B, the sixth power transistor Q6A, the tenth power transistor Q6B, the seventh power transistor Q7A, the eleventh power transistor Q7B, the eighth power transistor Q8A, and the twelfth power transistor Q8B is zero before each turn-on, which greatly reduces switching losses and improves the conversion efficiency of the switched-capacitor converter.

[0066] exist Figure 2 Based on the novel two-phase 4:1 Dickson switched-capacitor converter shown, a two-phase N:1 Dickson switched-capacitor converter can be realized by adding main power transistors and capacitors, such as... Figure 8 As shown. This two-phase N:1 Dickson switched capacitor converter can be used with and Figure 2 The same auxiliary circuitry and similar control methods are used to achieve zero-voltage turn-on (i.e., conduction) of all main power transistors. Here, N is an integer greater than or equal to 4. When N=4, the two-phase N:1 Dickson switched-capacitor converter becomes a two-phase 4:1 Dickson switched-capacitor converter, such as... Figure 2 As shown.

[0067] When N is an integer greater than or equal to 5, the two-phase Dickson switched-capacitor converter is a two-phase N:1 zero-voltage turn-on switched-capacitor converter, such as... Figure 8 As shown, the two-phase N:1 Dickson switched-capacitor converter includes an auxiliary circuit, a first branch, and a second branch. The first branch includes a first power transistor Q1, a second power transistor Q2, N first sub-power transistors, and N-1 first sub-capacitors. The second branch includes a third power transistor Q3, a fourth power transistor Q4, N second sub-power transistors, and N-1 second sub-capacitors. All power transistors and N sub-power transistors in both the first and second branches are main power transistors, and all main power transistors have parasitic capacitance.

[0068] The two ends of the auxiliary circuit are respectively connected to the first node CFLA of the first branch between the first power transistor Q1 and the second power transistor Q2, and the second node CFLB of the second branch between the third power transistor Q3 and the fourth power transistor Q4. Figure 8The connection structure of the auxiliary circuit of the two-phase N:1 Dickson switched capacitor converter and Figure 2 The connection structure of the auxiliary circuit is the same as that of the dual-phase 4:1 Dickson switched capacitor converter.

[0069] The input terminal of the dual-phase N:1 Dickson switched capacitor converter is connected to an external input voltage, and is connected to the output terminal of the dual-phase N:1 Dickson switched capacitor converter in sequence through N first sub-power transistors and N second sub-power transistors. The N first sub-power transistors are connected in sequence, and the N second sub-power transistors are connected in sequence.

[0070] Each pair of adjacent first sub-power transistors forms a first sub-power transistor pair, and two adjacent first sub-power transistor pairs include the same first sub-power transistor. All first sub-power transistor pairs are connected sequentially. Each pair of adjacent second sub-power transistors forms a second sub-power transistor pair, and two adjacent second sub-power transistor pairs include the same second sub-power transistor. All second sub-power transistor pairs are connected sequentially.

[0071] Any two adjacent first sub-power transistor pairs are used to connect a first sub-capacitor and a second sub-capacitor, respectively. For example, any two adjacent first sub-power transistor pairs include a first pair of first sub-power transistor pairs and a second pair of first sub-power transistor pairs. The first end of a first sub-capacitor is connected between the two first sub-power transistors of the first pair of first sub-power transistor pairs, and the first end of a second sub-capacitor is connected between the two first sub-power transistors of the second pair of first sub-power transistor pairs.

[0072] Any two adjacent pairs of second sub-power transistors are used to connect another first sub-capacitor and another second sub-capacitor, respectively. For example, any two adjacent pairs of second sub-power transistors include a first pair of second sub-power transistors and a second pair of second sub-power transistors. The first end of the other second sub-capacitor is connected between the two second sub-power transistors of the first pair of second sub-power transistors, and the first end of the other first sub-capacitor is connected between the two second sub-power transistors of the second pair of second sub-power transistors.

[0073] The first sub-power transistor pair and the second sub-power transistor pair connected adjacent to the output terminal of the switched capacitor converter are respectively the first stage first sub-power transistor pair and the first stage second sub-power transistor pair. A first sub-capacitor is connected between the two first sub-power transistors of the first stage first sub-power transistor pair, and a second sub-capacitor is connected between the two second sub-power transistors of the first stage second sub-power transistor pair.

[0074] The second terminal of all first sub-capacitors is connected to the first node CFLA, and the second terminal of all second sub-capacitors is connected to the second node CFLB.

[0075] For example, such as Figure 8As shown, the N first sub-power transistors include the first first sub-power transistor, the second first sub-power transistor, ..., the (N-1)th first sub-power transistor Q(N+3)A and the Nth first sub-power transistor Q(N+4)A connected in sequence. The first first sub-power transistor is the fifth power transistor Q5A, the second first sub-power transistor is the sixth power transistor Q6A, and the fifth power transistor Q5A and the sixth power transistor Q6A form the first-stage first sub-power transistor pair. The sixth power transistor Q6A and its adjacent first sub-power transistor (... Figure 8 (Not shown) forms the second stage first sub-power transistor pair, ..., the (N-1)th first sub-power transistor Q(N+3)A and the Nth first sub-power transistor Q(N+4)A form the (N-1)th stage first sub-power transistor pair. The N-1 first sub-capacitors include the first first sub-capacitor, the second first sub-capacitor, ..., the (N-2)th first sub-capacitor and the (N-1)th first sub-capacitor, where the first first sub-capacitor is the first capacitor C1A, the second first sub-capacitor is the second capacitor C2B, when N is even, the (N-2)th first sub-capacitor is the first sub-capacitor C(N-2)B, and the (N-1)th first sub-capacitor is the first sub-capacitor C(N-1)A; when N is odd, the (N-2)th first sub-capacitor is the first sub-capacitor C(N-2)A, and the (N-1)th first sub-capacitor is the first sub-capacitor C(N-1)B.

[0076] The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter in sequence through the Nth first sub-power transistor Q(N+4)A, the N-1th first sub-power transistor Q(N+3)A, ..., the second first sub-power transistor and the first first sub-power transistor.

[0077] The N second sub-power transistors include a first second sub-power transistor, a second second sub-power transistor, ..., the (N-1)th second sub-power transistor Q(N+3)B and the Nth second sub-power transistor Q(N+4)B connected in sequence. The first second sub-power transistor is the ninth power transistor Q5B, the second second sub-power transistor is the tenth power transistor Q6B, and the ninth power transistor Q5B and the tenth power transistor Q6B form a first-stage second sub-power transistor pair. The ninth power transistor Q6B and the second sub-power transistor (... Figure 8(Not shown) forms the second-stage second sub-power transistor pair, ..., the (N-1)th second sub-power transistor Q(N+3)B and the Nth second sub-power transistor Q(N+4)B form the (N-1)th stage second sub-power transistor pair. The N-1 second sub-capacitors include the first second sub-capacitor, the second second sub-capacitor, ..., the (N-2)th second sub-capacitor and the (N-1)th second sub-capacitor, where the first second sub-capacitor is the fourth capacitor C1B, the second second sub-capacitor is the fifth capacitor C2A, when N is even, the (N-2)th second sub-capacitor is the second sub-capacitor C(N-2)A, and the (N-1)th second sub-capacitor is the second sub-capacitor C(N-1)B; when N is odd, the (N-2)th second sub-capacitor is the second sub-capacitor C(N-2)B, and the (N-1)th second sub-capacitor is the second sub-capacitor C(N-1)A.

[0078] The input terminal of the switched capacitor converter is connected to the output terminal of the switched capacitor converter in sequence through the Nth second sub-power transistor Q(N+4)B, the N-1th second sub-power transistor Q(N+3)B, ..., the second second sub-power transistor and the first second sub-power transistor.

[0079] The connection point of the second terminal of the second power transistor Q2, the second terminals of all the first sub-capacitors, and the first terminal of the first power transistor Q1 is the first node CFLA. The connection point of the second terminal of the third power transistor Q3, the second terminals of all the second sub-capacitors, and the first terminal of the fourth power transistor Q4 is the second node CFLB.

[0080] The first terminal of the first capacitor C1A is connected between the fifth power transistor Q5A and the sixth power transistor Q6A of the first sub-power transistor pair in the first stage, and the first terminal of the second capacitor C2B is connected between the tenth power transistor Q6B of the second sub-power transistor pair in the second stage and the adjacent first sub-power transistor. Figure 8 (Not shown) When N is even, the first terminal of the (N-1)th first sub-capacitor is connected between the (N-1)th first sub-power transistor Q(N+3)A and the Nth first sub-power transistor Q(N+4)A of the first sub-power transistor pair of the (N-1)th stage. When N is odd, the first terminal of the (N-1)th first sub-capacitor is connected between the (N-1)th second sub-power transistor Q(N+3)B and the Nth second sub-power transistor Q(N+4)B of the second sub-power transistor pair of the (N-1)th stage.

[0081] The first terminal of the fourth capacitor C1B is connected between the ninth power transistor Q5B and the tenth power transistor Q6B of the second sub-power transistor pair in the first stage, and the first terminal of the fifth capacitor C2A is connected between the sixth power transistor Q6A and the first sub-power transistor of the first sub-power transistor pair in the second stage. Figure 8(Not shown) When N is even, the first terminal of the (N-1)th second sub-capacitor is connected between the (N-1)th second sub-power transistor Q(N+3)B and the Nth second sub-power transistor Q(N+4)B of the second sub-power transistor pair of the (N-1)th stage. When N is odd, the first terminal of the (N-1)th second sub-capacitor is connected between the (N-1)th first sub-power transistor Q(N+3)A and the Nth first sub-power transistor Q(N+4)A of the first sub-power transistor pair of the (N-1)th stage.

[0082] In this article, both the power transistor and the sub-power transistor are switching transistors, which can be either N-type or P-type switching transistors.

[0083] In all embodiments of this application, the power transistors and sub-power transistors on the first branch and the second branch are all main power transistors, all main power transistors have parasitic capacitance, and the main power transistors can be either switching transistors or diodes.

[0084] Figure 2 The auxiliary circuit shown includes four NMOS transistors and an inductor. It enables the transfer of charge from one branch to another during the dead time when all main power transistors are off, achieving zero-voltage turn-on for all main power transistors and reducing switching losses. Besides... Figure 2 Besides the auxiliary circuit in the diagram, various other types of circuits can also achieve this function. Figure 2 The function of auxiliary circuits in [the system]. For example... Figure 9 As shown, there are several different auxiliary circuits.

[0085] like Figure 9 As shown, the auxiliary circuit may include a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor, and an inductor. The first terminal of the thirteenth power transistor is connected to the first node CFLA of the first branch, and the second terminal of the thirteenth power transistor is connected to the first terminal of the fourteenth power transistor and the first terminal of the inductor, respectively. The second terminal of the fourteenth power transistor is grounded. The second terminal of the inductor is connected to the first terminals of the fifteenth and sixteenth power transistors, respectively. The second terminal of the fifteenth power transistor is grounded, and the second terminal of the sixteenth power transistor is connected to the second node CFLB of the second branch. The thirteenth, fourteenth, fifteenth, and sixteenth power transistors can all be N-type, such as... Figure 9 As shown in auxiliary circuit A, alternatively, the thirteenth and sixteenth power transistors can both be P-type power transistors, and the fourteenth and fifteenth power transistors can both be N-type power transistors, as shown in the diagram. Figure 9 The auxiliary circuit D is shown in the figure.

[0086] Optionally, such as Figure 9As shown, the auxiliary circuit may include a thirteenth power transistor, a sixteenth power transistor, a first diode, a second diode, and an inductor. The first terminal of the thirteenth power transistor is connected to the first node CFLA of the first branch. The second terminal of the thirteenth power transistor is connected to the first terminal of both the first diode and the inductor. The second terminal of the first diode is grounded, with the first terminal being the negative terminal and the second terminal being the positive terminal. The second terminal of the inductor is connected to the first terminal of both the second diode and the sixteenth power transistor. The second terminal of the second diode is grounded. The second terminal of the sixteenth power transistor is connected to the second node CFLB of the second branch. The first terminal of the second diode is the negative terminal and the second terminal being the positive terminal. The thirteenth and sixteenth power transistors can both be N-type power transistors, such as... Figure 9 As shown in auxiliary circuit B, or, the thirteenth and sixteenth power transistors can both be P-type power transistors, such as... Figure 9 The auxiliary circuit E is shown in the figure.

[0087] Optionally, the auxiliary circuit may include a thirteenth power transistor, a sixteenth power transistor, and an inductor; wherein, the first terminal of the thirteenth power transistor is connected to the first node CFLA of the first branch, the second terminal of the thirteenth power transistor is connected to the first terminal of the inductor, the second terminal of the inductor is connected to the first terminal of the sixteenth power transistor, and the second terminal of the sixteenth power transistor is connected to the second node CFLB of the second branch. The thirteenth and sixteenth power transistors can both be N-type power transistors, such as... Figure 9 As shown in the auxiliary circuit C, or, the thirteenth and sixteenth power transistors can both be P-type power transistors, such as... Figure 9 The auxiliary circuit F is shown in the figure.

[0088] This demonstrates that the specific implementation circuits are diverse. Therefore, after understanding the content of this application, those skilled in the art can easily conceive of various modifications, variations, or equivalents of the above examples, but they should still be subject to the limitations set forth in the claims and any equivalents.

Claims

1. A two-phase Dickson switched capacitor converter, comprising a first branch, a second branch, and an auxiliary circuit, wherein the auxiliary circuit is connected between the first branch and the second branch, wherein the power transistors of the first branch and the second branch are main power transistors, and the auxiliary circuit is used to transfer the charge of one branch of the first branch and the second branch to the other branch during the dead time when all the main power transistors are off, so that the voltage difference across each of the main power transistors becomes zero, thereby enabling each of the main power transistors to turn on at zero voltage; wherein The dual-phase Dickson switched-capacitor converter is a dual-phase Dickson 4:1 switched-capacitor converter. The first branch includes a first power transistor, a second power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a first capacitor, a second capacitor, and a third capacitor; the second branch includes a fourth power transistor, a third power transistor, a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The first terminal of the eighth power transistor and the first terminal of the twelfth power transistor are connected to the input terminal of the two-phase Dickson switched capacitor converter. The input terminal is connected to an external input voltage. The second terminal of the eighth power transistor is connected to the first terminal of the seventh power transistor and the first terminal of the third capacitor, respectively. The second terminal of the twelfth power transistor is connected to the first terminal of the eleventh power transistor and the first terminal of the sixth capacitor, respectively. The second terminal of the seventh power transistor is connected to the first terminal of the sixth power transistor and the first terminal of the fifth capacitor, respectively; the second terminal of the eleventh power transistor is connected to the first terminal of the tenth power transistor and the first terminal of the second capacitor, respectively. The second end of the sixth power transistor is connected to the first end of the fifth power transistor and the first end of the first capacitor, respectively; the second end of the tenth power transistor is connected to the first end of the ninth power transistor and the first end of the fourth capacitor, respectively. The second end of the fifth power transistor is connected to the first end of the second power transistor, and the second end of the ninth power transistor is connected to the first end of the third power transistor; The second terminal of the second power transistor is connected to the first terminal of the first power transistor, the second terminal of the first capacitor, the second terminal of the second capacitor, and the second terminal of the third capacitor, respectively; the second terminal of the third power transistor is connected to the first terminal of the fourth power transistor, the second terminal of the fourth capacitor, the second terminal of the fifth capacitor, and the second terminal of the sixth capacitor, respectively; the second terminals of the first power transistor and the second terminals of the fourth power transistor are grounded. The connection point of the second terminal of the fifth power transistor, the first terminal of the second power transistor, the first terminal of the third power transistor, and the second terminal of the ninth power transistor is the output terminal of the two-phase Dickson switched capacitor converter. The connection point of the first end of the first power transistor, the second end of the second power transistor, the second end of the first capacitor, the second end of the second capacitor, and the second end of the third capacitor is the first node of the first branch. The connection point of the second end of the third power transistor, the first end of the fourth power transistor, the second end of the fourth capacitor, the second end of the fifth capacitor, and the second end of the sixth capacitor is the second node of the second branch.

2. The dual-phase Dickson switched-capacitor converter of claim 1, wherein, The auxiliary circuit includes a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor, and an inductor; the first end of the thirteenth power transistor is connected to the first node, the second end of the thirteenth power transistor is connected to the first end of the fourteenth power transistor and the first end of the inductor, and the second end of the fourteenth power transistor is grounded; the second end of the inductor is connected to the first end of the fifteenth power transistor and the first end of the sixteenth power transistor, the second end of the fifteenth power transistor is grounded, and the second end of the sixteenth power transistor is connected to the second node.

3. The dual-phase Dickson switched-capacitor converter of claim 2, wherein, The timing sequence of the dual-phase Dickson switched-capacitor converter includes four stages: First stage: The second, fourth, sixth, eighth, ninth, eleventh, fourteenth, and sixteenth power transistors are turned on, and the other power transistors are turned off; the first, second, and third capacitors are in a charging state, and the fourth, fifth, and sixth capacitors are in a discharging state, with the inductor current being 0; Second stage: The thirteenth power transistor and the sixteenth power transistor are turned on, and the other power transistors are turned off; The inductor current first rises and then falls, and the second stage ends when the inductor current drops to 0. Third stage: The first power transistor, the third power transistor, the fifth power transistor, the seventh power transistor, the tenth power transistor, the twelfth power transistor, the thirteenth power transistor, and the fifteenth power transistor are turned on, and the other power transistors are turned off; the first capacitor, the second capacitor, and the third capacitor are in a discharging state, the fourth capacitor, the fifth capacitor, and the sixth capacitor are in a charging state, and the inductor current is 0; Fourth stage: The thirteenth and sixteenth power transistors are turned on, and the other power transistors are turned off; The inductor current first rises and then falls. When the inductor current drops to 0, the fourth stage ends and returns to the first stage.

4. The dual-phase Dickson switched-capacitor converter of claim 1, wherein, The dual-phase Dickson switched-capacitor converter is a dual-phase N:1 Dickson switched-capacitor converter, where N is an integer greater than or equal to 5; The first branch includes a first power transistor, a second power transistor, N first sub-power transistors and N-1 first sub-capacitors; the second branch includes a third power transistor, a fourth power transistor, N second sub-power transistors and N-1 second sub-capacitors. The two ends of the auxiliary circuit are respectively connected to a first node between the first power transistor and the second power transistor, and a second node between the third power transistor and the fourth power transistor. The input terminal of the dual-phase Dickson switched capacitor converter is connected to the output terminal of the dual-phase N:1 Dickson switched capacitor converter through the N first sub-power transistors and the N second sub-power transistors in sequence. The N first sub-power transistors are connected in sequence, and the N second sub-power transistors are connected in sequence. Two adjacent first sub-power transistors form a first sub-power transistor pair, and two adjacent first sub-power transistor pairs include the same first sub-power transistor; two adjacent second sub-power transistors form a second power transistor pair, and two adjacent second sub-power transistor pairs include the same second power transistor. Any two adjacent first sub-power transistor pairs include a first pair of first sub-power transistor pairs and a second pair of first sub-power transistor pairs. The first end of a first sub-capacitor is connected between the two first sub-power transistors of the first pair of first sub-power transistor pairs, and the first end of a second sub-capacitor is connected between the two first sub-power transistors of the second pair of first sub-power transistor pairs. Any two adjacent pairs of second sub-power transistors include a first pair of second sub-power transistors and a second pair of second sub-power transistors. The first end of another first sub-capacitor is connected between the two second sub-power transistors of the first pair of second sub-power transistors, and the first end of another second sub-capacitor is connected between the two second sub-power transistors of the second pair of second sub-power transistors. A first sub-capacitor is connected between the two first sub-power transistors of a first sub-power transistor pair connected to the output terminal, and a second sub-capacitor is connected between the two second sub-power transistors of a second sub-power transistor pair connected to the output terminal. The second end of all the first sub-capacitors is connected to the first node, and the second end of all the second sub-capacitors is connected to the second node.

5. The dual-phase Dickson switched-capacitor converter of claim 4, wherein, The auxiliary circuit includes a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor, and an inductor; the first end of the thirteenth power transistor is connected to the first node, the second end of the thirteenth power transistor is connected to the first end of the fourteenth power transistor and the first end of the inductor, and the second end of the fourteenth power transistor is grounded; the second end of the inductor is connected to the first end of the fifteenth power transistor and the first end of the sixteenth power transistor, the second end of the fifteenth power transistor is grounded, and the second end of the sixteenth power transistor is connected to the second node.

6. The dual-phase Dickson switched-capacitor converter of claim 1 or 4, wherein, The auxiliary circuit includes a thirteenth power transistor, a sixteenth power transistor, a first diode, a second diode, and an inductor; the first end of the thirteenth power transistor is connected to the first node, the second end of the thirteenth power transistor is connected to the first end of the first diode and the first end of the inductor, and the second end of the first diode is grounded; the second end of the inductor is connected to the first end of the second diode and the first end of the sixteenth power transistor, the second end of the second diode is grounded, and the second end of the sixteenth power transistor is connected to the second node.

7. The dual-phase Dickson switched-capacitor converter of claim 1 or 4, wherein, The auxiliary circuit includes a thirteenth power transistor, a sixteenth power transistor, and an inductor; wherein, the first end of the thirteenth power transistor is connected to the first node, the second end of the thirteenth power transistor is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the sixteenth power transistor, and the second end of the sixteenth power transistor is connected to the second node.

8. The dual-phase Dickson switched-capacitor converter of claim 2 or 5, wherein, The thirteenth, sixteenth, fifteenth, and sixteenth power transistors are all N-type power transistors; or, the thirteenth and sixteenth power transistors are both P-type power transistors, and the sixteenth and fifteenth power transistors are both N-type power transistors.

9. The dual-phase Dickson switched-capacitor converter of claim 6, wherein, Both the thirteenth and sixteenth power transistors are N-type or P-type power transistors.

10. The dual-phase Dickson switched-capacitor converter of claim 7, wherein, Both the thirteenth and sixteenth power transistors are P-type or N-type power transistors.

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