Dynamic Comparator and Circuit System Using the Same

Abstract

The present invention provides a dynamic comparator and a circuit system using the same, which includes a differential stage, a switching unit, and a switched charge storage unit. The switched charge storage unit includes a plurality of switching transistors and a charge storage capacitor electrically connected to the plurality of switching transistors. When the dynamic comparator switches from a comparison state to a reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage, so as to achieve charge recycling. Thus, the present invention can enable the dynamic comparator to have lower power consumption and lower charging and discharging currents.

Description

Technical Field

[0001] The present invention relates to a dynamic comparator, and more particularly to a dynamic comparator capable of charge-recycling a charge storage capacitor and a circuit system using the same. Background Art

[0002] Different from general comparators, a dynamic comparator is controlled by a clock signal and an inverted clock signal, and can be operated in a reset state and a comparison state at different times. The dynamic comparator has the advantages of high-speed operation and low power consumption, and can be applied to analog-to-digital converters or other circuits, especially various biomedical electronic devices and successive-approximation register ADCs (SAR ADCs).

[0003] Please refer to Figure 1 , Figure 1 which is a circuit diagram of a conventional dynamic comparator. The conventional dynamic comparator includes a plurality of transistors M1 to M4, MT, MB, a plurality of capacitors CP, and a charge storage capacitor CTAIL, and may further include a latch unit (not shown in Figure 1 ). The latch unit is electrically connected to nodes FN and FP to output the comparison result and the inverted comparison result of the conventional dynamic comparator thereby. Transistors M1 and M2 serve as a differential amplifier stage, and the gates of transistors M1 and M2 receive a first input signal VIP and a second input signal VIN respectively, wherein the difference between the first input signal VIP and the second input signal VIN determines the voltage values of nodes FN and FP.

[0004] In the reset state, the inverted clock signal CLK_B is at a logic high level and the clock signal CLK is at a logic low level, so transistor MT is turned off, and transistors M3, M4, and MB are turned on. Therefore, the inverted clock signal CLK_B charges the charge storage capacitor CTAIL, causing the voltage of node CBOM to rise to the system voltage DVDD, while the voltage of node CTOP is the ground voltage, that is, the voltage difference between the second end and the first end of the charge storage capacitor CTAIL (i.e., nodes CBOM and CTOP) is the system voltage DVDD.

[0005] Next, in the comparison state, the frequency signal CLK is at a logic high level and the inverted frequency signal CLK_B is at a logic low level. Therefore, the transistor MT is turned on, and the transistors M3, M4, and MB are turned off. The inverted frequency signal CLK_B is at a logic low level. At the instant when the charge is not redistributed, the voltage difference across the charge storage capacitor CTAIL must be maintained at the system voltage DVDD. Thus, in the comparison state, the voltage of the node CBOM is the ground voltage, and the voltage of the node CTOP is the negative system voltage DVDD (i.e., -DVDD). Due to the fact that the transistor MT is turned on, the voltage of the node VS is substantially equal to the voltage of the node CTOP. The charge of one of the capacitors CP flows to the node VS, causing the voltages of the node VS and the node CTOP to be charged from -DVDD to DVDD / 2. Therefore, the voltage difference between the first end and the second end of the charge storage capacitor CTAIL (i.e., the nodes CTOP and CBOM) is half of the system voltage DVDD (i.e., DVDD / 2).

[0006] Although the charge storage capacitor CTAIL can be pre-charged to the system voltage DVDD in the reset state. However, when the charge storage capacitor CTAIL switches from the comparison state to the reset state, the voltage of the first end of the charge storage capacitor CTAIL (i.e., the node CTOP) is pulled down from DVDD / 2 to the ground voltage. Therefore, the charge stored in the charge storage capacitor CTAIL (CTAIL*DVDD / 2) is wasted and not recycled, which results in power waste and a large charging and discharging current. Summary of the Invention

[0007] According to the object of the present invention, an embodiment of the present invention provides a dynamic comparator, which has a first node, a second node and a third node inside, and the dynamic comparator includes: a differential stage, configured to receive a first input signal and a second input signal, and respectively output a comparison result and an inverted comparison result of the first input signal and the second input signal to the second node and the first node when the dynamic comparator is in a comparison state; a switching unit, electrically connected to the differential stage through the first node and the second node, and supplying a system voltage to the first node and the second node in a reset state; and a switched charge storage unit, electrically connected to the differential stage through the third node, including a plurality of switching transistors and a charge storage capacitor electrically connected to the plurality of switching transistors, wherein when the dynamic comparator is in the comparison state, the switched charge storage unit connects the third node to a low voltage through the charge storage capacitor, when the dynamic comparator is in the reset state, the third node is disconnected from the switched charge storage unit and not electrically connected, and when the dynamic comparator switches from the comparison state to the reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage.

[0008] According to the above technical features, the dynamic comparator further includes: a control unit, electrically connected to the switched charge storage unit, configured to receive a first frequency signal, a first inverted frequency signal, a second frequency signal and a second inverted frequency signal, and generate a plurality of control signals accordingly to control the dynamic comparator to operate in the reset state or the comparison state, wherein the period of the second frequency signal is twice the period of the first frequency signal, the first inverted frequency signal is the inverted first frequency signal, and the second inverted frequency signal is the inverted second frequency signal; wherein the switched charge storage unit is configured to receive the system voltage, a plurality of switching signals, the second frequency signal and the second inverted frequency signal, and the plurality of switching transistors are controlled by the plurality of switching signals, the second frequency signal and the second inverted frequency signal, so that when the dynamic comparator switches from the comparison state to the reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage.

[0009] According to the above technical features, the reset state includes a first reset state and a second reset state, and the comparison state includes a first comparison state and a second comparison state; when the dynamic comparator switches from the first comparison state to the second reset state, the voltage at the second terminal of the charge storage capacitor rises from half of the system voltage to the system voltage, and the voltage at the first terminal of the charge storage capacitor maintains the low voltage; when the dynamic comparator switches from the second comparison state to the first reset state, the voltage at the first terminal of the charge storage capacitor rises from half of the system voltage to the system voltage, and the voltage at the second terminal of the charge storage capacitor maintains the low voltage.

[0010] According to the above technical features, the plurality of switch signals include a first switch signal, a second switch signal, a third switch signal, and a fourth switch signal, and the plurality of switches include a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, and a sixth switch transistor, wherein the six gates of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, and the sixth switch transistor respectively receive the first switch signal, the second switch signal, the second inverted frequency signal, the second frequency signal, the third switch signal, and the fourth switch signal. The two drains of the first switch transistor and the second switch transistor are electrically connected to the third node, the two sources of the first switch transistor and the second switch transistor are respectively electrically connected to the first terminal and the second terminal of the charge storage capacitor, the two drains of the fourth switch transistor and the third switch transistor are respectively electrically connected to the first terminal and the second terminal of the charge storage capacitor, the two sources of the fourth switch transistor and the third switch transistor are electrically connected to the low voltage, the two sources of the fifth switch transistor and the sixth switch transistor receive the system voltage, and the two drains of the fifth switch transistor and the sixth switch transistor are respectively electrically connected to the first terminal and the second terminal of the charge storage capacitor.

[0011] According to the above technical features, in the first reset state, the third switching transistor and the fifth switching transistor are turned on, and the first switching transistor, the second switching transistor, the fourth switching transistor, and the sixth switching transistor are turned off; in the first comparison state, the second switching transistor and the fourth switching transistor are turned on, and the first switching transistor, the third switching transistor, the fifth switching transistor, and the sixth switching transistor are turned off; in the second reset state, the fourth switching transistor and the sixth switching transistor are turned on, and the first switching transistor, the second switching transistor, the third switching transistor, and the fifth switching transistor are turned off; in the second comparison state, the first switching transistor and the third switching transistor are turned on, and the second switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are turned off.

[0012] According to the above technical features, the control unit includes a first AND logic gate, a second AND logic gate, a first NAND logic gate, and a second NAND logic gate. The first AND logic gate receives the first frequency signal and the second frequency signal to generate the second switching signal. The second AND logic gate receives the first frequency signal and the second inverted frequency signal to generate the first switching signal. The first NAND logic gate receives the first inverted frequency signal and the second frequency signal to generate the fourth switching signal. And the second NAND logic gate receives the first inverted frequency signal and the second inverted frequency signal to generate the third switching signal.

[0013] According to the above technical features, the differential stage includes a first transistor and a second transistor. Two gates of the first transistor and the second transistor respectively receive the first input signal and the second input signal. Two sources of the first transistor and the second transistor are electrically connected to the third node. And two drains of the first transistor and the second transistor are respectively electrically connected to the second node and the first node.

[0014] According to the above technical features, the switching unit includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor. Two ends of the first capacitor are respectively electrically connected to the second node and the low voltage. Two ends of the second capacitor are respectively electrically connected to the first node and the low voltage. Two gates of the third transistor and the fourth transistor receive the first frequency signal. Two sources of the third transistor and the fourth transistor electrically receive the system voltage. And two drains of the third transistor and the fourth transistor are respectively electrically connected to the second node and the first node.

[0015] According to the object of the present invention, an embodiment of the present invention provides a dynamic comparator, which has a first node, a second node and a third node inside, and the dynamic comparator includes: a differential stage for receiving a first input signal and a second input signal, and outputting the comparison result and the inverted comparison result of the first input signal and the second input signal to the second node and the first node respectively in a first comparison state and a second comparison state; a switching unit electrically connected to the differential stage through the first node and the second node, for receiving a system voltage, and providing the system voltage to the first node and the second node in a first reset state and a second reset state; a control unit for controlling the dynamic comparator to operate in one of the first reset state, the second reset state, the first comparison state and the second comparison state; and a switched charge storage unit electrically connected to the differential stage through the third node and electrically connected to the control unit, including a charge storage capacitor, wherein when the dynamic comparator switches from the first comparison state to the second reset state, the voltage at the second end of the charge storage capacitor rises from half of the system voltage to the system voltage; when the dynamic comparator switches from the second comparison state to the first reset state, the voltage at the first end of the charge storage capacitor rises from half of the system voltage to the system voltage.

[0016] According to the object of the present invention, an embodiment of the present invention further provides a circuit system, which includes a plurality of circuits, wherein the plurality of circuits include one of the aforementioned dynamic comparators, and the dynamic comparator is electrically connected to at least one of the other circuits of the plurality of circuits.

[0017] In summary, an embodiment of the present invention provides a dynamic comparator and a circuit system using the dynamic comparator, and the dynamic comparator can recycle the charge of the charge storage capacitor when switching from the reset state to the comparison state.

[0018] In order to further understand the technology, means and effects of the present invention, the following detailed description and drawings can be referred to, so as to thoroughly and specifically understand the object, features and concepts of the present invention. However, the following detailed description and drawings are only used for reference and illustration of the implementation manner of the present invention, and are not used to limit the present invention. Description of the Drawings

[0019] Through the following detailed description of the embodiments in conjunction with the drawings, the present invention can be more comprehensively understood, wherein:

[0020] Figure 1 is the circuit diagram of a conventional dynamic comparator;

[0021] Figure 2 is the functional block diagram of the dynamic comparator according to the embodiment of the present invention;

[0022] Figure 3 A circuit diagram that is part of the dynamic comparator according to an embodiment of the present invention;

[0023] Figures 4A to 4D A schematic diagram showing the charging and discharging of the charge storage capacitor by the dynamic comparator according to an embodiment of the present invention in different operating states;

[0024] Figure 5 A signal waveform diagram of the dynamic comparator according to an embodiment of the present invention;

[0025] Figure 6 A functional block diagram of the circuit system according to an embodiment of the present invention.

[0026] Reference numerals in the drawings:

[0027] 2, 61: Dynamic comparator;

[0028] 21: Switching unit;

[0029] 22: Differential stage;

[0030] 23: Switching charge storage unit;

[0031] 24: Control unit;

[0032] 25: Latch unit;

[0033] 6: Circuit system;

[0034] 62: Analog-to-digital converter;

[0035] 63: Successive approximation register;

[0036] 64: Sample / hold circuit;

[0037] DVDD: System voltage;

[0038] CLK, CLK_D2: Frequency signals;

[0039] CLK_B, CLK_D2B: Inverted frequency signals;

[0040] M1 to M4, MT, MB: Transistors;

[0041] CTOP, CBOM, VS, FP, FN: Nodes;

[0042] SW1 to SW6: Switching transistors;

[0043] CP: Capacitor;

[0044] CTAIL: Charge storage capacitor;

[0045] VIN, VIN’, VIP: Input signals;

[0046] OUTN, OUTP: Output terminals;

[0047] P_1, P_2, PX, PY: Switching signals;

[0048] VCTA: First terminal;

[0049] VCTB: Second terminal;

[0050] AND1, AND2: Logic sum gates;

[0051] NAND1, NAND2: Logic negative sum gates;

[0052] D0 to DN-1: Bits;

[0053] VREF: Reference voltage;

[0054] EOC: End-of-conversion signal. Detailed implementation

[0055] Now, a detailed reference will be made to exemplary embodiments of the present invention, which will be illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts. Additionally, the practices of the exemplary embodiments are merely one of the implementation manners of the design concept of the present invention, and the following exemplary embodiments are not intended to limit the present invention.

[0056] An embodiment of the present invention provides a dynamic comparator, which can mainly recover the charge of the charge storage capacitor to avoid charge loss when the dynamic comparator switches from the comparison state to the reset state, resulting in excessive power consumption and an increase in charging and discharging currents. Additionally, an embodiment of the present invention further provides a circuit system using the dynamic comparator. The circuit system includes multiple circuits, where one circuit is the aforementioned dynamic comparator, and this dynamic comparator is also electrically connected to at least one of the other circuits. Further, the circuit system can be various biomedical electronic devices and successive approximation analog-to-digital converters, but the present invention is not limited by the type of the circuit system (i.e., the application of the dynamic comparator).

[0057] First, please refer to Figure 2 and Figure 3 , Figure 2 which is a functional block diagram of the dynamic comparator according to an embodiment of the present invention, and Figure 3A circuit diagram that is part of the dynamic comparator according to an embodiment of the present invention. Inside the dynamic comparator 2, there are nodes FN, FP, and node VS, and it includes a switching unit 21, a differential stage 22, a switched charge storage unit 23, a control unit 24, and a latch unit 25. The switching unit 21 is electrically connected to the differential stage 22 and the latch unit 25 through nodes FP and FN. The switched charge storage unit 23 is electrically connected to the differential stage 22 through node VS, and the control unit 24 is electrically connected to the switched charge storage unit 23. The dynamic comparator 2 can operate in a first comparison state, a second comparison state, a first reset state, and a second reset state.

[0058] The switching unit 21 is used to receive the system voltage DVDD and the frequency signal CLK. In the first reset state and the second reset state (the frequency signal CLK is at a logic low level), the switching unit 21 supplies the system voltage DVDD to nodes FP and FN. The differential stage 22 is used to receive the input signals VIP and VIN. In the first comparison state and the second comparison state (the frequency signal CLK is at a logic high level), the differential stage 22 respectively outputs the comparison result and the inverted comparison result of the input signals VIP and VIN to nodes FP and FN.

[0059] The switched charge storage unit 23 is used to receive the switch signals P_1, P_2, PX, PY, the frequency signal CLK_D2, the inverted frequency signal CLK_D2B, and the system voltage DVDD, and includes a plurality of switching transistors SW1 to SW6 and a charge storage capacitor CTAIL electrically connected to the plurality of switching transistors SW1 to SW6. The switching transistors SW1 to SW6 are controlled by the switch signals P_1, P_2, PX, PY, the frequency signal CLK_D2, and the inverted frequency signal CLK_D2B. When the dynamic comparator 2 switches from the first comparison state to the second reset state, the voltage of the second end VCTB of the charge storage capacitor CTAIL rises from DVDD / 2 to DVDD, and the voltage of the first end VCTA of the charge storage capacitor CTAIL remains at a low voltage (for example, the ground voltage, but not limited thereto). When the dynamic comparator 2 switches from the second comparison state to the first reset state, the voltage of the first end VCTA of the charge storage capacitor CTAIL rises from DVDD / 2 to DVDD, and the voltage of the second end VCTB of the charge storage capacitor CTAIL remains at a low voltage (for example, the ground voltage, but not limited thereto).

[0060] The control unit 24 is configured to receive the frequency signals CLK, CLK_D2 and the inverted frequency signals CLK_B, CLK_D2B, and accordingly generate the switching signals P_1, P_2, PX, PY to control the dynamic comparator 2 to operate in the first reset state, the second reset state, the first comparison state, or the second comparison state. The period of the frequency signal CLK_D2 is twice that of the frequency signal CLK, the inverted frequency signal CLK_B is the inverted frequency signal CLK, and the inverted frequency signal CLK_D2B is the inverted frequency signal CLK_D2. It should be noted here that in some embodiments, the control unit 24 may be an unnecessary component, and instead, the switched charge storage unit 23 can switch between the first reset state, the second reset state, the first comparison state, and the second comparison state by itself. Incidentally, although the inverted frequency signals CLK_D2B, CLK_B and the frequency signal CLK_D2 are input from the outside of the control unit 24 in this embodiment, in other implementations, they may also be generated by the control unit 24 according to the frequency signal CLK.

[0061] The latch unit 25 receives the system voltage DVDD and the inverted frequency signal CLK_B, thereby latching the inverted comparison result and the comparison result of the nodes FN, FP, and outputting the inverted comparison result and the comparison result to the output terminals OUTN and OUTP respectively in the first comparison state and the second comparison state. It should be noted that the latch unit 25 can be various types of latch components, so details are not described here. Furthermore, Figure 2 the latch unit 25 in Figure 3 is not a necessary condition, so it is not drawn in

[0062] An implementation manner of the switching unit 21 is as follows, but the present invention is not limited thereto. The switching unit 21 includes PMOS transistors M3, M4 and two capacitors CP. Figure 3 Both ends of the left capacitor CP are electrically connected to the node FN and a low voltage (for example, the ground voltage, but not limited thereto), Figure 3 Both ends of the right capacitor CP are electrically connected to the node FP and a low voltage (for example, the ground voltage, but not limited thereto). The two gates of the PMOS transistors M3, M4 receive the frequency signal CLK, the two sources of the PMOS transistors M3, M4 are electrically connected to the system voltage DVDD, and the two drains of the PMOS transistors M3, M4 are electrically connected to the nodes FN, FP respectively.

[0063] One implementation of the differential stage 22 is as follows, but the present invention is not limited thereto. The differential stage 22 includes NMOS transistors MN1 and MN2. The two gates of the NMOS transistors MN1 and MN2 respectively receive input signals VIP and VIN. The two sources of the NMOS transistors MN1 and MN2 are electrically connected to node VS, and the two drains of the NMOS transistors MN1 and MN2 are respectively electrically connected to nodes FN and FP.

[0064] One implementation of the switched charge storage unit 23 is as follows, but the present invention is not limited thereto. The switched charge storage unit 23 has six switching transistors SW1 to SW6. The switching transistors SW1 to SW4 are NMOS transistors, and the switching transistors SW5 and SW6 are PMOS transistors. The six gates of the first to sixth switching transistors SW1 to SW6 respectively receive switching signals P_1, P_2, frequency signal CLK_D2, inverted frequency signal CLK_D2B, and switching signals PX and PY. The two drains of the switching transistors SW1 and SW2 are electrically connected to node VS. The two sources of the switching transistors SW1 and SW2 are respectively electrically connected to the first end VCTA and the second end VCTB of the charge storage capacitor CTAIL. The two drains of the switching transistors SW4 and SW3 are respectively electrically connected to the first end VCTA and the second end VCTB of the charge storage capacitor CTAIL. The two sources of the switching transistors SW4 and SW3 are connected to a low voltage (for example, ground voltage, but not limited thereto). The two sources of the switching transistors SW5 and SW6 receive the system voltage DVDD. The two drains of the switching transistors SW5 and SW6 are respectively electrically connected to the first end VCTA and the second end VCTB of the charge storage capacitor CTAIL.

[0065] One implementation of the control unit 24 is as follows, but the present invention is not limited thereto. The control unit 24 includes logic AND gates AND1 and AND2 and logic NAND gates NAND1 and NAND2. The logic AND gate AND1 receives frequency signals CLK and CLK_D2 to generate the switching signal P_2. The logic AND gate AND2 receives the frequency signal CLK and the inverted frequency signal CLK_D2B to generate the switching signal P_1. The logic NAND gate NAND1 receives the inverted frequency signal CLK_B and the frequency signal CLK_D2 to generate the switching signal PY. The logic NAND gate NAND2 receives the inverted frequency signals CLK_B and CLK_D2B to generate the switching signal PX.

[0066] Then, please refer to Figures 3 to 5 , Figures 4A to 4D is a schematic diagram of the charge storage capacitor being charged and discharged by the dynamic comparator of the embodiment of the present invention in different operating states, and Figure 5 is a signal waveform diagram of the dynamic comparator of the embodiment of the present invention. According toFigure 5 For the signal waveform diagram, the dynamic comparator 2 will first operate in the first comparison state (or switch from the second reset state to the first comparison state). The frequency signals CLK and CLK_D2 are at the logical high level, and the switch signals P_2, PX, and PY are at the logical high level. Therefore, as Figure 4A , the switching transistors SW2 and SW4 are turned on, and the other switching transistors SW1, SW3, SW5, and SW6 are turned off. The node VS is sequentially connected to the low voltage through the charge storage capacitor CTAIL. The second terminal VCTB of the charge storage capacitor CTAIL is charged from -DVDD to DVDD / 2, and the first terminal VCTA of the charge storage capacitor CTAIL maintains the low voltage. Therefore, the voltage difference between the second terminal VCTB and the first terminal VCTA of the charge storage capacitor CTAIL is DVDD / 2.

[0067] Next, the frequency signal CLK changes from the logical high level to the logical low level. The dynamic comparator 2 will switch from the first comparison state to the first reset state. The switch signal PX is at the logical high level. Therefore, as Figure 4B , the switching transistors SW4 and SW6 are turned on, and the other switching transistors SW1, SW2, SW3, and SW5 are turned off. The node VS will be disconnected from the charge storage capacitor CTAIL and not electrically connected. The second terminal VCTB of the charge storage capacitor CTAIL is charged from DVDD / 2 to DVDD, and the first terminal VCTA of the charge storage capacitor CTAIL maintains the low voltage. Therefore, the voltage difference between the second terminal VCTB and the first terminal VCTA of the charge storage capacitor CTAIL is DVDD, and the charge (CTAIL * DVDD / 2) of the charge storage capacitor CTAIL is recycled and no charge is wasted.

[0068] Next, the frequency signal CLK changes from the logical low level to the logical high level and the frequency signal CLK_D2 changes from the logical high level to the logical low level. The dynamic comparator 2 will switch from the first reset state to the second comparison state. The switch signals P_1 and PX are at the logical high level. Therefore, as Figure 4C , the switching transistors SW1 and SW3 are turned on, and the other switching transistors SW2, SW4, SW5, and SW6 are turned off. The node VS is sequentially connected to the low voltage through the charge storage capacitor CTAIL. The first terminal VCTA of the charge storage capacitor CTAIL is charged from -DVDD to DVDD / 2, and the second terminal VCTB of the charge storage capacitor CTAIL maintains the low voltage. Therefore, the voltage difference between the second terminal VCTB and the first terminal VCTA of the charge storage capacitor CTAIL is -DVDD / 2.

[0069] Next, the frequency signal CLK changes from the logical high level to the logical low level. The dynamic comparator 2 will switch from the second comparison state to the second reset state. The switch signal PY is at the logical high level. Therefore, asFigure 4D , the switching transistors SW3 and SW5 are turned on, and the other switching transistors SW1, SW2, SW4, and SW6 are turned off. The node VS is disconnected from the charge storage capacitor CTAIL and not electrically connected. The first terminal VCTA of the charge storage capacitor CTAIL is charged from DVDD / 2 to DVDD, and the second terminal VCTB of the charge storage capacitor CTAIL maintains a low voltage. Therefore, the voltage difference between the second terminal VCTB and the first terminal VCTA of the charge storage capacitor CTAIL is -DVDD, and the charge (CTAIL*DVDD / 2) of the charge storage capacitor CTAIL is recycled and not wasted.

[0070] Finally, please refer to Figure 6 , Figure 6 is a functional block diagram of the circuit system according to an embodiment of the present invention. The circuit system 6 includes a plurality of circuits. In this embodiment, the circuit system 6 is a successive approximation analog-to-digital converter. Therefore, the plurality of circuits are respectively a dynamic comparator 61, an analog-to-digital converter 62, a successive approximation register 63, and a sample / hold circuit 64. The dynamic comparator 61 can be the aforementioned dynamic comparator 2 and is electrically connected to the analog-to-digital converter 62, the successive approximation register 63, and the sample / hold circuit 64. The analog-to-digital converter 62 is electrically connected to the successive approximation register 63. The successive approximation register 63 receives the frequency signal CLK and the comparison result of the output terminal OUTP of the dynamic comparator 61 to generate a plurality of bits D0 to DN-1 for the analog-to-digital converter 62. The analog-to-digital converter 62 receives a reference voltage and generates an input signal VIN according to the plurality of bits D0 to DN-1. The sample / hold circuit 64 receives the input signal VIN' to generate the input signal VIN. The dynamic comparator 61 compares the input signals VIP and VIN. After the conversion is completed, the successive approximation register 63 outputs an end-of-conversion signal EOC.

[0071] In summary, the dynamic comparator provided by the embodiment of the present invention can recycle the charge of the charge storage capacitor when switching from the reset state to the comparison state. Therefore, compared with the prior art, the dynamic comparator has lower power consumption and lower charge and discharge current. Especially in the case of limited power, the circuit system using the dynamic comparator has a longer operation time.

[0072] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A dynamic comparator, characterized in that, It has a first node, a second node and a third node inside, and the dynamic comparator includes: A differential stage for receiving a first input signal and a second input signal, and respectively outputting a comparison result and an inverted comparison result of the first input signal and the second input signal to the second node and the first node when the dynamic comparator is in a comparison state; A switching unit electrically connecting the differential stage through the first node and the second node, and supplying a system voltage to the first node and the second node in a reset state; and A switched charge storage unit electrically connecting the differential stage through the third node, including a plurality of switching transistors and a charge storage capacitor electrically connected to the plurality of switching transistors. Wherein, when the dynamic comparator is in the comparison state, the switched charge storage unit connects the third node to a low voltage through the charge storage capacitor; when the dynamic comparator is in the reset state, the third node is disconnected from the switched charge storage unit and not electrically connected; and when the dynamic comparator switches from the comparison state to the reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage.

2. The dynamic comparator according to claim 1, wherein The dynamic comparator further includes: A control unit electrically connected to the switched charge storage unit, for receiving a first frequency signal, a first inverted frequency signal, a second frequency signal and a second inverted frequency signal, and generating a plurality of control signals accordingly to control the dynamic comparator to operate in the reset state or the comparison state, wherein the period of the second frequency signal is twice that of the first frequency signal, the first inverted frequency signal is the inverted first frequency signal, and the second inverted frequency signal is the inverted second frequency signal; Wherein the switched charge storage unit is used to receive the system voltage, a plurality of switch signals, the second frequency signal and the second inverted frequency signal, and the plurality of switching transistors are controlled by the plurality of switch signals, the second frequency signal and the second inverted frequency signal, so that when the dynamic comparator switches from the comparison state to the reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage.

3. The dynamic comparator according to claim 2, wherein Wherein the reset state includes a first reset state and a second reset state, and the comparison state includes a first comparison state and a second comparison state; when the dynamic comparator switches from the first comparison state to the second reset state, the voltage at the second end of the charge storage capacitor rises from half of the system voltage to the system voltage, and the voltage at the first end of the charge storage capacitor maintains the low voltage; when the dynamic comparator switches from the second comparison state to the first reset state, the voltage at the first end of the charge storage capacitor rises from half of the system voltage to the system voltage, and the voltage at the second end of the charge storage capacitor maintains the low voltage.

4. The dynamic comparator according to claim 3, wherein Wherein the plurality of switch signals include a first switch signal, a second switch signal, a third switch signal, and a fourth switch signal, and the plurality of switches include a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, and a sixth switch transistor. The six gates of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, and the sixth switch transistor respectively receive the first switch signal, the second switch signal, the second inverted frequency signal, the second frequency signal, the third switch signal, and the fourth switch signal. The two drains of the first switch transistor and the second switch transistor are electrically connected to the third node. The two sources of the first switch transistor and the second switch transistor are respectively electrically connected to the first end and the second end of the charge storage capacitor. The two drains of the fourth switch transistor and the third switch transistor are respectively electrically connected to the first end and the second end of the charge storage capacitor. The two sources of the fourth switch transistor and the third switch transistor are electrically connected to the low voltage. The two sources of the fifth switch transistor and the sixth switch transistor receive the system voltage, and the two drains of the fifth switch transistor and the sixth switch transistor are respectively electrically connected to the first end and the second end of the charge storage capacitor.

5. The dynamic comparator according to claim 4, characterized in that, Wherein in the first reset state, the third switch transistor and the fifth switch transistor are turned on, and the first switch transistor, the second switch transistor, the fourth switch transistor, and the sixth switch transistor are turned off; in the first comparison state, the second switch transistor and the fourth switch transistor are turned on, and the first switch transistor, the third switch transistor, the fifth switch transistor, and the sixth switch transistor are turned off; in the second reset state, the fourth switch transistor and the sixth switch transistor are turned on, and the first switch transistor, the second switch transistor, the third switch transistor, and the fifth switch transistor are turned off; in the second comparison state, the first switch transistor and the third switch transistor are turned on, and the second switch transistor, the fourth switch transistor, the fifth switch transistor, and the sixth switch transistor are turned off.

6. The dynamic comparator according to claim 4, wherein The control unit includes a first AND gate, a second AND gate, a first NAND gate, and a second NAND gate. The first AND gate receives the first frequency signal and the second frequency signal to generate the second switching signal. The second AND gate receives the first frequency signal and the second inverted frequency signal to generate the first switching signal. The first NAND gate receives the first inverted frequency signal and the second frequency signal to generate the fourth switching signal. The second NAND gate receives the first inverted frequency signal and the second inverted frequency signal to generate the third switching signal.

7. The dynamic comparator according to claim 1, wherein The differential stage includes a first transistor and a second transistor. Two gates of the first transistor and the second transistor respectively receive the first input signal and the second input signal. Two sources of the first transistor and the second transistor are electrically connected to the third node. Two drains of the first transistor and the second transistor are respectively electrically connected to the second node and the first node.

8. The dynamic comparator according to claim 1, wherein The switching unit includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor. Two ends of the first capacitor are respectively electrically connected to the second node and the low voltage. Two ends of the second capacitor are respectively electrically connected to the first node and the low voltage. Two gates of the third transistor and the fourth transistor receive a first frequency signal. Two sources of the third transistor and the fourth transistor electrically receive the system voltage. Two drains of the third transistor and the fourth transistor are respectively electrically connected to the second node and the first node.

9. A dynamic comparator, characterized in that, It has a first node, a second node, and a third node inside, and the dynamic comparator includes: A differential stage, configured to receive a first input signal and a second input signal, and output comparison results and inverted comparison results of the first input signal and the second input signal at the second node and the first node respectively in a first comparison state and a second comparison state; A switching unit, electrically connected to the differential stage through the first node and the second node, configured to receive the system voltage, and supply the system voltage to the first node and the second node in a first reset state and a second reset state; A control unit, configured to control the dynamic comparator to operate in one of the first reset state, the second reset state, the first comparison state, and the second comparison state; and A switched charge storage unit, electrically connected to the differential stage through the third node and electrically connected to the control unit, including a charge storage capacitor. When the dynamic comparator switches from the first comparison state to the second reset state, the voltage at the second end of the charge storage capacitor rises from half of the system voltage to the system voltage. When the dynamic comparator switches from the second comparison state to the first reset state, the voltage at the first end of the charge storage capacitor rises from half of the system voltage to the system voltage.

10. A circuit system, characterized in that, The circuit system includes a plurality of circuits, wherein the plurality of circuits includes a dynamic comparator as described in any one of claims 1 to 9, and the dynamic comparator is electrically connected to at least one other of the plurality of circuits.

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