Incremental analog-to-digital converter and circuitry using the same

Abstract

The embodiment of the present application provides a delta-sigma analog-to-digital converter, wherein the end point of the second reset signal (changed from logic true to logic false) received by the first non-delay component of the storage is more than one frequency period longer than the end point of the first reset signal received by other components (i.e. the reset time of the first non-delay component of the storage is longer than that of other components), so as to avoid the output of the first non-delay component of the storage from overshooting or surging. The delta-sigma analog-to-digital converter of the present application can maintain a good signal-to-noise ratio even if the internal components have low voltage swing limits.

Description

TECHNICAL FIELD

[0001] The present application relates to an incremental analog-to-digital converter, and in particular, to an incremental analog-to-digital converter capable of reducing overshoot or spike of a first integrator at reset, and a circuit system (e.g., a circuit system for sensing or monitoring an environment) using the aforementioned incremental analog-to-digital converter. BACKGROUND

[0002] Incremental analog-to-digital converter (I-ADC) is a branch of sigma-delta analog-to-digital converter (SD-ADC), which is mainly applied in low frequency and high precision field. Due to the oversampling characteristic, the matching and linearity requirement of circuit components is not as enhanced as the Nyquist rate counterparts at the same resolution.

[0003] Although the structure of I-ADC is similar to that of SD-ADC, the conversion of I-ADC can be a one-to-one relationship, and is not dependent on the previous results of SD-ADC, that is, it is more like a Nyquist rate ADC in this respect. Since I-ADC has at least one integrator in the loop, the integrator and the digital filter after it are storage components, so the values thereof should be cleared before starting conversion each time, that is, after converting the analog signal into digital signal each time, the value of the integrator and the digital filter after it should be cleared before converting the next analog signal, and the reset action is needed.

[0004] Please refer to Figure 1, the prior art I-ADC 1 includes a first stage integrator module 11, a weight adder module 12, 14, a second stage integrator module 13, a limiter 15, a quantizer 16, a feedback module 17 and a weight subtractor module 18. The weight subtractor module 18 subtracts the analog input signal VA from the feedback signal VF generated by the feedback module 17 by a weight, and generates a signal V0 to the first stage integrator module 11. The first stage integrator module 11 integrates the signal V0, and generates a signal V1. The weight adder module 12 adds the signal V1 to the analog input signal VA by a weight, and generates a signal V2 to the second stage integrator module 13. The second stage integrator module 13 integrates the signal V2, and generates a signal V3. The weight adder module 14 adds the signal V1, V3, the analog input signal VA by a weight, and generates a signal V4 to the limiter 15. The limiter 15 limits the signal V4, and generates a signal V5. The quantizer 16 quantizes the signal V5 to generate a digital output signal VD. The feedback module 17 receives the digital output signal VD, and generates a feedback signal VF, wherein the feedback signal VF is a delayed signal generated according to the digital output signal VD.

[0005] Please refer to Figure 1 and Figure 2 , the I-ADC 1 needs to spend multiple frequency periods to integrate the analog input signal VA before outputting the final digital output signal VD. After the current analog input signal VA is converted into the digital output signal VD, the storage components in the I-ADC 1 need to be reset to clear the values stored in the storage components before the next analog input signal VA is converted into the digital output signal VD.

[0006] Please refer to Figure 1 and Figure 3 , the first reset signal RST is directly received by the first stage integrator module 11, the second stage integrator module 13 and the feedback module 17, and is used to reset the first stage integrator module 11, the second stage integrator module 13 and the feedback module 17. Since the first stage integrator module 11 and the second stage integrator module 13 are non-delay components, but the feedback module 17 is a delay component, in the first frequency period of the reset process, the signal V1 generated by the first stage integrator module 11 is only the result of integrating the analog input signal VA, and does not include the result of integrating the feedback signal VF (note: the feedback signal VF is reset to 0), so the signal V1 will have an overshoot or a spike 31.

[0007] I-ADC 1 can recover from the overshoot in only a few consecutive frequency cycles and does not necessarily affect the final performance of I-ADC 1. However, if the internal swing of I-ADC 1 is limited by the actual circuit, the signal-to-noise-and-distortion ratio (SNDR) will be reduced. In particular, in the case of low voltage swing, for example, in the case of I-ADC 1 of Figure 1 95.5 dB without swing limitation, but only 83 dB with swing limit of ±0.8 volts, and the fast Fourier transform (FFT) of the digital output signal VD shows that the harmonic distortion is very obvious. SUMMARY

[0008] According to the purpose of the present application, an embodiment of the present application provides an increment type analog-to-digital converter (I-ADC), which comprises a conversion circuit and a reset signal processing module. The conversion circuit is used to implement increment type analog-to-digital conversion and comprises a plurality of integrator modules and a feedback module. The reset signal processing module is electrically connected to the conversion circuit and is used to receive a first reset signal and generate a second reset signal according to the first reset signal, wherein the starting time point of the first reset signal and the second reset signal is the same, but the ending time point of the second reset signal is more than one frequency cycle than the ending time point of the first reset signal. The first stage integrator module in the plurality of integrator modules is reset by the second reset signal, and the other stage integrator module in the plurality of integrator modules and the feedback module are reset by the first reset signal.

[0009] In an embodiment of the present application, the increment type analog-to-digital converter is a two-stage integrator module increment type analog-to-digital converter, and the other stage integrator module comprises a second stage integrator module.

[0010] In one embodiment of the present application, the incremental analog-to-digital converter further comprises a first weight adder module, a second weight adder module, a limiter, a quantizer and a weight subtractor module, wherein: the first integrator module receives and integrates a first signal to generate a second signal; the first weight adder module is electrically connected to the first integrator module and performs weighted addition of the second signal and an analog input signal to generate a third signal; the second integrator module is electrically connected to the first weight adder module and receives and integrates the third signal to generate a fourth signal; the second weight adder module is electrically connected to the second integrator module and performs weighted addition of the fourth signal, the second signal and the analog input signal to generate a fifth signal; the limiter is electrically connected to the second weight adder module and receives and limits the fifth signal to generate a sixth signal; the quantizer is electrically connected to the limiter and quantizes the sixth signal to generate a digital output signal; the feedback module is electrically connected to the quantizer and receives the digital output signal to generate a feedback signal, wherein the feedback signal is a delayed signal generated according to the digital output signal; and the weight subtractor module is electrically connected to the feedback module and the first integrator module and performs weighted subtraction of the analog input signal and the feedback signal to generate the first signal.

[0011] In one embodiment of the present application, the end point of the second reset signal is one frequency period later than the end point of the first reset signal.

[0012] In one embodiment of the present application, the reset signal processing module comprises an OR gate and a transfer function unit, the OR gate is electrically connected to the first integrator module and the transfer function unit, the transfer function of the transfer function unit is (1 / z), and the transfer function unit is configured to output the first reset signal after delaying the first reset signal by one frequency period to the OR gate, the OR gate is configured to perform OR operation on the first reset signal and the first reset signal delayed by one frequency period to generate the second reset signal.

[0013] In one embodiment of the present application, the transfer function of the transfer function unit in the first integrator module is z / (z-1).

[0014] In one embodiment of the present application, the transfer function of the transfer function unit in the second integrator module is z / (z-1).

[0015] In one embodiment of the present application, the transfer function of the transfer function unit in the second integrator module is 1 / (z-1).

[0016] According to the purpose of the present application, the embodiment of the present application provides an incremental analog-to-digital converter (I-ADC), which comprises a conversion circuit and a reset signal processing module for realizing incremental analog-to-digital conversion. The conversion circuit comprises a plurality of storage components, and the plurality of storage components comprise a first-stage non-delay storage component. The reset signal processing module is used for receiving a first reset signal and generating a second reset signal according to the first reset signal, wherein the starting time point of the first reset signal is the same as that of the second reset signal, but the ending time point of the second reset signal is more than one frequency period than that of the first reset signal. The first-stage non-delay storage component is reset by the second reset signal, and the other storage components are reset by the first reset signal.

[0017] According to the purpose of the present application, the embodiment of the present application provides a circuit system, which comprises a signal acquisition device, the aforementioned I-ADC and a processing device, wherein the I-ADC is electrically connected with the signal acquisition device and the processing device.

[0018] In summary, the incremental analog-to-digital converter provided by the embodiment of the present application can maintain good SNDR under the condition of limited internal swing, because the first-stage integrator module (first-stage non-delay storage component) does not have overshoot or surge after reset.

[0019] For further understanding of the technical means and effects of the present application, the following detailed description and drawings can be referred to, so that the purpose, features and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and drawings are only used for reference and illustration of the implementation mode of the present application, and are not used for limiting the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The present application can be more fully understood by the following detailed description and drawings, in which:

[0021] Figure 1 is a schematic diagram of the functional modules of the prior art I-ADC;

[0022] Figure 2 is a schematic diagram of the operating states of the I-ADC;

[0023] Figure 3 is a schematic diagram of the signal waveforms of the prior art I-ADC;

[0024] Figure 4 is a schematic diagram of the functional modules of the I-ADC of the embodiment of the present application;

[0025] Figure 5is a schematic diagram of signal waveforms of the I-ADC of the embodiment of the present application.

[0026] Figure 6 is a schematic diagram of signal waveforms of the I-ADC of the embodiment of the present application.

[0027] The symbols denoted in the drawings are explained as follows: 1, 2 incremental analog-to-digital converter; 11 first integrator module; 111, 131, 171 switch; 112, 132, 172, 191 transfer function unit 113, 123, 15 limiter; 12, 14 weight adder module; 121, 122, 141-143, 181, 183 amplifier; 123, 144 adder; 13 second integrator module; 16 quantizer; 17 feedback module; 18 weight subtractor module; 181 subtractor; 19 reset signal processing module; 192 OR gate; 31 overshoot or glitch; RST first reset signal; RST' second reset signal; T RST , T RST＇ during operation; V0-V5 signal; V A analog input signal; V D digital output signal; V F feedback signal. DETAILED DESCRIPTION

[0028] Reference will now be made to the exemplary embodiments of the present application, which will be illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in various drawings and the same or similar components will be referred to by the same reference numbers. In addition, the practice of the exemplary embodiments is merely one implementation of the design concepts of the present application, and the following exemplary embodiments are not intended to limit the present application.

[0029] The embodiment of the present application provides an incremental analog-to-digital converter, wherein the end point of the second reset signal received by the first non-delay component of the incremental analog-to-digital converter is more than one frequency period later than the end point of the first reset signal received by other components, so as to avoid overshoot or glitch of the output of the first non-delay component with memory, and thus the incremental analog-to-digital converter of the present application can maintain good SNDR even if the internal components have low voltage swing limitation.

[0030] In particular, compared to the prior art, the delta-sigma analog-to-digital converter of the present embodiment additionally has a reset signal processing module that processes a first reset signal to generate a second reset signal, wherein the first reset signal and the second reset signal have the same starting point (the point at which the logic false becomes the logic true), but the second reset signal has an ending point that is more than one frequency period later than the ending point of the first reset signal.

[0031] Briefly, the delta-sigma analog-to-digital converter can include a conversion circuit and a reset signal processing module, wherein the conversion circuit is used to implement delta-sigma analog-to-digital conversion, and the storage first non-delay component in the conversion circuit uses the second reset signal for resetting, and other storage components in the conversion circuit that need to be reset use the second reset signal for resetting. When the conversion circuit is used to implement delta-sigma analog-to-digital conversion, it can be a delta-sigma analog-to-digital converter having more than two integrator modules and feedback modules.

[0032] Please refer to Figure 4 The delta-sigma analog-to-digital converter 2 of the present embodiment includes a first integrator module 11, weight adder modules 12, 14, a second integrator module 13, a limiter 15, a quantizer 16, a feedback module 17, a weight subtractor module 18, and a reset signal processing module 19. Except for the reset signal processing module 19, the above-mentioned hardware components that constitute the conversion circuit can be divided into non-delay components and delay components, wherein some of the non-delay components are storage components and thus need to be reset after completing one analog-to-digital conversion. The storage non-delay components include the first integrator module 11, the second integrator module 13, and the feedback module 17, wherein the first integrator module 11 is a storage first non-delay component.

[0033] The first integrator module 11 is electrically connected to the weight subtractor module 18, the reset signal processing module 19, and the weight adder module 12. The second integrator module 13 is electrically connected to the weight adder modules 12, 14. The weight adder module 14 is further electrically connected to the first integrator module 11 and the limiter 15. The quantizer 16 is electrically connected to the limiter 15 and the feedback module 17, and the feedback module 17 is electrically connected to the weight subtractor module 18.

[0034] The weight subtractor module 18 subtracts the analog input signal V A from the feedback signal generated by the feedback module 17 to generate a signal V0 to the first integrator module 11. Further, the weight subtractor module 18 is composed of two amplifiers 182, 183 and a subtractor 181, wherein the subtractor 181 is electrically connected to the amplifiers 182, 183 and the first integrator module 11. The amplifiers 182, 183 respectively amplify the analog input signal VA and the feedback signal V F The subtractor 181 then subtracts the amplified analog input signal V A and the feedback signal V F to generate a signal V0, i.e., V0[n] = al x V A [n] - a2 x V F [n], where al and a2 are the gains of the amplifiers 182, 183, respectively, and n is a discrete time value, e.g., "n = x" indicates that the present time point is the xth frequency period. In addition, V F is a delayed signal of the digital output signal V D , e.g., V F [n] = V D [n - 1].

[0035] The first integrator module 11 integrates the signal V0 and generates a signal V1. Further, the first integrator module 11 comprises a switch 111, a transfer function unit 112, and a limiter 113, where the switch 111 is electrically connected to the reset signal processing module 19 and the weight subtractor module 18, the transfer function unit 112 is electrically connected to the switch 111 and the limiter 113, and the limiter 113 is electrically connected to the weight adder module 12. The switch 111 receives the signal V0, 0, and a second reset signal RST', and outputs the signal V0 or 0 to the transfer function unit 112 according to whether the second reset signal RST' is a logic true or a logic false, where the second reset signal RST' is a logic true, the output is 0, otherwise, the output is V0. The transfer function of the transfer function unit 112 is z / (z - 1) to thereby integrate the output signal V0, and the transfer function unit 112 also receives the second reset signal RST' to be reset when the second reset signal RST' is a logic true. The limiter 113 then limits the output of the transfer function unit 112 to generate the signal V1. In addition, since the transfer function of the transfer function unit 112 is z / (z - 1), the first integrator module 11 is a storage non-delay component of the I-ADC 2, and is a storage first non-delay component among the at least one non-delay component.

[0036] The weight adder module 12 weight-adds the signal V1 and the analog input signal V A and generates a signal V2 to the second integrator module 13. Further, the weight adder module 12 is composed of two amplifiers 121, 122 and an adder 123, where the adder 123 is electrically connected to the amplifiers 121, 122 and the second integrator module 13. The amplifiers 121, 122 amplify the signal V1 and the analog input signal V A , respectively, and the adder 123 then subtracts the amplified signal V1 and the analog input signal V AV2[n] = a3 x V1[n] - a4 x V A where a3 and a4 are the gains of the amplifiers 121, 123, respectively.

[0037] The second integrator module 13 integrates the signal V2 and generates a signal V3. Further, the second integrator module 13 comprises a switch 131, a transfer function unit 132 and a limiter 133, wherein the switch 131 is electrically connected to the weight adder module 12, the transfer function unit 132 is electrically connected to the switch 131 and the limiter 133, and the limiter 133 is electrically connected to the weight adder module 14. The switch 131 receives the signal V2, 0 and a first reset signal RST, and outputs the signal V2 or 0 to the transfer function unit 132 according to whether the first reset signal RST is logic true or logic false, wherein the switch 131 outputs 0 when the first reset signal RST is logic true, and otherwise outputs V2. The transfer function of the transfer function unit 132 is z / (z-l) to integrate the output signal V2, and the transfer function unit 132 also receives the first reset signal RST to be reset when the first reset signal RST is logic true. The limiter 133 then limits the output of the transfer function unit 132 to generate the signal V3. Since the transfer function of the transfer function unit 112 is z / (z-l), the second integrator module 11 is a non-delay component of the I-ADC 2, and is a second non-delay component of the at least one non-delay component. Please note that the transfer function of the transfer function unit 112 can be changed to 1 / (z-l) so that the second integrator module 11 is a delay component of the I-ADC 2.

[0038] The weight adder module 14 adds the signals V1, V3, the analog input signal V A and generates a signal V4 to the limiter 15. Further, the weight adder module 14 is composed of three amplifiers 141-143 and an adder 143, wherein the adder 143 is electrically connected to the amplifiers 141-143 and the limiter 15. The amplifiers 141-143 amplify the signals V3, the analog input signal V A and the signal V1, respectively. The adder 143 then adds the amplified signals V1, V3 and the analog input signal V A to generate the signal V4, i.e. V4[n] = a5 x V3[n] + a6 x V A [n] + a7 x V1[n], where a5-a7 are the gains of the amplifiers 141-143, respectively.

[0039] The limiter 15 limits the signal V4 and generates a signal V5. The quantizer 16 quantizes the signal V5 to generate a digital output signal V Dwherein quantizer 16 is, for example, a 3-bit quantizer, or more bits, and the present application is not limited in this regard. Feedbacker module 17 receives digital output signal V D and generates feedback signal V F wherein feedback signal V F is a delayed signal generated from digital output signal V D . Further, feedbacker module 17 includes switch 171 electrically connected to quantizer 16 and transfer function unit 172 electrically connected to switch 171 and weight subtracter module 18. Switch 171 receives signals V D , 0 and first reset signal RST and outputs signal V D or 0 to transfer function unit 172 depending on whether first reset signal RST is logic true or logic false, wherein signal 0 is output when first reset signal RST is logic true and signal V D is output otherwise. Transfer function unit 172 has a transfer function of 1 / z whereby output signal V D is delayed by one frequency period (V F [n] = V D [n-1]) to generate feedback signal V F . Transfer function unit 172 also receives first reset signal RST to be reset when first reset signal RST is logic true.

[0040] Reset signal processing module 19 receives first reset signal RST and generates second reset signal RST' wherein first reset signal RST and second reset signal RST' have the same starting point (the point in time when it changes from logic false to logic true) but second reset signal RST' has an ending point that is more than one frequency period later than the ending point of first reset signal RST. Further, reset signal processing module 19 includes transfer function unit 191 electrically connected to OR gate 192 and OR gate 192 electrically connected to first integrator module 11. In this embodiment, transfer function unit 191 has a transfer function of (1 / z) and thus outputs first reset signal RST delayed by one frequency period to OR gate 192. OR gate 192 ORs first reset signal RST and first reset signal RST delayed by one frequency period to generate second reset signal RST' and thus the ending point of second reset signal RST' is more than one frequency period later than the ending point of first reset signal RST.

[0041] It is noted that the above example is described with respect to the I-ADC 2 having two-stage integrator modules, but the present application is not limited thereto. In other embodiments, the conversion circuit for I-ADC function can include three-stage integrator modules or more, and according to the inventive concept of the present application, the first stage integrator module is reset using the second reset signal RST' while the second stage to the last stage integrator modules and the feedback module are reset using the first reset signal RST. In brief, the reset time of the second stage to the last stage integrator modules and the feedback module is less than that of the first stage integrator module by at least one frequency period during the reset phase.

[0042] Referring to Figure 4 and Figure 5 , in the reset phase, the operation period of the first reset signal RST is m frequency periods and the operation period of the second reset signal RST' is k frequency periods, where k and m are integers and k > m. In the embodiment of the present application, k = m + 1. Referring to Figure 5 and Figure 4 , since the operation period T RST＇ of the second reset signal RST' is k frequency periods, the operation period T RST of the first reset signal RST is m frequency periods, and the first stage integrator module 11 is reset using the second reset signal RST', the signal V1 generated by the first stage integrator module 11 after the reset phase will not have overshoot or glitch. Thus, the I-ADC 2 can maintain a good SNDR under the voltage swing limitation of the internal components. Figure 4 Figure 6

[0043] In addition, the present application provides a circuit system including a signal acquisition device, an incremental analog-to-digital converter and a processing device, wherein the incremental analog-to-digital converter is electrically connected to the signal acquisition device and the processing device. The signal acquisition device can be various types of sensors or measuring devices, but is not limited thereto. The signal acquisition device is used to generate an analog input signal to the incremental analog-to-digital converter. The incremental analog-to-digital converter is implemented as described above, and is used to convert the analog input signal to a digital output signal. The digital output signal is received by the processing device and processed, for example, output, calculation or analysis of the digital output signal, but the present application is not limited thereto.

[0044] ​​In summary, the embodiment of the present application provides an incremental analog-to-digital converter, in which the time for resetting the first-stage non-delay component with storage is longer than the time for resetting other components with storage, so that the overshoot or surge of the first-stage non-delay component with storage after completing the reset can be avoided, and thus the incremental analog-to-digital converter of the embodiment of the present application can maintain a good SNDR under the limitation of the voltage swing of the internal components.

[0045] It will be understood that the above-described embodiments are cited by way of example, and that the present application is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present application includes both combinations and sub-combinations of the various features described above, as well as variations and modifications such as would be obvious to one skilled in the art upon reading the foregoing description. The documents incorporated by reference into this patent application are to be considered an integral part of the application except that to the extent any terms are defined in such incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, the definitions in the present specification take precedence.

Claims

1. An incrementing analog-to-digital converter, characterized by The increment type analog-digital converter comprises: a conversion circuit for implementing increment type analog-digital conversion, comprising a plurality of integrator modules and a feedback module; and a reset signal processing module for receiving a first reset signal and generating a second reset signal according to the first reset signal, wherein the starting time point of the first reset signal and the second reset signal is the same, but the ending time point of the second reset signal is more than the ending time point of the first reset signal by one or more frequency periods; wherein the first stage integrator module in the plurality of integrator modules is reset by the second reset signal, and the other stage integrator modules and the feedback module are reset by the first reset signal.

2. The incrementing analog-to-digital converter of claim 1, wherein, wherein the increment type analog-digital converter is a two-stage integrator module increment type analog-digital converter, and the other stage integrator module comprises a second stage integrator module.

3. The incrementing analog-to-digital converter of claim 2, wherein, The increment type analog-digital converter further comprises a first weight adder module, a second weight adder module, a limiter, a quantizer and a weight subtractor module, wherein: the first stage integrator module receives and integrates a first signal to generate a second signal; the first weight adder module is electrically connected to the first stage integrator module, and performs weighted addition on the second signal and an analog input signal to generate a third signal; the second stage integrator module is electrically connected to the first weight adder module, receives and integrates the third signal to generate a fourth signal; the second weight adder module is electrically connected to the second stage integrator module, and performs weighted addition on the fourth signal, the second signal and the analog input signal to generate a fifth signal; the limiter is electrically connected to the second weight adder module, receives and limits the fifth signal to generate a sixth signal; the quantizer is electrically connected to the limiter, and quantizes the sixth signal to generate a digital output signal; the feedback module is electrically connected to the quantizer, receives the digital output signal to generate a feedback signal, wherein the feedback signal is a delayed signal generated according to the digital output signal; and the weight subtractor module is electrically connected to the feedback module and the first stage integrator module, and performs weighted subtraction on the analog input signal and the feedback signal to generate the first signal.

4. The incrementing analog-to-digital converter of claim 1, wherein, The ending time point of the second reset signal is more than the ending time point of the first reset signal by one frequency period.

5. The incrementing analog-to-digital converter of claim 4, wherein, The reset signal processing module comprises an OR gate and a transfer function unit, the OR gate is electrically connected to the first stage integrator module and the transfer function unit, the transfer function of the transfer function unit is (1 / z), used for outputting the first reset signal delayed by one frequency period to the OR gate, and the OR gate performs OR operation on the first reset signal and the first reset signal delayed by one frequency period to generate the second reset signal.

6. The incrementing analog-to-digital converter of claim 3, wherein, The transfer function of the transfer function unit in the first stage integrator module is z / (z-1).

7. The incrementing analog-to-digital converter of claim 6, wherein, The transfer function of the transfer function unit in the second stage integrator module is z / (z-1).

8. The incrementing analog-to-digital converter of claim 6, wherein, The transfer function of the transfer function unit in the second stage integrator module is 1 / (z-1).

9. An incrementing analog-to-digital converter, characterized by The incremental analog-to-digital converter comprises: A conversion circuit for implementing incremental analog-to-digital conversion, wherein the conversion circuit comprises a plurality of storage components, and the plurality of storage components comprise a first stage of non-delay storage components; and A reset signal processing module for receiving a first reset signal and generating a second reset signal according to the first reset signal, wherein the starting time point of the first reset signal and the second reset signal is the same, but the ending time point of the second reset signal is more than one frequency period than the ending time point of the first reset signal; Wherein the first stage of non-delay storage components are reset by the second reset signal, and the other storage components are reset by the first reset signal.

10. A circuit system, characterized by, The circuit system comprises: A signal acquisition device; The incremental analog-to-digital converter according to any one of claims 1 to 9 is electrically connected to the signal acquisition device; and A processing device electrically connected to the incremental analog-to-digital converter.

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