Fast successive cancellation decoding method and device for polar code special node

Abstract

This invention proposes a fast continuous cancellation decoding method for special nodes of polar codes, comprising: determining special nodes in the target decoding tree for continuous cancellation decoding based on the distribution of polar code information bits and frozen bits, wherein the special nodes include a first dual constraint and a second dual constraint; performing a hard decision on the log-likelihood ratio sequence of the special nodes to obtain a first estimated codeword sequence; calculating the check value of the first dual constraint, and flipping the bit estimates in the first estimated codeword sequence based on the check value of the first dual constraint to obtain a second estimated codeword sequence; calculating the check value of the second dual constraint, constructing a set of flipped bit pairs based on the check value of the second dual constraint, selecting the bit pair with the smallest metric in the set, and flipping the bit estimates at the corresponding positions of the bit pairs in the second estimated codeword sequence to obtain the target estimated codeword sequence. This method significantly reduces decoding latency while maintaining performance lossless and is easy to implement on hardware platforms.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology. Background Technology

[0002] Polar codes are a channel coding scheme theoretically proven to achieve Shannon capacity and have been adopted by fifth-generation mobile communication systems (5G). Decoding algorithms have a significant impact on the error correction capability of polar codes in practical applications. Among them, decoding algorithms based on Successive Cancellation (SC) employ a bit-by-bit decoding method, effectively utilizing the polarization effect and exhibiting good error correction performance, attracting widespread attention from academia and industry. However, SC decoding algorithms have two main drawbacks. Firstly, according to polarization theory, polar codes under SC decoding can only achieve channel capacity when the code length approaches infinity. Therefore, in practice, SC decoding cannot provide reasonable error correction performance for polar codes with finite code lengths. Successive Cancellation List (SCL) decoding, by maintaining a list that preserves multiple most reliable codeword sequences, greatly improves the error correction performance of SC decoding. By concatenating polar codes with Cyclic Redundancy Check (CRC), CRC-Aided SCL (CA-SCL) decoders offer decoding performance approaching that of maximum-likelihood (ML) decoders. This makes polar codes a strong competitor to other state-of-the-art channel coding systems such as Low-Density Parity-Check (LDPC) codes and Turbo codes. On the other hand, the bit-by-bit sequential nature of SC decoding leads to high decoding latency and low throughput, hindering its application in low-latency communication scenarios such as Ultra-Reliable Low-Latency Communication (URLLC). To achieve efficient decoding, a common approach is to parallelize the decoding process, decoding at the intermediate node level of the decoding tree rather than the leaf node level, thereby avoiding traversal of the entire code tree and improving decoding speed. To ensure that decoding performance does not degrade, node-level decoding needs to consider the constraints imposed by the distribution characteristics of information and frozen bits within the node, so that the decoding result is valid. Therefore, the higher the level of the decoding tree where the node is located, the higher the parallelism, the lower the decoding latency, and the higher the throughput. However, at the same time, the more bits a node contains, the more complex the constraints become, which makes it difficult to implement a lossless decoding algorithm. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the related art.

[0004] Therefore, the purpose of this invention is to propose a fast continuous cancellation decoding method for special nodes of polar codes to reduce decoding delay.

[0005] To achieve the above objectives, a first aspect of the present invention proposes a fast successive cancellation decoding method for special nodes of polar codes, comprising:

[0006] Based on the distribution of polar code information bits and frozen bits, special nodes in the target decoding tree for continuous cancellation decoding are determined, and the special nodes include the first dual constraint and the second dual constraint.

[0007] A hard decision is made on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence;

[0008] Calculate the check value of the first dual constraint, and flip the bit estimates in the first estimated codeword sequence according to the check value of the first dual constraint to obtain the second estimated codeword sequence;

[0009] Calculate the check value of the second dual constraint, construct a set of flipped bit pairs based on the check value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimate value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

[0010] In addition, the fast successive cancellation decoding method for special nodes of polar codes according to the above embodiments of the present invention may also have the following additional technical features:

[0011] Furthermore, in one embodiment of the present invention, the special node is a polar code sub-code comprising a source node and a sequence of code rate one or single even parity check code sub-nodes.

[0012] Further, in one embodiment of the present invention, the step of making a hard decision on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence includes:

[0013] When the log-likelihood ratio is greater than 0, the hard decision result is 0; otherwise, the hard decision result is 1.

[0014] Furthermore, in one embodiment of the present invention, calculating the verification value of the first dual constraint includes:

[0015] Calculate the log-likelihood ratio sequence of the source nodes in the special nodes, and decode the source nodes according to the log-likelihood ratio sequence to obtain the source node estimated codeword sequence;

[0016] The check value of the first dual constraint is calculated based on the codeword sequence estimated from the source node.

[0017] Further, in one embodiment of the present invention, obtaining the source node estimated codeword sequence includes:

[0018] If the source node has a special structure, the estimated codeword sequence of the source node can be calculated using the fast decoding algorithm corresponding to the source node;

[0019] If the source node has a general structure, the estimated codeword sequence of the source node can be calculated using the traditional serial cancellation decoding algorithm.

[0020] Further, in one embodiment of the present invention, the step of flipping the bit estimates in the first estimated codeword sequence according to the check value of the first dual constraint includes:

[0021] If the codeword sequence already satisfies the first type of duality check value, then no bit flipping operation is performed;

[0022] If the codeword sequence does not satisfy the first type of duality check value, then the bit with the smallest absolute log-likelihood ratio is bit-flipped.

[0023] Furthermore, in one embodiment of the present invention, constructing a set of flipped bit pairs based on the check value of the second dual constraint includes:

[0024] The set is generated offline.

[0025] To achieve the above objectives, a second aspect of the present invention provides a fast successive cancellation decoding apparatus for special nodes of polar codes, comprising:

[0026] The acquisition module is used to determine special nodes in the target decoding tree of continuous cancellation decoding based on the distribution of polar code information bits and frozen bits. The special nodes include a first dual constraint and a second dual constraint.

[0027] The decision module is used to make a hard decision on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence;

[0028] The first verification module is used to calculate the verification value of the first dual constraint, and flip the bit estimation values ​​in the first estimated codeword sequence according to the verification value of the first dual constraint to obtain the second estimated codeword sequence.

[0029] The second verification module is used to calculate the verification value of the second dual constraint, construct a set of flipped bit pairs based on the verification value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimation value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

[0030] To achieve the above objectives, a third aspect of the present invention provides a computer device, characterized in that it includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the fast continuous cancellation decoding method for special nodes of polar codes as described above.

[0031] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the fast continuous cancellation decoding method for special nodes of polar codes as described above.

[0032] The present invention provides a fast continuous cancellation decoding method for special nodes of polar codes. In the first aspect, the present invention proposes a novel type of special node with higher parallelism. In the second aspect, for the proposed special node, the present invention proposes a fast continuous cancellation decoding algorithm. The proposed decoding algorithm considers the dual constraints contained in the node and can greatly reduce the decoding latency without sacrificing error correction performance. Attached Figure Description

[0033] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0034] Figure 1 This is a flowchart illustrating a fast continuous cancellation decoding method for special nodes of polar codes provided in an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of a special node structure provided in an embodiment of the present invention.

[0036] Figure 3 The flowchart illustrates a fast, continuous cancellation decoding algorithm for special nodes of polar codes provided in an embodiment of the present invention.

[0037] Figure 4 This is a flowchart for constructing a set of flipped bit pairs according to an embodiment of the present invention.

[0038] Figure 5 A comparison of the theoretical decoding delays of the fast continuous cancellation decoding algorithm for special nodes of polar codes provided in this embodiment of the invention and the traditional continuous cancellation decoding algorithm.

[0039] Figure 6 This is a comparison of the error correction performance of the fast continuous cancellation decoding algorithm for special nodes of polar codes provided in this embodiment of the invention with that of the traditional continuous cancellation decoding algorithm.

[0040] Figure 7 This is a flowchart illustrating a fast continuous cancellation decoding device for special nodes of polar codes, provided as an embodiment of the present invention. Detailed Implementation

[0041] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0042] The fast successive cancellation decoding method for special nodes of polar codes according to embodiments of the present invention is described below with reference to the accompanying drawings.

[0043] Example 1

[0044] Figure 1 This is a flowchart illustrating a fast continuous cancellation decoding method for special nodes of polar codes provided in an embodiment of the present invention.

[0045] like Figure 1 As shown, the fast successive cancellation decoding method for special nodes of this polar code includes the following steps:

[0046] S101: Based on the distribution of polar code information bits and frozen bits, determine the special nodes in the target decoding tree of continuous cancellation decoding. The special nodes include the first dual constraint and the second dual constraint.

[0047] S102: Hard decision is made on the log-likelihood ratio sequence of special nodes to obtain the first estimated codeword sequence;

[0048] S103: Calculate the check value of the first dual constraint, and flip the bit estimate values ​​in the first estimated codeword sequence according to the check value of the first dual constraint to obtain the second estimated codeword sequence;

[0049] S104: Calculate the check value of the second dual constraint, construct a set of flipped bit pairs based on the check value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimate value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

[0050] Specifically, successive cancellation decoding can be regarded as a traversal process from the root node to the leaf node of the decoding tree and from the left subtree to the right subtree. There are two types of information that are transmitted between nodes in the decoding tree. The first type is the sequence of log-likelihood ratios transmitted from the upper-level node to the lower-level node (specifically, at the root node, the decoder calculates the sequence of channel log-likelihood ratios provided by the previous module). The second type is the estimated codeword sequence transmitted from the lower-level node to the upper-level node. During the decoding process, the log-likelihood ratios are calculated level by level and transmitted to the next-level node in sequence. When the decoding reaches the level of the special node, the estimated codeword sequence is directly calculated based on the sequence of log-likelihood ratios of the special node, and the estimated codeword sequence is calculated level by level and transmitted to the upper-level node in sequence until the root node. The above process is continuously repeated until the decoding of the last leaf node is completed.

[0051] When successive cancellation decoding encounters a special node, a hard decision is directly made on the sequence of log-likelihood ratios of the node to obtain a preliminary estimated codeword sequence.

[0052] Further, in an embodiment of the present invention, the special node is a polar code sub-code including a source node and a sequence of rate-1 or single parity check code child nodes.

[0053] Figure 2 Schematic diagram of the special node structure provided in an embodiment of the present invention. Refer to Figure 2 , and the special node in this embodiment is described in detail.

[0054] For the i-th node in the p-th layer of the successive cancellation decoding tree, define and as the sequence of log-likelihood ratios (Log-likelihood Ratio, LLR) and the codeword estimation sequence of the node respectively. Refer to Figure 2 , define a special node of the i-th node in the p-th layer located in the decoding tree. This node is composed of a source node and a sequence of rate-1 (Rate-1, R1) or single parity check code (Single Parity Check, SPC) child nodes, where the source node is located at the leftmost end L of the q-th layer r = 2 p-r (i - 1)+1, and the second node L in each layer where q ≤ r < p r +1 is an R1 or SPC child node. Therefore, this special node is called a sequence R1 or SPC node (Sequence R1 or SPC, SR1 / SPC).

[0055] Further, in an embodiment of the present invention, making a hard decision on the sequence of log-likelihood ratios of the special node to obtain the first estimated codeword sequence includes:

[0056] When the log-likelihood ratio is greater than 0, the hard decision result is 0; otherwise, the hard decision result is 1.

[0057] Furthermore, in one embodiment of the present invention, calculating the verification value of the first dual constraint includes:

[0058] Calculate the log-likelihood ratio sequence of the source nodes in the special nodes, and decode the source nodes according to the log-likelihood ratio sequence to obtain the estimated codeword sequence of the source nodes;

[0059] Calculate the check value of the first dual constraint based on the codeword sequence estimated from the source node.

[0060] Furthermore, in one embodiment of the present invention, obtaining the source node estimated codeword sequence includes:

[0061] If the source node has a special structure, the estimated codeword sequence of the source node can be calculated by the fast decoding algorithm corresponding to the source node;

[0062] If the source node has a general structure, the estimated codeword sequence of the source node can be calculated using the traditional serial cancellation decoding algorithm.

[0063] Further, in one embodiment of the present invention, flipping the bit estimates in the first estimated codeword sequence according to the check value of the first dual constraint includes:

[0064] If the codeword sequence already satisfies the first type of duality check value, then no bit flipping operation is performed;

[0065] If the codeword sequence does not satisfy the first type of duality check value, then the bit with the smallest absolute log-likelihood ratio is bit-flipped.

[0066] Furthermore, in one embodiment of the present invention, constructing a set of flipped bit pairs based on the check value of the second dual constraint includes:

[0067] Generate collections offline.

[0068] Example 2

[0069] On the other hand, embodiments of the present invention propose a fast successive cancellation decoding algorithm for special nodes of polar codes, see reference. Figure 3 The decoding algorithm may include the following steps:

[0070] S1: When continuous cancellation decoding encounters an SR1 / SPC node, two types of dual constraints are determined;

[0071] S2: A preliminary estimated codeword sequence is obtained by directly making a hard decision on the log-likelihood ratio sequence of the node;

[0072] S3: Calculate the log-likelihood ratio sequence of the source node, and decode the source node according to the log-likelihood ratio sequence to obtain the estimated codeword sequence of the source node;

[0073] S4: Calculate the first type duality check value, and perform bit flipping on the estimated codeword sequence to make it satisfy the first type duality constraint;

[0074] S5: Calculate the second type duality check value, determine a set consisting of flipped bit pairs, and calculate the metric for each bit pair in the set;

[0075] S6: Select the bit pair with the smallest metric, perform bit flipping on the estimated codeword sequence to satisfy the second type of duality constraint, and the estimated codeword sequence after the flipping is the final output.

[0076] Specifically, in operation S1, for SR1 / SPC nodes, their codeword estimation sequences need to satisfy two dual constraints. The first dual constraint is the Parallel Parity Constraint (P-PC), which is caused by the source node. The specific form of the constraint on the codeword is as follows:

[0077]

[0078] The second type of dual constraint is the Segmental Parity Constraint (S-PC), which is caused by SPC child nodes. The specific form of the constraint on the codeword is as follows:

[0079]

[0080] in This indicates an XOR bitwise operation, and r represents the layer number where the SPC child node is located.

[0081] In operation S2, a hard decision is made directly on the received LLR sequence of the SR1 / SPC node, resulting in the preliminary estimated codeword sequence:

[0082]

[0083] Where HD(·) is the hard decision function.

[0084] In operation S3, the LLR and estimated codeword sequences of the SR1 / SPC nodes are divided into the following two categories based on P-PC: q Parts:

[0085]

[0086] in This represents the LLR subsequence corresponding to the k-th P-PC, while Indicates corresponding to The codeword estimation subsequence.

[0087] In order to obtain the codeword estimation sequence of the source node in formula (1) The LLR sequence of the source node needs to be calculated. The formula is as follows:

[0088]

[0089] Then use Decode the source node to obtain the estimated codeword sequence of the source node.

[0090] Furthermore, regarding S3, in this embodiment, it should be noted that if the source node has a special structure, it is calculated using the fast decoding algorithm corresponding to that node. If the source node has only a general structure, then it can be calculated using the traditional serial cancellation decoding algorithm.

[0091] In operation S4, the dual check and candidate flip positions for each P-PC are determined as follows:

[0092]

[0093]

[0094] Where γ P-PC [k] and η[k] represent the dual parity check and candidate flipped bit corresponding to the k-th P-PC, respectively. According to γ P-PC [k] and η[k] are used to perform bit flipping on the estimated codeword sequence:

[0095]

[0096] In operation S5, the LLR and estimated codeword sequences of the SR1 / SPC nodes are divided into the following two categories based on S-PC: p-q Each block:

[0097]

[0098] Where (k-1)2 q +1 to k2 q The bits form a block, and k represents the block index. Let represent the LLR subsequence of the k-th block, and Indicates corresponding to The codeword estimation subsequence.

[0099] Define γ S-PC [1:pq] is the dual parity check sequence of the S-PC, which can be calculated by the following formula:

[0100]

[0101] Introducing a set of flipped bit pairs When the dual parity sequence does not contain 1 Otherwise, construct according to suboperation S51-suboperation S55.

[0102] In suboperation S51, for Perform initialization. Specifically, in conjunction with... Figure 4 Let t be such that γ S-PC The smallest index value where [t] = 1, if the circular index k ≤ 2 t-1 Construct ε = {k, k+2} t-1}, and towards Add ε to the loop index k and increment the loop index k by 1; when k = 2 t-1 +1, end The initialization operation ends; otherwise, continue executing the loop steps in sub-operation S51.

[0103] In sub-operation S52, depending on the situation, [the following is applied]... Continue adding elements. Specifically, combine... Figure 4 Increment the cycle index t by 1, and let W be the value of the current set. The total number of elements in the data is specifically: If γ S-PC [t] = -1, execute suboperation S53; if γ S-PC If [t] = 0, execute suboperation S54; if γ S-PC When [t] = 1, execute suboperation S55; when t = pq, output... Otherwise, continue executing the loop steps in suboperation S52.

[0104] In suboperation S53, when γ S-PC When [t] = -1, the direction is... Continue adding elements. Specifically, combine... Figure 4 If the cycle index ω≤W, choose Given the ω-th element ε = {k1, k2}, construct four new elements: ε1 = {k1, k2}, ε2 = {k1 + 2}. t-1 k2+2 t-1},ε3={k1+2 t-1 ,k2},ε4={k1,k2+2 t-1}, and add these four new elements into In the loop, the value of the loop index ω is incremented by 1; the loop ends when ω = W + 1. The initialization operation ends; otherwise, return to sub-operation S52.

[0105] In suboperation S54, when γ S-PC When [t] = 0, towards Continue adding elements. Specifically, combine... Figure 4 If the cycle index ω≤W, choose Given the ω-th element ε = {k1, k2}, construct two new elements: ε1 = {k1, k2}, ε2 = {k1 + 2}. t-1 k2+2 t-1}, and add these two new elements into In the loop, the value of the loop index ω is incremented by 1; the loop ends when ω = W + 1. The initialization operation ends; otherwise, return to sub-operation S52.

[0106] In suboperation S54, when γ S-PC When [t] = 1, towards Continue adding elements. Specifically, combine... Figure 4 If the cycle index ω≤W, choose Given the ω-th element ε = {k1, k2}, construct four new elements: ε1 = {k1 + 2} t-1 ,k2},ε2={k1,k2+2 t-1}, and add these two new elements into In the loop, the value of the loop index ω is incremented by 1; the loop ends when ω = W + 1. The initialization operation ends; otherwise, return to sub-operation S52.

[0107] Introduce a metric λ for bit pairs ε. ε The calculation of the measurement is specifically manifested as follows:

[0108]

[0109] In operation S6, the bit pair ε with the smallest metric is selected. opt Specifically:

[0110]

[0111] According to ε opt The estimated codeword sequence is bit-flipped, and the specific operation is as follows:

[0112]

[0113] The estimated codeword sequence after the flipping is completed is the final decoding result.

[0114] Figure 5 , 6The theoretical time delay and error correction performance of the fast successive cancellation decoding algorithm for special nodes of polar codes are compared with those of the traditional successive cancellation decoding algorithm. Specifically, combined with... Figure 5 FSSC decoding considers special node types including Rate-0, Rate-1, REP, and SPC. HFSC1, based on FSSC decoding, additionally considers the special node Type IV. HFSC2, based on HFSC1 decoding, additionally considers the special nodes SR0 / REP. SN-FSC, based on HFSC1 decoding, additionally considers the proposed special nodes SR1 / SPC. At various code lengths and rates, the decoding algorithms incorporating these special nodes can further reduce decoding latency. Figure 6 With a code length of N=1024, the SN-FSC decoding algorithm suffers almost no performance loss.

[0115] The present invention proposes a fast continuous cancellation decoding method for special nodes of polar codes. Firstly, the present invention proposes a novel type of special node with higher parallelism. Secondly, for the proposed special nodes, the present invention proposes a fast continuous cancellation decoding algorithm. The proposed decoding algorithm considers the dual constraints contained in the nodes and can greatly reduce decoding latency without sacrificing error correction performance.

[0116] Figure 7 This is a schematic diagram of a fast continuous cancellation decoding device for special nodes of polar codes provided in an embodiment of the present invention.

[0117] like Figure 7 As shown, the fast continuous cancellation decoding device for special nodes of the polar code includes: an acquisition module 100, a decision module 200, a first verification module 300, and a second verification module 400, wherein...

[0118] The acquisition module is used to determine the special nodes in the target decoding tree of continuous cancellation decoding based on the distribution of polar code information bits and frozen bits. The special nodes include the first dual constraint and the second dual constraint.

[0119] The decision module is used to make hard decisions on the log-likelihood ratio sequence of special nodes to obtain the first estimated codeword sequence;

[0120] The first verification module is used to calculate the verification value of the first dual constraint, and flip the bit estimation values ​​in the first estimated codeword sequence according to the verification value of the first dual constraint to obtain the second estimated codeword sequence.

[0121] The second verification module is used to calculate the verification value of the second dual constraint, construct a set of flipped bit pairs based on the verification value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimate value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

[0122] To achieve the above objectives, a third aspect of the present invention provides a computer device, characterized in that it includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the fast continuous cancellation decoding method for special nodes of polar codes as described above.

[0123] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the fast continuous cancellation decoding method for special nodes of polar codes as described above.

[0124] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0125] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0126] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A fast successive cancellation decoding method for special nodes of polar codes, characterized in that, Includes the following steps: Based on the distribution of polar code information bits and frozen bits, special nodes in the target decoding tree for continuous cancellation decoding are determined, and the special nodes include the first dual constraint and the second dual constraint. A hard decision is made on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence; Calculate the check value of the first dual constraint, and flip the bit estimates in the first estimated codeword sequence according to the check value of the first dual constraint to obtain the second estimated codeword sequence; Calculate the check value of the second dual constraint, construct a set of flipped bit pairs based on the check value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimate value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

2. The method according to claim 1, characterized in that, The special node is a polar code that includes a source node and a sequence of code rate one or single even parity check code sub-nodes.

3. The method according to claim 1, characterized in that, The step of making a hard decision on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence includes: When the log-likelihood ratio is greater than 0, the hard decision result is 0; otherwise, the hard decision result is 1.

4. The method according to claim 1, characterized in that, The calculation of the verification value of the first dual constraint includes: Calculate the log-likelihood ratio sequence of the source nodes in the special nodes, and decode the source nodes according to the log-likelihood ratio sequence to obtain the source node estimated codeword sequence; The check value of the first dual constraint is calculated based on the codeword sequence estimated from the source node.

5. The method according to claim 4, characterized in that, The obtained source node estimated codeword sequence includes: If the source node has a special structure, the estimated codeword sequence of the source node can be calculated using the fast decoding algorithm corresponding to the source node; If the source node has a general structure, the estimated codeword sequence of the source node can be calculated using the traditional serial cancellation decoding algorithm.

6. The method according to claim 1, characterized in that, The step of flipping the bit estimates in the first estimated codeword sequence based on the check value of the first dual constraint includes: If the codeword sequence already satisfies the first type of duality check value, then no bit flipping operation is performed; If the codeword sequence does not satisfy the first type of duality check value, then the bit with the smallest absolute log-likelihood ratio is bit-flipped.

7. The method according to claim 1, characterized in that, The step of constructing a set of flipped bit pairs based on the check value of the second dual constraint includes: The set is generated offline.

8. A fast successive cancellation decoding device for special nodes of polar codes, characterized in that, Includes the following modules: The acquisition module is used to determine special nodes in the target decoding tree of continuous cancellation decoding based on the distribution of polar code information bits and frozen bits. The special nodes include a first dual constraint and a second dual constraint. The decision module is used to make a hard decision on the log-likelihood ratio sequence of the special node to obtain the first estimated codeword sequence; The first verification module is used to calculate the verification value of the first dual constraint, and flip the bit estimation values ​​in the first estimated codeword sequence according to the verification value of the first dual constraint to obtain the second estimated codeword sequence. The second verification module is used to calculate the verification value of the second dual constraint, construct a set of flipped bit pairs based on the verification value of the second dual constraint, select the bit pair with the smallest metric in the set, flip the bit estimation value of the corresponding position of the bit pair in the second estimated codeword sequence, and obtain the target estimated codeword sequence.

9. A computer device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the fast successive cancellation decoding method for special nodes of polar codes as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the fast continuous cancellation decoding method for special nodes of polar codes as described in any one of claims 1-7.

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