A universal clock management system and method for multiple Ethernet interface modes

Abstract

The invention discloses a universal clock management system and method for multiple Ethernet interface modes, comprising a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a MUX_4 module, a MUX_6 module and a MUX_7 module. The clock signals in various interface modes are multiplexed and bidirectional pins are set, thereby reducing the number of signals. The interface is made clearer by separating the receiving and sending paths. The user only needs to select the port mode and the working frequency according to his / her needs, and the structure will automatically switch to the clock frequency adapted thereto. The universal clock management method effectively solves the problems of complex clock structure, multiple interface signals and difficulty in use by users. At the same time, the convergence of physical realization timing is guaranteed by separating the clock path and the data path in two working modes of the RGMII interface.

Description

Technical Field

[0001] The invention belongs to the field of computer communication and network, and in particular to a universal clock management system and method for multiple Ethernet interface modes. Background Art

[0002] Currently, in mainstream Ethernet switching chips, in order to facilitate user use, their management ports support multiple interface modes, such as GMII / MII / RGMII / RvMII, etc. In order to achieve better adaptation with the other end, the RGMII interface supports both nomal and delay modes. Since each interface mode has a separate working rate and clock frequency, its clock structure is complex, the interface signals are numerous, and it is not easy for users to use. The two working modes of the RGMII interface have different timing requirements, which makes it difficult to converge the physical implementation timing. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a universal clock management system and method for multiple Ethernet interface modes, which are used to solve the above problems.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A universal clock management system for multiple Ethernet interface modes, including a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a MUX_4 module, a MUX_6 module, and a MUX_7 module;

[0006] The output end of the PLL module is connected to the input end of the Devider module, the output end of the Devider module is connected to the input end of the MUX_1 module, the output end of the MUX_1 module is connected to the input end of the MUX_2 module; the input end of the MUX_2 module is connected to the bidirectional PAD circuit;

[0007] The MUX_2 module is used to switch the four interface modes of GMII / MII / RGMII / RvMII according to the control signal; the output end of the MUX_2 module is connected to the input end of the MAC module; the MAC module is used to perform sampling after the interface mode and rate selection;

[0008] For the receiving path, the RvMII interface mode in the MUX_2 module selects the clock frequency output by the MUX_1 module, and selects the external input IMP_RXCLK in the GMII / MII / RGMII interface modes. If it is the RGMII interface mode, select the clock frequency after the nomal and delay switching; the MUX_3 module is used to select IMP_RXCLK and imp_rxclk_d according to the IMP interface receiving delay mode control signal; the MUX_7 module is used to select the received data and control signal in the RGMII interface mode;

[0009] For the transmission path, the three interface modes of GMII / RGMII / RvMII in the MUX_2 module select the clock frequency output by the MUX_1 module, and the external input IMP_TXCLK in the MII interface mode. If it is the RGMII interface mode, select the clock frequency after the nomal and delay are switched;

[0010] The MUX_4 module is used to select the clock according to the delay mode control signal; the MUX_6 module is used to select the sending data and control signal according to the delay mode control signal.

[0011] Preferably, the PLL module is used to multiply the input 25 MHz clock by 10 to generate a 250 MHz clock for transmission to the Devider module.

[0012] Preferably, the Devider module is used to divide the clock output by the PLL module to generate three clocks of 125MHz / 25MHz / 2.5MHz.

[0013] Preferably, the MUX_1 module is used to select three clock frequencies of 125MHz / 25MHz / 2.5MHz after the Devider module divides the clock frequencies according to the control signal.

[0014] Preferably, a Delay module is further included, and the Delay module is used to delay the control signal.

[0015] Preferably, the MUX_3 module selects the clock imp_rxclk_d when the IMP_RXC_DELAY signal is 1, otherwise it selects the clock IMP_RXCLK.

[0016] Preferably, the MUX_4 module is used to select the clock according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface to generate the clock IMP_GTX_CLK; when the IMP_TXC_DELAY signal is 1, the clock after the delay module is selected, otherwise the clock generated by the MUX_1 module is selected.

[0017] Preferably, the MUX_6 module is used to select the transmission data and control signal according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface, and generate TXD[3:0] and TX_CTRL;

[0018] When the control signal IMP_TXC_DELAY is 0, the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module are selected. When the control signal IMP_TXC_DELAY is 1, the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module are selected.

[0019] Preferably, the MUX_7 module is used to select the received data and control signal according to the IMP interface receiving delay mode control signal IMP_RXC_DELAY, and generate mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module;

[0020] When the control signal IMP_RXC_DELAY is 1, the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module are selected. When the control signal IMP_RXC_DELAY is 0, the external input RXD[3:0] and RX_CTRL signals are selected.

[0021] A general clock management method for multiple Ethernet interface modes includes the following processes:

[0022] The PLL module multiplies the input clock and outputs it to the Devider module. The Devider module divides the clock output by the PLL module and transmits it to the MUX_1 module. The MUX_1 module selects the clock divided by the Devider module and transmits it to the MUX_2 module.

[0023] The MUX_2 module switches the four interface modes of GMII / MII / RGMII / RvMII according to the control signal; the MAC module is used to sample the clock and data after the four interface modes of GMII / MII / RGMII / RvMII and the 10 / 100 / 1000Mbps rate are selected;

[0024] For the receiving path, select the clock frequency output by the MUX_1 module in the RvMII interface mode, select the external input IMP_RXCLK in the GMII / MII / RGMII interface mode, and select the clock frequency after the nomal and delay are switched in the RGMII interface mode;

[0025] For the transmit path, select the clock frequency output by the MUX_1 module in the GMII / RGMII / RvMII interface modes, select the external input IMP_TXCLK in the MII interface mode, and select the clock frequency after switching between nomal and delay in the RGMII interface mode.

[0026] Compared with the prior art, the present invention has the following beneficial technical effects:

[0027] The present invention provides a universal clock management system for multiple Ethernet interface modes, which reduces the number of signals by multiplexing clock signals in various interface modes and setting bidirectional pins; the interface is made clearer by separating receiving and sending paths; the user only needs to select the port mode and operating frequency according to his own needs, and the structure will automatically switch to a clock frequency adapted thereto; for the two operating modes of the RGMII interface, in order to ensure the convergence of the physical implementation timing, a design structure that separates the clock path and the data path is adopted.

[0028] The invention discloses a universal clock management method for multiple Ethernet interface modes, supports various commonly used Ethernet interface modes, can realize clock switching under various working modes and rate combinations, and has simple, clear and small interface signals, and has high engineering application value. The invention simulates the function of the invention and compares it with the traditional Ethernet switching circuit structure. In the test environment, 1000 groups of messages are randomly generated, the port mode is switched to GMII / MII / RGMII / RvMII, the communication rate is switched to 10 / 100 / 1000Mbps, and the traditional Ethernet switching circuit structure and the universal clock management method proposed by the invention are respectively used to exchange and forward these message tasks; wherein, the number of ports is 7, the working clock is 2.5 / 25 / 125MHz, the data bit width is 8 bits, and a continuous data communication method is adopted. The simulation results show that the universal clock management method effectively solves the problems of complex clock structure, multiple interface signals, and difficulty for users to use; at the same time, by separating the clock path and the data path in the two working modes of the RGMII interface, the convergence of the physical implementation timing is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a clock structure diagram for the management port receiving path;

[0030] Figure 2 Send path clock structure diagram for management port;

[0031] Figure 3 The structure diagram of the clock and data isolation of the transmission path of the management port RGMII mode;

[0032] Figure 4This is a diagram of the clock and data isolation structure of the management port RGMII mode receive path. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.

[0034] Example

[0035] The present invention provides a universal clock management system for multiple Ethernet interface modes, which mainly includes a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a Delay module, a MUX_4 module, a MUX_5 module, a MUX_6 module, and a MUX_7 module. Its structure is as follows Figure 1 , Figure 2 , Figure 3 and Figure 4 shown; through Figure 1 and Figure 2 The structure realizes four interface modes of GMII / MII / RGMII / RvMII and pin multiplexing at 10 / 100 / 1000Mbps. If pin multiplexing is not performed, the GMII interface mode requires 3 clock signals, the MII interface mode requires 2 clock signals, the RGMII interface mode requires 3 clock signals, and the RvMII interface mode requires 2 clock signals, a total of 10 clock signals. After multiplexing, the four interface modes only require 3 clock signals. The multiplexed clock pin signals are shown in the following table:

[0036]

[0037] pass Figure 3 and Figure 4 The structure realizes the separation of the clock path and data path of the RGMII interface in normal and delay modes, thereby ensuring the convergence of the physical implementation timing.

[0038] exist Figure 3 In the nominal mode, the paths for sending data and control signals are the MAC module and the MUX_6 module, and the path for sending clock is the MUX_4 module; only the timing checks need to be performed on these two paths; in the delay mode, the paths for sending data and control signals are the MAC module, the Delay module, and the MUX_6 module, and the path for sending clock is the Delay module and the MUX_4 module; only the timing checks need to be performed on these two paths.

[0039] exist Figure 4In the nomal mode, the receiving data and control signal paths are the MUX_7 module and the MAC module, and the receiving clock path is the MUX_3 module; only the timing checks need to be performed on these two paths; in the delay mode, the receiving data and control signal paths are the Delay module, the MUX_7 module, and the MAC module, and the receiving clock path is the Delay module and the MUX_3 module; only the timing checks need to be performed on these two paths.

[0040] The main function of the PLL module is to multiply the input 25MHz clock by 10 and generate a 250MHz clock for the Devider module.

[0041] The Devider module mainly divides the clock output by the PLL module to generate three clocks: 125MHz / 25MHz / 2.5MHz. 125MHz corresponds to a communication rate of 1000Mbps, 25MHz corresponds to a communication rate of 100Mbps, and 2.5MHz corresponds to a communication rate of 10Mbps.

[0042] The MUX_1 module mainly selects the three clock frequencies of 125MHz / 25MHz / 2.5MHz after the Devider module is divided according to the control signal IMP_SPD_SEL[1:0]. IMP_SPD_SEL[1:0]: 00=10Mbps, select 2.5MHz working clock; 01=100Mbps, select 25MHz working clock; 10=1000Mbps (default), select 125MHz working clock; 11=lllegal.

[0043] The MUX_2 module mainly switches the four interface modes of GMII / MII / RGMII / RvMII according to the control signal IMP_MODE[1:0]. IMP_MODE[1:0]: 00 = RGMII mode, 01 = MII mode, 10 = RvMII mode, 11 = GMII mode.

[0044] For the receiving path, select the clock frequency output by the MUX_1 module in the RvMII interface mode, select the external input IMP_RXCLK (the direction of this bidirectional pin is input) in the GMII / MII / RGMII interface modes, and select the clock frequency after the nomal and delay are switched in the RGMII interface mode.

[0045] For the transmit path, select the clock frequency output by the MUX_1 module in the GMII / RGMII / RvMII interface modes, select the external input IMP_TXCLK (the direction of this bidirectional pin is input) in the MII interface mode, and select the clock frequency after the nomal and delay are switched in the RGMII interface mode.

[0046] The MAC module mainly implements the four interface modes of GMII / MII / RGMII / RvMII and the clock and data sampling after the 10 / 100 / 1000Mbps rate selection. For the receiving channel, if it works in the RGMII interface mode, the clock and data are switched according to the control signal IMP_RXC_DELAY.

[0047] The MUX_3 module mainly selects IMP_RXCLK and imp_rxclk_d according to the IMP interface receiving delay mode control signal IMP_RXC_DELAY. When the IMP_RXC_DELAY signal is 1, the clock imp_rxclk_d is selected, otherwise the clock IMP_RXCLK (the direction of this bidirectional pin is input) is selected, thereby realizing the separation of the receiving clock path of the RGMII interface in normal and delay modes.

[0048] The Delay module mainly implements the delay of IMP_GTX_CLK, TXD[3:0], TX_CTRL, IMP_RXCLK, RXD[3:0], RX_CTRL and other signals. The delay time granularity is based on the specific timing requirements, thereby realizing the path separation of the RGMII interface in delay mode.

[0049] The MUX_4 module mainly selects the clock according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface to generate the clock IMP_GTX_CLK. When the IMP_TXC_DELAY signal is 1, the clock after the delay module is selected, otherwise the clock generated by the MUX_1 module is selected, thereby realizing the separation of the sending clock path of the RGMII interface in normal and delay modes.

[0050] The MUX_5 module mainly implements the selection of the IMP_GTX_CLK clock in GMII and RGMII modes based on the control signal IMP_MODE[1:0]. IMP_MODE[1:0]: 00 = RGMII mode, select the clock generated by the MUX_4 module; 01 = MII mode; 10 = RvMII mode; 11 = GMII mode, select the 125MHz clock generated by the Devider module.

[0051] The MUX_6 module mainly selects the transmission data and control signals according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface, and generates TXD[3:0] and TX_CTRL. When the control signal IMP_TXC_DELAY is 0, the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module are selected. When the control signal IMP_TXC_DELAY is 1, the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module are selected; thus, the RGMII interface can separate the transmission data and control signal paths in the normal and delay modes.

[0052] The MUX_7 module mainly selects the received data and control signals according to the IMP interface receiving delay mode control signal IMP_RXC_DELAY, and generates mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module. When the control signal IMP_RXC_DELAY is 1, the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module are selected, and when the control signal IMP_RXC_DELAY is 0, the external input RXD[3:0] and RX_CTRL signals are selected; thus, the separation of the received data and control signal paths of the RGMII interface in normal and delay modes is realized.

[0053] The present invention reduces the number of signals by multiplexing clock signals in various modes and setting bidirectional pins; the interface is made clearer by separating the receiving and transmitting paths; the user only needs to select the port mode and the operating frequency according to his or her needs, and the structure will automatically switch to a clock frequency adapted thereto; for the two operating modes of the RGMII interface, the convergence of the physical implementation timing is ensured by a design structure that separates the clock path and the data path.

[0054] The invention discloses a universal clock management method for multiple Ethernet interface modes, supports various commonly used Ethernet interface modes, can realize clock switching under various working modes and rate combinations, has simple and clear interface signals, and has a small number, and has high engineering application value.

[0055] The invention is functionally simulated and compared with the traditional Ethernet switching circuit structure. In the test environment, 1000 groups of messages are randomly generated, the port mode is switched between GMII / MII / RGMII / RvMII, the communication rate is switched between 10 / 100 / 1000Mbps, and the traditional Ethernet switching circuit structure and the universal clock management method proposed by the invention are used to exchange and forward these message tasks; wherein, the number of ports is 7, the working clock is 2.5 / 25 / 125MHz, the data bit width is 8 bits, and a continuous data communication method is used. The simulation results show that the universal clock management method effectively solves the problems of complex clock structure, multiple interface signals, and difficulty for users to use; at the same time, by separating the clock path and data path in the two working modes of the RGMII interface, the convergence of the physical implementation timing is guaranteed.

[0056] The management port receiving path clock structure diagram of the present invention is as follows Figure 1 As shown in the figure, the clock structure diagram of the management port sending path is as follows Figure 2 As shown in Figure 1, the IMP_RXC_Delay and IMP_TXC_Delay signals are controlled by external input pins; the management port RGMII mode transmit path clock and data isolation structure is as follows Figure 3 As shown, the receiving path clock and data isolation structure is as follows Figure 4 shown.

[0057] The following is a description of the numbered modules in the figure:

[0058] Module No. 1 is a PLL module, and its quantity is 2. Figure 1 and Figure 2 Multiplexing. It mainly realizes 10 times the input 25MHz clock to generate a 250MHz clock.

[0059] Module No. 2 is the Devider module, and its quantity is 2. Figure 1 and Figure 2 Multiplexing. It mainly realizes the frequency division of the clock output by module 1 to generate three types of clocks: 125MHz / 25MHz / 2.5MHz.

[0060] Module No. 3 is MUX_1 module, the number of which is 2. Figure 1 and Figure 2 Multiplexing. The three clocks of 125MHz / 25MHz / 2.5MHz are selected mainly according to the IMP_SPD_SEL[1:0] signal.

[0061] Module No. 4 is MUX_2 module, and its quantity is 2. Figure 1 and Figure 2Multiplexing. The four interface modes of GMII / MII / RGMII / RvMII are switched mainly according to the IMP_MODE[1:0] signal.

[0062] Module No. 5 is a MAC module, and its quantity is 4. Figure 1 , Figure 2 , Figure 3 and Figure 4 Multiplexing. Mainly implements sampling after interface mode and rate selection.

[0063] Module No. 6 is a MUX_3 module, and its quantity is 2. Figure 1 and Figure 4 Multiplexing. The selection of IMP_RXCLK and imp_rxclk_d is mainly based on the IMP_RXC_DELAY signal.

[0064] Module No. 7 is a Delay module, and its quantity is 6. Figure 1 , Figure 2 , Figure 3 and Figure 4 Multiplexing. Mainly realizes the delay of IMP_GTX_CLK, TXD[3:0], TX_CTRL, IMP_RXCLK, RXD[3:0], RX_CTRL and other signals.

[0065] Module No. 8 is a MUX_4 module, and its quantity is 2. Figure 2 and Figure 3 Multiplexing. The clock is selected mainly based on the IMP_TXC_DELAY signal to generate IMP_GTX_CLK.

[0066] Module No. 9 is the MUX_5 module, and its quantity is 1. It mainly realizes the selection of IMP_GTX_CLK clock in GMII and RGMII modes.

[0067] Module No. 10 is a MUX_6 module, and its quantity is 1. It mainly implements the selection of sending data and control signals according to the IMP_TXC_DELAY signal, and generates TXD[3:0] and TX_CTRL.

[0068] Module No. 11 is a MUX_7 module, and its quantity is 1. It mainly implements the selection of RXD[3:0], RX_CTRL and rxd_d[3:0], rx_ctrl according to the IMP_RXC_DELAY signal, and generates mac_rxd[3:0] and mac_rx_ctrl signals to module No. 5.

[0069] The invention can be used in the design of Ethernet switching chips in the fields of Ethernet switches, network servers, computer data storage systems, etc.

[0070] Currently, in mainstream Ethernet switching chips, in order to facilitate user use, their management ports support multiple interface modes, such as GMII / MII / RGMII / RvMII, etc. In order to achieve better adaptation with the other end, the RGMII interface supports both nomal and delay modes. Since each interface mode has a separate working rate and clock frequency, its clock structure is complex, the interface signals are numerous, and it is not easy for users to use. The two working modes of the RGMII interface have different timing requirements, which makes it difficult to converge the physical implementation timing.

[0071] A universal clock management method for multiple Ethernet interface modes proposed in the present invention is adopted, and the number of signals is reduced by multiplexing the clock signals in various modes and setting bidirectional pins; the interface is made clearer by separating the receiving and sending paths; the user only needs to select the port mode and the operating frequency according to his own needs, and the structure will automatically switch to the clock frequency adapted thereto; for the two operating modes of the RGMII interface, in order to ensure the convergence of the physical implementation timing, a design structure that separates the clock path and the data path is adopted.

[0072] According to the above scheme, the logic design of each module in the present invention is described in Verilog language, and it is verified at the system level with other devices in the network device. The verification results show that the present invention realizes the design function and the performance meets expectations.

Claims

1. A universal clock management system for multiple Ethernet interface modes, characterized in that: Including PLL module, Devider module, MUX_1 module, MUX_2 module, MAC module, MUX_3 module, MUX_4 module, MUX_6 module, MUX_7 module; The output end of the PLL module is connected to the input end of the Devider module, the output end of the Devider module is connected to the input end of the MUX_1 module, the output end of the MUX_1 module is connected to the input end of the MUX_2 module; the input end of the MUX_2 module is connected to the bidirectional PAD circuit; The MUX_2 module is used to switch the four interface modes of GMII / MII / RGMII / RvMII according to the control signal; the output end of the MUX_2 module is connected to the input end of the MAC module; the MAC module is used to perform sampling after the interface mode and rate selection; For the receiving path, the RvMII interface mode in the MUX_2 module selects the clock frequency output by the MUX_1 module, and selects the external input IMP_RXCLK in the GMII / MII / RGMII interface modes. If it is the RGMII interface mode, select the clock frequency after the nomal and delay switching; the MUX_3 module is used to select IMP_RXCLK and imp_rxclk_d according to the IMP interface receiving delay mode control signal; the IMP_RXCLK is a bidirectional pin for external input; the imp_rxclk_d is the output of the IMP_RXCLK after the delay mode; The MUX_7 module is used to select received data and control signals in RGMII interface mode; For the transmission path, the three interface modes of GMII / RGMII / RvMII in the MUX_2 module select the clock frequency output by the MUX_1 module, and the external input IMP_TXCLK in the MII interface mode. If it is the RGMII interface mode, select the clock frequency after the nomal and delay are switched; The MUX_4 module is used to select the clock according to the delay mode control signal; the MUX_6 module is used to select the transmission data and control signal according to the delay mode control signal; The PLL module is used to multiply the input 25MHz clock by 10 to generate a 250MHz clock and transmit it to the Devider module; The Devider module is used to divide the clock output by the PLL module to generate three clocks of 125MHz / 25MHz / 2.5MHz; The MUX_1 module is used to select the three clock frequencies of 125MHz / 25MHz / 2.5MHz after the Devider module divides the clock frequency according to the control signal; The MUX_6 module is used to select the transmission data and control signal according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface, and generate TXD[3:0] and TX_CTRL; When the control signal IMP_TXC_DELAY is 0, the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module are selected; when the control signal IMP_TXC_DELAY is 1, the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module are selected; The MUX_7 module is used to select the received data and control signal according to the IMP interface receiving delay mode control signal IMP_RXC_DELAY, and generate mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module; When the control signal IMP_RXC_DELAY is 1, the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module are selected. When the control signal IMP_RXC_DELAY is 0, the external input RXD[3:0] and RX_CTRL signals are selected. The MUX_4 module is used to select the clock according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface to generate the clock IMP_GTX_CLK; when the IMP_TXC_DELAY signal is 1, the clock after the delay module is selected, otherwise the clock generated by the MUX_1 module is selected.

2. A universal clock management system for multiple Ethernet interface modes according to claim 1, characterized in that: It also includes a Delay module, and the Delay module is used to delay the control signal.

3. A universal clock management system for multiple Ethernet interface modes according to claim 1, characterized in that: The MUX_3 module selects the clock imp_rxclk_d when the IMP_RXC_DELAY signal is 1, otherwise it selects the clock IMP_RXCLK.

4. A method for managing a universal clock management system for multiple Ethernet interface modes according to any one of claims 1 to 3, characterized in that: Including the following process, The PLL module multiplies the input clock and outputs it to the Devider module. The Devider module divides the clock output by the PLL module and transmits it to the MUX_1 module. The MUX_1 module selects the clock divided by the Devider module and transmits it to the MUX_2 module. The MUX_2 module switches the four interface modes of GMII / MII / RGMII / RvMII according to the control signal; the MAC module is used to sample the clock and data after the four interface modes of GMII / MII / RGMII / RvMII and the 10 / 100 / 1000Mbps rate are selected; For the receiving path, select the clock frequency output by the MUX_1 module in the RvMII interface mode, select the external input IMP_RXCLK in the GMII / MII / RGMII interface modes, and select the clock frequency after the nomal and delay are switched in the RGMII interface mode; For the transmit path, select the clock frequency output by the MUX_1 module in the GMII / RGMII / RvMII interface modes, select the external input IMP_TXCLK in the MII interface mode, and select the clock frequency after switching between nomal and delay in the RGMII interface mode.

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