Avalon protocol conversion method, device, equipment and medium

Abstract

The present application discloses an Avalon protocol conversion method, device, equipment and medium, which are applied to the field of bus protocol conversion technology, including: configuring the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number; receiving the data on the Avalon-ST bus through the unpacker, if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module; the controller reads the data from the data cache module, and transmits the data to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory. It can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is conducive to the system-level interconnection, development, maintenance and upgrade of the algorithm module.

Description

Technical Field

[0001] The present application relates to the technical field of bus protocol conversion, and in particular to an Avalon protocol conversion method, device, equipment and medium. Background Art

[0002] At present, heterogeneous acceleration usually uses FPGA to help CPU perform calculations, and the FPGA algorithm module writes the calculated data into storage. The existing technical solutions usually use two buses separately according to specific business needs, and there is no more universal conversion design. Figure 1 As shown, Figure 1 A schematic diagram is written for the FPGA algorithm module data in the prior art. The data calculated by the FPGA algorithm module needs to be written into the RAM using the RAM original interface, or written into the DDR using the Avalon-MM bus interface. Generally, the algorithm module interface is a ready / valid handshake signal (Avalon-ST protocol simplified version), so the algorithm core needs to perform calculations and control at the same time. In summary, the prior art has the following defects: specific business needs are analyzed specifically, and designers implement transformations based on the needs, which is not flexible and general enough. In addition, control and calculation are not separated, and the coupling is extremely high, which is not conducive to system-level interconnection, development, maintenance and upgrading. Summary of the invention

[0003] In view of this, the purpose of this application is to provide an Avalon protocol conversion method, device, equipment and medium, which can ensure the universality of FPGA algorithm modules writing data to storage, and realize the separation of writing data to storage and calculation, which is conducive to the system-level interconnection, development, maintenance and upgrading of algorithm modules. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses an Avalon protocol conversion method, comprising:

[0005] Configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number;

[0006] Receiving data on the Avalon-ST bus through a depacketizer, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data in a data cache module;

[0007] The controller reads the data from the data cache module and transmits the data to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into the memory.

[0008] Optionally, also include:

[0009] If the channel number of the channel to which the data belongs is inconsistent with the Avalon-ST bus channel number, the data is directly discarded.

[0010] Optionally, storing the data in a data cache module includes:

[0011] Storing the data in FIFO;

[0012] Correspondingly, reading the data from the data cache module through the controller includes: reading the data from the FIFO through the controller.

[0013] Optionally, also include:

[0014] If the FIFO is full, the reception of data on the Avalon-ST bus is suspended.

[0015] Optionally, configuring the Avalon-ST bus channel number includes:

[0016] Configure the Avalon-ST bus channel number to the first register.

[0017] Optionally, also include:

[0018] Configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively;

[0019] The controller calculates a write burst address and a burst length based on the write address initial address and the write data length, and transmits the data and the write burst address and the burst length to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

[0020] Optionally, the Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

[0021] Optionally, configuring the Avalon-ST bus channel number to the first register through the APB bus, and configuring the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register respectively, includes:

[0022] The Avalon-ST bus channel number is configured to the first register through the APB bus using the CPU, and the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

[0023] Optionally, also include:

[0024] When a wait request signal sent by the Avalon-MM bus slave module is received and the wait request signal indicates that the Avalon-MM bus slave module is currently busy, the sending of the data is suspended.

[0025] Optionally, also include:

[0026] Configure the preset Avalon-ST to Avalon-MM module's work trigger register to start the controller and the depacketizer to work;

[0027] Set the working status characterization register to the working state.

[0028] Optionally, the first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer and the data cache module all belong to a preset Avalon-ST to Avalon-MM module.

[0029] Optionally, the preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

[0030] In a second aspect, the present application discloses an Avalon protocol conversion device, comprising:

[0031] The configuration module is used to configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number;

[0032] A depacketizer, configured to receive data on the Avalon-ST bus, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, store the data in a data cache module;

[0033] The controller is used to read the data from the data cache module and transmit the data to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into the memory.

[0034] Optionally, the depacketizer is further configured to directly discard the data if the channel number of the channel to which the data belongs is inconsistent with the channel number of the Avalon-ST bus.

[0035] Optionally, the depacketizer is specifically used to store the data into the FIFO; correspondingly, the controller is specifically used to read the data from the FIFO.

[0036] Optionally, the depacketizer is further configured to suspend receiving data on the Avalon-ST bus if the FIFO is full.

[0037] Optionally, the configuration module is specifically used to configure the Avalon-ST bus channel number to the first register.

[0038] Optionally, the configuration module is further used to configure the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register respectively;

[0039] Correspondingly, the controller is used to calculate the write burst address and the burst length based on the write address initial address and the write data length, and transmit the data and the write burst address and the burst length to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

[0040] Optionally, the configuration module is specifically used to configure the Avalon-ST bus channel number to the first register through the APB bus, and configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0041] Optionally, the configuration module is a CPU, and the CPU is used to configure the Avalon-ST bus channel number to the first register through the APB bus, and configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0042] Optionally, the controller is further configured to suspend sending the data when receiving a wait request signal sent by the Avalon-MM bus slave module and the wait request signal indicates that the Avalon-MM bus slave module is currently busy.

[0043] Optionally, the configuration module is further used to configure a preset working trigger register of the Avalon-ST to Avalon-MM module so as to start the controller and the depacketizer to work; and set the working status characterization register to a working state.

[0044] Optionally, the first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer and the data cache module all belong to a preset Avalon-ST to Avalon-MM module.

[0045] Furthermore, the preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

[0046] In a third aspect, the present application discloses an electronic device, characterized in that it includes a storage unit and a processing unit, wherein:

[0047] The storage unit is used to store the computer program;

[0048] The processing unit is used to execute the computer program to implement the aforementioned Avalon protocol conversion method.

[0049] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program implements the aforementioned Avalon protocol conversion method when executed by a processor.

[0050] It can be seen that the present application configures the Avalon-ST bus channel number, the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number, and receives the data on the Avalon-ST bus through the depacketizer. If the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. That is, the present application configures the Avalon-ST bus channel number of the channel through which the FPGA algorithm module transmits data, receives data on the Avalon-ST bus through a depacketizer, and when the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, stores the data in a data cache module, reads the data from the data cache module through a controller, and transmits the data to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. In this way, the Avalon-ST bus protocol is converted to the Avalon-MM bus protocol, and the data calculated by the algorithm module is written to the storage, rather than letting the algorithm module itself control the writing. This can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is beneficial to the system-level interconnection, development, maintenance and upgrading of the algorithm module. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0052] Figure 1 Write a schematic diagram for the FPGA algorithm module data in the prior art;

[0053] Figure 2 A flow chart of an Avalon protocol conversion method disclosed in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of a specific Avalon-ST to Avalon-MM module disclosed in an embodiment of the present application;

[0055] Figure 4 A schematic diagram of a specific application scenario of converting the Avalon-ST protocol to Avalon-MM disclosed in an embodiment of the present application;

[0056] Figure 5 A schematic diagram of the structure of an Avalon protocol conversion device disclosed in an embodiment of the present application;

[0057] Figure 6 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] First, the terms involved in this application are explained:

[0060] FPGA: Field Programmable Gate Arrays, field programmable gate array;

[0061] IC: Integrated Circuit, commonly known as chip;

[0062] FIFO: First-in, first-out storage;

[0063] DDR: Double Data Rate Synchronous Dynamic Random Access Memory, a type of memory;

[0064] RAM: Random Access Memory, random access memory;

[0065] Pcie: peripheral component interconnect express is a high-speed serial computer expansion bus standard;

[0066] ASIC (Application Specific Integrated Circuit) is a special integrated circuit;

[0067] Avalon bus: This bus was proposed by Intel and is commonly used in Intel FPGA system design for high-speed data stream transmission, reading and writing registers, memories, and control of off-chip devices;

[0068] Avalon-Stream: also known as Avalon-ST or AVST, Avalon bus stream mode, simple protocol, supports unidirectional data flow, no address line, generally used in high-bandwidth and low-latency scenarios;

[0069] Avalon-Memory Map: also known as Avalon-MM or AVMM, with address lines, generally used for read and write operations of status registers and control registers; supports burst mode, mainly used for large-scale data movement in burst mode, and has complex protocols;

[0070] APB (Advanced Peripheral Bus): means peripheral bus. This bus protocol is one of the AMBA bus structures proposed by ARM and has almost become a standard on-chip bus structure.

[0071] With the popularization and application of technologies such as AI, big data, 5G, and deep learning, Internet server tasks are becoming more and more serious. CPU performance is no longer sufficient to support various video and image business needs. Heterogeneous acceleration has become an effective solution. Heterogeneous acceleration usually uses FPGA to help CPU calculate and share the CPU's work pressure. In the FPGA design process, module connection and system interconnection are often required, which requires a standard bus, but the same bus also has protocols that use different requirements. The existing technical solutions usually use two buses according to specific business needs, and there is no more universal conversion design. The data calculated by the FPGA algorithm module needs to be written to RAM using the RAM original interface, or written to DDR using the Avalon-MM bus interface. Generally, the algorithm module interface is ready / valid handshake signal (Avalon-ST protocol simplified version), so the algorithm core needs to do calculations and control at the same time. In summary, the existing technology has the following defects: they are all specific business needs for specific analysis, and designers implement conversion according to needs, which is not flexible and universal. In addition, control and calculation are not separated, and the coupling is extremely high, which is not conducive to system-level interconnection, development, maintenance and upgrading. To this end, this application provides an Avalon protocol conversion solution that can ensure the universality of FPGA algorithm modules writing data to storage, and realize the separation of writing data to storage and calculation, which is conducive to the system-level interconnection, development, maintenance and upgrading of algorithm modules.

[0072] See also Figure 2 As shown, the embodiment of the present application discloses an Avalon protocol conversion method, including:

[0073] Step S11: configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number.

[0074] It is understandable that the FPGA algorithm module is a module based on FPGA that uses a preset algorithm to calculate data, and the preset algorithm corresponds to a computing task. For example, if the computing task is an encryption and decryption task, the preset algorithm is an encryption and decryption algorithm, and if the computing task is an image processing task, the preset algorithm is an image processing algorithm.

[0075] In one implementation, the Avalon-ST bus channel number can be configured into the first register.

[0076] Step S12: receiving data on the Avalon-ST bus through the depacketizer, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data in a data cache module.

[0077] In a specific implementation manner, if the channel number of the channel to which the data belongs is inconsistent with the Avalon-ST bus channel number, the data is directly discarded.

[0078] Step S13: reading the data from the data cache module through a controller, and transmitting the data to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into a memory.

[0079] In one implementation, the data may be stored in a FIFO, and the data may be read from the FIFO by a controller. If the FIFO is full, the reception of data on the Avalon-ST bus is suspended. That is, the data buffer module is a FIFO.

[0080] Furthermore, when a wait request signal sent by the Avalon-MM bus slave module is received and the wait request signal indicates that the Avalon-MM bus slave module is currently busy, the sending of the data is suspended.

[0081] Furthermore, the embodiment of the present application can configure the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register respectively; calculate the write burst address and the burst length based on the write address initial address and the write data length through the controller, and transmit the data and the write burst address and the burst length to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory based on the write burst address and the burst length.

[0082] In addition, the embodiment of the present application can configure a preset Avalon-ST to Avalon-MM module work trigger register to start the controller and the depacketizer to work, and set the work status characterization register to the working state. And after the data writing is completed, the work status characterization register is set to the idle state.

[0083] Among them, after configuring the working trigger register, the depacketer waits for data on the AVST bus. If the channel number does not match, it will be discarded directly after receiving. If the channel number matches, it will start receiving after receiving the startofpacket signal until the endofpacket signal is received. The ready / valid handshake signal protocol needs to be followed in this process. The received valid data is written into the FIFO. If the FIFO is full during this process, it is necessary to suspend receiving the AVST bus data and suspend writing the data into the FIFO. In addition, after configuring the working trigger register, the controller takes out the data through the FIFO, and passes the burst address, burst length and data to the slave module. When the Avmm_waitrequest signal transmitted from the slave module is obtained to be high, it means that the slave module is busy and the transmission is suspended. When it is low, it means that it is idle and the burst address, burst length and data can be sent. After the AVMM bus write transmission is completed, the working status characterization register is set to the idle state low, indicating that the module is idle.

[0084] In one embodiment, the Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and write data length of the Avalon-MM bus are configured to the second register and the third register respectively, and the working trigger register and working status characterization register of the preset Avalon-ST to Avalon-MM module are configured.

[0085] Furthermore, the Avalon-ST bus channel number is configured to the first register by using the CPU and the APB bus, and the write address initial address and write data length of the Avalon-MM bus are configured to the second register and the third register respectively. And the preset Avalon-ST to Avalon-MM module work trigger register and work status characterization register are configured. Among them, the CPU can be the CPU inside the FPGA or the external CPU. The external CPU schedules data through the pcie Bar space mechanism. The internal CPU can be the ARM hard core embedded in the FPGA, or it can be a soft core built with logic in the FPGA.

[0086] Furthermore, the first register, the second register, the third register, the work trigger register, the work status characterization register, the unpacker and the data cache module all belong to the preset Avalon-ST to Avalon-MM module. The preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via the Avalon-MM bus. It should be pointed out that both Avalon-ST and Avalon-MM are part of the Avalon bus, but they cannot be directly interconnected. This application designs a general Avalon-ST protocol to Avalon-MM protocol module. The Avalon-MM protocol is converted to the Avalon-ST protocol, and the data calculated by the algorithm module is written into the data in RAM or DDR by using the internal CPU of the FPGA or the external CPU to schedule data, instead of letting the algorithm module itself control the writing.

[0087] The aforementioned Avalon-MM bus slave module is a slave module corresponding to the preset Avalon-ST to Avalon-MM module, which is a preset Avalon-MM bus interconnection module. The preset Avalon-MM bus interconnection module writes data into DDR or RAM through a DDR controller or a RAM controller. Relative to the preset Avalon-MM bus interconnection module, the DDR controller or the RAM controller is a slave module.

[0088] For example, see Figure 3 As shown, Figure 3 A specific Avalon-ST to Avalon-MM module schematic diagram provided for an embodiment of the present application. The Avalon-ST to Avalon-MM module includes registers, FIFOs, depacketizers, and APB bus, Avalon-MM bus, Avalon-ST bus interface and other modules. The registers are configured via the APB bus, where the register list is shown in Table 1, where R / W stands for readable and writable, WT stands for write trigger, and RO stands for read-only.

[0089] Table 1

[0090]

[0091] Among them, the depacketizer will be responsible for receiving data on the Avalon-ST bus, depacketizing the data, extracting valid data, and putting the valid data into the FIFO, which is used to temporarily store the depacketized data. The controller is responsible for calculating the burst write address (avmm_waddr) and burst length (avmm_burstcount) of each Avalon-MM bus based on the initial write address and write data length, and controlling the behavior of the Avalon-MM bus. When the register start is triggered, the controller passes the burst write address and burst length to the slave module through the avmm_write signal (i.e. write signal), and transmits the data in the RAM or DDR back through the avmm_writedata signal (i.e. write data signal) and the avmm_beginburst signal (i.e. start burst signal). When the Avmm_waitrequest signal (i.e. the busy status characterization signal of the slave module) is high, it means that the slave module is busy and the handshake is invalid. When data starts to be transmitted to the slave module, the avst_startofpacket signal is enabled. When data transmission ends, the avst_endofpacket signal is enabled. avst_channle represents the channel number, which can be configured according to the register channel. avst_valid and avst_ready are transmission handshake signals, and avst_data represents data. i_psel, i_paddr, i_penable, i_pwrite, i_pwdata, o_prdata, and o_pready are all signals designed based on the APB protocol and are used to configure registers.

[0092] The operation steps of the Avalon-ST to Avalon-MM module are as follows: 1. Configure the three registers, write_addr, write_length, and channel, through the APB bus to tell the module which address on the Avalon-MM bus to start writing data, how much data to write, and which channel on the Avalon-ST bus to get the data from. 2. Write the register start on the APB bus to notify the module to start working. After the module works, the register status is set high. 3. After receiving the start, the depacketizer waits for data on the AVST bus. If the channel number does not match, it will be discarded directly after receiving it. If the channel number matches, it will start receiving after receiving the startofpacket signal until the endofpacket signal is received. The ready / valid handshake signal protocol needs to be followed during this process. The received valid data is written into the FIFO. If the FIFO is full during this process, it is necessary to suspend receiving the Avalon-ST bus data and suspend writing the data into the FIFO. 4. When the register start is triggered, the controller module takes out the data through the FIFO, and passes the address, burst length and data to the slave module. The slave module notifies the master module whether to receive through the Avmm_waitrequest signal. When it is high, it means the slave module is busy and the master stops sending. When it is low, it means it is idle and can send the address, burst length and data. 5. After the Avalon-MM bus write transfer is completed, the register status is set low, indicating that the module is idle.

[0093] For further information, see Figure 4 As shown, Figure 4A schematic diagram of a specific application scenario of Avalon-ST protocol to Avalon-MM disclosed in the embodiment of the present application. It is mainly composed of CPU, APB bus split arbitration module, Avalon-ST to Avalon-MM module, kernel (i.e. algorithm core, the aforementioned FPGA algorithm module), Avalon-MM bus interconnection module, DDR controller, Block RAM controller and other modules. The CPU can be an ARM hard core embedded in the FPGA, or a soft core built with logic in the FPGA, which is mainly responsible for control scheduling; the Avalon-MM bus interconnection module is used for bus split arbitration, where S represents bus slave and M represents bus master; the DDR controller and the Block RAM controller respectively control the external storage DDR and the internal storage RAM; the kernel is responsible for the acceleration algorithm; the Avalon-ST to Avalon-MM module is responsible for converting the Avalon-ST bus to the Avalon-MM bus, and moving the kernel output data to the DDR or RAM; the APB bus is used for register read and write configuration.

[0094] It should be pointed out that all modules of this application are designed with standard bus protocols, which greatly facilitates system-level design and integration. Decoupling between modules guarantees the independence, portability and maintainability of each module to the greatest extent. Converting the avst interface protocol to the avmm interface simplifies the interface control of the kernel algorithm calculation module, making it convenient for the algorithm module to focus on calculation rather than control. The scheduling method can achieve full flow, and each module can be carried out synchronously. The method of configuring the address, length, and channel through registers improves the flexibility of the system, and the control authority is given to the CPU as much as possible, which greatly facilitates the development and design of the CPU control program. In addition, both digital IC and FPGA are digital circuit designs, and the solution provided in this application is applicable to FPGA design and digital IC design.

[0095] It can be seen that the embodiment of the present application configures the Avalon-ST bus channel number, the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number, and receives the data on the Avalon-ST bus through the depacketizer. If the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. That is, the embodiment of the present application configures the Avalon-ST bus channel number of the channel through which the FPGA algorithm module transmits data, receives data on the Avalon-ST bus through the depacketizer, and when the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, and the data is read from the data cache module through the controller and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. In this way, the Avalon-ST bus protocol is converted to the Avalon-MM bus protocol, and the data calculated by the algorithm module is written to the storage, rather than letting the algorithm module itself control the writing. This can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is beneficial to the system-level interconnection, development, maintenance and upgrading of the algorithm module.

[0096] See also Figure 5 As shown, the embodiment of the present application discloses an Avalon protocol conversion device, including:

[0097] The configuration module 11 is used to configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number;

[0098] The depacketizer 12 is used to receive data on the Avalon-ST bus, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, store the data in a data cache module;

[0099] The controller 13 is used to read the data from the data cache module and transmit the data to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory.

[0100] It can be seen that the embodiment of the present application configures the Avalon-ST bus channel number, the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number, and receives the data on the Avalon-ST bus through the depacketizer. If the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. That is, the embodiment of the present application configures the Avalon-ST bus channel number of the channel through which the FPGA algorithm module transmits data, receives data on the Avalon-ST bus through the depacketizer, and when the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, and the data is read from the data cache module through the controller and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. In this way, the Avalon-ST bus protocol is converted to the Avalon-MM bus protocol, and the data calculated by the algorithm module is written to the storage, rather than letting the algorithm module itself control the writing. This can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is beneficial to the system-level interconnection, development, maintenance and upgrading of the algorithm module.

[0101] The depacketizer 12 is further configured to directly discard the data if the channel number of the channel to which the data belongs is inconsistent with the channel number of the Avalon-ST bus.

[0102] Furthermore, the depacketizer 12 is specifically used to store the data into the FIFO; correspondingly, the controller 13 is specifically used to read the data from the FIFO.

[0103] The depacketizer 12 is further configured to suspend receiving data on the Avalon-ST bus if the FIFO is full.

[0104] The configuration module 11 is specifically used to configure the Avalon-ST bus channel number to the first register.

[0105] The configuration module 11 is also used to configure the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register respectively;

[0106] Correspondingly, the controller 13 is used to calculate the write burst address and the burst length based on the write address initial address and the write data length, and transmit the data and the write burst address and the burst length to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

[0107] The configuration module 11 is specifically used to configure the Avalon-ST bus channel number to the first register through the APB bus, and to configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0108] Furthermore, in one embodiment, the configuration module is a CPU, and the CPU is used to configure the Avalon-ST bus channel number to the first register through the APB bus, and configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0109] Furthermore, the controller is also used to suspend sending the data when receiving a wait request signal sent by the Avalon-MM bus slave module and the wait request signal indicates that the Avalon-MM bus slave module is currently busy.

[0110] Furthermore, the configuration module 11 is also used to configure the preset Avalon-ST to Avalon-MM module work trigger register so as to start the controller and the depacketizer to work; and set the work status characterization register to the working state.

[0111] Among them, after configuring the work trigger register, the depacketizer waits for data on the Avalon-ST bus. If the channel number does not match, it will be discarded directly after receiving. If the channel number matches, it will start receiving after receiving the startofpacket signal until the endofpacket signal is received. The ready / valid handshake signal protocol needs to be followed in this process. The received valid data is written into the FIFO. If the FIFO is full during this process, it is necessary to suspend receiving the AVST bus data and suspend writing the data into the FIFO. In addition, after configuring the work trigger register, the controller takes out the data through the FIFO, and passes the burst address, burst length and data to the slave module. When the Avmm_waitrequest signal transmitted from the slave module is high, it means that the slave module is busy and the transmission is suspended. When it is low, it means that it is idle and the burst address, burst length and data can be sent. After the AVMM bus write transmission is completed, the work status characterization register is set to the idle state low, indicating that the module is idle.

[0112] In one implementation, the first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer, and the data cache module all belong to a preset Avalon-ST to Avalon-MM module.

[0113] Furthermore, the preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

[0114] See also Figure 6 As shown, the embodiment of the present application discloses an electronic device, including a processing unit 21 and a storage unit 22; wherein the storage unit 22 is used to store a computer program; and the processing unit 21 is used to execute the computer program to implement the following steps:

[0115] The Avalon-ST bus channel number is configured; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number; the data on the Avalon-ST bus is received through the depacketizer, and if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module; the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory.

[0116] It can be seen that the embodiment of the present application configures the Avalon-ST bus channel number, the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number, and receives the data on the Avalon-ST bus through the depacketizer. If the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. That is, the embodiment of the present application configures the Avalon-ST bus channel number of the channel through which the FPGA algorithm module transmits data, receives data on the Avalon-ST bus through the depacketizer, and when the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, and the data is read from the data cache module through the controller and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. In this way, the Avalon-ST bus protocol is converted to the Avalon-MM bus protocol, and the data calculated by the algorithm module is written to the storage, rather than letting the algorithm module itself control the writing. This can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is beneficial to the system-level interconnection, development, maintenance and upgrading of the algorithm module.

[0117] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps may be specifically implemented: if the channel number of the channel to which the data belongs is inconsistent with the Avalon-ST bus channel number, the data is directly discarded.

[0118] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps may be specifically implemented: storing the data into the FIFO; and reading the data from the FIFO through the controller.

[0119] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps may be specifically implemented: if the FIFO is full, the reception of data on the Avalon-ST bus is suspended.

[0120] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps may be specifically implemented: configuring the Avalon-ST bus channel number to the first register.

[0121] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps can be specifically implemented: the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register respectively; the write burst address and the burst length are calculated by the controller based on the write address initial address and the write data length, and the data and the write burst address and the burst length are transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

[0122] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps can be specifically implemented: the Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

[0123] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps can be specifically implemented: using the CPU and configuring the Avalon-ST bus channel number to the first register through the APB bus, and configuring the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0124] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps can be specifically implemented: when a wait request signal sent by the Avalon-MM bus slave module is received and the wait request signal indicates that the Avalon-MM bus slave module is currently busy, suspending the sending of the data.

[0125] In this embodiment, when the processing unit 21 executes the computer subroutine stored in the storage unit 22, the following steps can be specifically implemented: configuring a preset Avalon-ST to Avalon-MM module work trigger register to start the controller and the depacketizer to work; setting the work status characterization register to the working state.

[0126] The first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer, and the data cache module all belong to a preset Avalon-ST to Avalon-MM module. The preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

[0127] Furthermore, an embodiment of the present application discloses a computer-readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the following steps are implemented:

[0128] The Avalon-ST bus channel number is configured; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number; the data on the Avalon-ST bus is received through the depacketizer, and if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module; the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory.

[0129] It can be seen that the embodiment of the present application configures the Avalon-ST bus channel number, the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number, and receives the data on the Avalon-ST bus through the depacketizer. If the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, the data is read from the data cache module through the controller, and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. That is, the embodiment of the present application configures the Avalon-ST bus channel number of the channel through which the FPGA algorithm module transmits data, receives data on the Avalon-ST bus through the depacketizer, and when the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in the data cache module, and the data is read from the data cache module through the controller and the data is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to the memory. In this way, the Avalon-ST bus protocol is converted to the Avalon-MM bus protocol, and the data calculated by the algorithm module is written to the storage, rather than letting the algorithm module itself control the writing. This can ensure the versatility of the FPGA algorithm module writing data to the storage, and realize the separation of writing data to the storage and calculation, which is beneficial to the system-level interconnection, development, maintenance and upgrading of the algorithm module.

[0130] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: if the channel number of the channel to which the data belongs is inconsistent with the Avalon-ST bus channel number, the data is directly discarded.

[0131] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: storing the data into the FIFO; and reading the data from the FIFO through the controller.

[0132] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: if the FIFO is full, suspending the reception of data on the Avalon-ST bus.

[0133] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: configuring the Avalon-ST bus channel number to the first register.

[0134] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register respectively; the write burst address and the burst length are calculated by the controller based on the write address initial address and the write data length, and the data and the write burst address and the burst length are transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

[0135] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: the Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

[0136] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: using the CPU and configuring the Avalon-ST bus channel number to the first register through the APB bus, and configuring the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively.

[0137] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: when a wait request signal sent by the Avalon-MM bus slave module is received and the wait request signal indicates that the Avalon-MM bus slave module is currently busy, suspending the sending of the data.

[0138] In this embodiment, when the computer subroutine stored in the computer-readable storage medium is executed by the processor, the following steps can be specifically implemented: configuring a preset working trigger register of the Avalon-ST to Avalon-MM module to start the controller and the depacketizer to work; setting the working status characterization register to the working state.

[0139] The first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer, and the data cache module all belong to a preset Avalon-ST to Avalon-MM module. The preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

[0140] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0141] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0142] The above is a detailed introduction to the Avalon protocol conversion method, device, equipment and medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An Avalon protocol conversion method, characterized in that: include: Configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number; Receiving data on the Avalon-ST bus through a depacketizer, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data in a data cache module; Reading the data from the data cache module through a controller, and transmitting the data to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into a memory; The controller calculates the burst write address and burst length of each Avalon-MM bus according to the initial write address and the write data length, and controls the behavior of the Avalon-MM bus; transmits the burst write address and burst length to the Avalon-MM bus slave module through a write signal, and transmits the data in the memory back through a write data signal and a start burst signal.

2. The Avalon protocol conversion method according to claim 1, characterized in that: Also includes: If the channel number of the channel to which the data belongs is inconsistent with the Avalon-ST bus channel number, the data is directly discarded.

3. The Avalon protocol conversion method according to claim 1, characterized in that: The storing the data into a data cache module comprises: Storing the data in FIFO; Correspondingly, reading the data from the data cache module through the controller includes: reading the data from the FIFO through the controller.

4. The Avalon protocol conversion method according to claim 3, characterized in that: Also includes: If the FIFO is full, the reception of data on the Avalon-ST bus is suspended.

5. The Avalon protocol conversion method according to claim 1, characterized in that: The configuration of the Avalon-ST bus channel number includes: Configure the Avalon-ST bus channel number to the first register.

6. The Avalon protocol conversion method according to claim 5, characterized in that: Also includes: Configure the write address initial address and write data length of the Avalon-MM bus to the second register and the third register respectively; The controller calculates a write burst address and a burst length based on the write address initial address and the write data length, and transmits the data and the write burst address and the burst length to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

7. The Avalon protocol conversion method according to claim 6, characterized in that: The Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

8. The Avalon protocol conversion method according to claim 7, characterized in that: The method configures the Avalon-ST bus channel number to the first register through the APB bus, and configures the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register respectively, including: The Avalon-ST bus channel number is configured to the first register through the APB bus using the CPU, and the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register respectively.

9. The Avalon protocol conversion method according to claim 6, characterized in that: Also includes: When a wait request signal sent by the Avalon-MM bus slave module is received and the wait request signal indicates that the Avalon-MM bus slave module is currently busy, the sending of the data is suspended.

10. The Avalon protocol conversion method according to claim 6, characterized in that: Also includes: Configure the preset Avalon-ST to Avalon-MM module's work trigger register to start the controller and the depacketizer to work; Set the working status characterization register to the working state.

11. The Avalon protocol conversion method according to claim 10, characterized in that: The first register, the second register, the third register, the work trigger register, the work status characterization register, the depacketizer and the data cache module all belong to a preset Avalon-ST to Avalon-MM module.

12. The Avalon protocol conversion method according to claim 11, characterized in that: The preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

13. An Avalon protocol conversion device, characterized in that: include: The configuration module is used to configure the Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through the channel corresponding to the Avalon-ST bus channel number; A depacketizer, configured to receive data on the Avalon-ST bus, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, store the data in a data cache module; A controller is used to read the data from the data cache module and transmit the data to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory; wherein the controller calculates the burst write address and burst length of each Avalon-MM bus according to the initial write address and the write data length, and controls the Avalon-MM bus behavior; transmits the burst write address and burst length to the Avalon-MM bus slave module through a write signal, and transmits the data in the memory back through a write data signal and a start burst signal.

14. An electronic device, characterized in that: It includes a storage unit and a processing unit, wherein: The storage unit is used to store the computer program; The processing unit is used to execute the computer program to implement the Avalon protocol conversion method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the Avalon protocol conversion method according to any one of claims 1 to 12 is implemented.

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