Constant voltage generating circuit

Abstract

The constant voltage generation circuit includes: a first amplifier circuit that drives a transistor controlling an output current based on a reference voltage; a second amplifier circuit that operates faster than the first amplifier circuit and drives the transistor based on the reference voltage; a protection circuit that limits the output current flowing from the transistor to a load; and a control circuit that controls the operation of the second amplifier circuit. The control circuit controls so that the second amplifier circuit does not operate until the output current increases to a second threshold current, and the second amplifier circuit operates when it becomes equal to or greater than the second threshold current. On the other hand, the second amplifier circuit operates until the output current decreases to a first threshold current smaller than the second threshold current, and the second amplifier circuit does not operate when it becomes equal to or less than the first threshold current. The second amplifier circuit further includes: a first operating potential fixing circuit that fixes the operating potential of an internal node of the second amplifier circuit when it is not operating.

Description

Technical Field

[0001] The present invention relates to a constant voltage generating circuit such as a low dropout regulator (hereinafter referred to as LDO) that operates even in the case of a relatively low input-output potential difference. Background Art

[0002] Conventionally, in a power supply circuit configuration that switches between multiple modes corresponding to the output voltage value, output current value, or the polarity of the terminal applied voltage, when a reference voltage source is shared, the potential of one or both of the drain and source of the transistor connected to the reference voltage source changes during the switching of each mode. During the above switching, the parasitic capacitance of the transistor acts as a coupling capacitance, and noise overlaps the reference voltage source, causing the reference voltage to change before and after the switching. As a result, the output voltage of the power supply circuit follows this, resulting in a change in the output voltage, or a change in the output current accompanies the change in the output voltage of the power supply circuit. And, due to the change in the output voltage, or the change in the output current accompanying the change in the output voltage of the power supply circuit, an unexpected mode transition is induced. In the worst case, there is a problem of malfunction that causes continuous transition between each mode.

[0003] As a means to avoid the above malfunctions, a method is known in which different reference voltage sources are used between the circuit where the potential changes and the other circuit so as not to affect the operation of the other circuit. Further, in order to suppress the absolute value of the noise overlapping the reference voltage source, it is also a known fact that during mode switching, the size of the transistor connected to the reference voltage source whose potential of one or both of the drain and source changes is reduced to reduce the parasitic capacitance. And, a bias is given to the differential amplifier so that when the reference voltage changes before and after the switching, the output voltage of the power supply circuit does not change due to the control that the output voltage of the power supply circuit follows the reference voltage, or the change in the output current accompanying it, resulting in a mode switch. This method also exists as a known technique.

[0004] For example, Patent Document 1 discloses a series regulator having: a first amplifier that drives a first transistor connected between a power supply and a load; a second amplifier that drives a second transistor connected in parallel with the first transistor; and an amplifier control circuit that controls the first amplifier and the second amplifier respectively. In this series regulator, the current capacity of the second transistor is set to be smaller than that of the first transistor, and the current consumption of the second amplifier is set to be smaller than that of the first amplifier. The amplifier control circuit controls the first amplifier and the second amplifier respectively so that in a first load region where the output current flowing to the load is smaller than a specified amplifier switching threshold, the first output current flowing in the first transistor becomes zero, and all the output current is supplied by the second output current flowing in the second transistor. On the other hand, in a second load region where the output current is larger than the amplifier switching threshold, the second output current becomes zero or a fixed value smaller than the amplifier switching threshold. In addition, the first amplifier and the second amplifier are controlled respectively so that all the output current is supplied by the first output current or the difference obtained by subtracting the second output current from the output current.

[0005] Prior Art Documents

[0006] Patent Document

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-185095 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] However, as a means for preventing malfunction of continuous migration between modes in the past, the method of using different reference voltage sources causes an increase in chip area, and due to the processing deviation of the reference voltage source, the difference in output voltage between modes causes deterioration in accuracy. In addition, the method of reducing the transistor size causes incorrect matching between transistors, resulting in an increase in the characteristic deviation of the comparator or differential amplifier, which also causes the difference in output voltage generated between modes to become larger, leading to deterioration in output voltage accuracy. Furthermore, the method of applying a bias to the differential amplifier requires a bias greater than the noise superimposed on the reference voltage source, so there are also problems such as deterioration in the accuracy of the output voltage as described above.

[0010] An object of the present invention is to solve the above problems and provide a constant voltage generation circuit that can suppress deterioration in the accuracy of the output voltage and prevent malfunction of continuous migration between multiple modes compared with the prior art.

[0011] Means for Solving the Problems

[0012] The constant voltage generation circuit according to one aspect of the present invention includes:

[0013] A transistor is connected between a power supply and a load to control an output current;

[0014] A first amplifier circuit drives the transistor based on a reference voltage from the power supply;

[0015] A second amplifier circuit is connected in parallel with the first amplifier circuit, operates faster than the first amplifier circuit, and drives the transistor based on a reference voltage from the power supply;

[0016] A protection circuit limits the output current flowing from the transistor to the load during a specified operation; and

[0017] A control circuit controls the operation of the second amplifier circuit,

[0018] The control circuit controls such that the second amplifier circuit does not operate until the output current increases from a light load to a specified second threshold current, and the second amplifier circuit operates when the output current becomes equal to or greater than the second threshold current. On the other hand, the second amplifier circuit operates until the output current decreases from a heavy load to a specified first threshold current smaller than the second threshold current, and the second amplifier circuit does not operate when the output current becomes equal to or less than the first threshold current.

[0019] The second amplifier circuit further includes: a first action potential fixing circuit that fixes the action potential of an internal node of the second amplifier circuit when it is not operating.

[0020] Advantageous Effects of the Invention

[0021] Thus, according to the constant voltage generation circuit of the present invention, it is possible to suppress changes in the output voltage of the reference voltage source due to noise overlap via the coupling capacitor. As a result, it is possible to set the bias voltage of the differential amplifier small, suppress deterioration in the accuracy of the output voltage that occurs as the difference in the output voltage in each mode, and prevent malfunction of the power supply circuit from continuously migrating between multiple modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram showing a structural example of the constant voltage generation circuit 2 and its peripheral circuits according to the embodiment.

[0023] Figure 2 is showing Figure 1 the detailed structure of the differential amplifier circuits 21 and 22 of.

[0024] Figure 3 is showing Figure 1Timing chart of the differential amplifier circuit 21 of the constant voltage generation circuit 2 and the stop operation of the differential amplifier circuit 22 for protecting the execution circuit 13.

[0025] Figure 4 It is a block diagram showing a structural example of the differential amplifier circuit 21A according to Modification 1.

[0026] Figure 5 It is a block diagram showing a structural example of the differential amplifier circuit 21B according to Modification 2.

[0027] Figure 6 It is a block diagram showing a structural example of the differential amplifier circuit 21C according to Modification 3.

[0028] Figure 7A It is to explain Figure 1 Graph showing the set values of the threshold currents Ith1 and Ith2 used in the differential amplifier circuit 21.

[0029] Figure 7B It is to explain Figure 1 Graph showing the set values of the threshold currents Ith3 and Ith4 used in the differential amplifier circuit 22. Detailed implementation mode

[0030] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same reference numerals are added to the same or similar structural elements.

[0031] (Knowledge and insights of the inventor)

[0032] In the series voltage regulator disclosed in Patent Document 1, the following situation was found: when the operation mode is switched, the noise of the differential amplifier overlaps with the output voltage from the reference voltage source having a high output resistance via the parasitic capacitance of the MOS transistor, resulting in a malfunction of the circuit such as switching oscillation that mutually switches between two operation modes. The purpose of the following embodiments is to prevent this malfunction.

[0033] (Embodiment)

[0034] Figure 1 It is a block diagram showing a structural example of the constant voltage generation circuit 2 and its peripheral circuits according to the embodiment.

[0035] In Figure 1 , the input voltage Vin is input from the DC voltage source 1 to the constant voltage generation circuit 2. The constant voltage generation circuit 2 is, for example, an LDO, and based on the input voltage Vin, generates a constant voltage Vout, which is output to the load 4 via the output capacitor 3.

[0036] The constant voltage generation circuit 2 is configured to include a reference voltage generation circuit 11, a monitored node 12, a protection execution circuit 13, a P-channel MOS transistor Q1, a current source 14, three differential amplifier circuits 21, 22, 23, and a control circuit 10 that controls the operations of the differential amplifier circuits 21 and 22.

[0037] The reference voltage generation circuit 11 converts the input voltage Vin into a specified reference voltage Vref and outputs it. The differential amplifier circuits 21 and 22 are, for example, "differential amplifier circuits with a voltage fluctuation suppression function" having the same circuit structure. Based on the enable signals EN1 and EN2 from the control circuit 10, they operate at an operation frequency of, for example, 10 MHz to several 100 MHz, operate faster and with higher power consumption than the differential amplifier circuit 23. Here, the differential amplifier circuits 21 and 22 operate in response to the enable signals EN1 and EN2 at the H level from the control circuit 10, respectively. On the other hand, they do not operate in response to the enable signal EN1 at the L level. Here, the differential amplifier circuit 21 is the main differential amplifier of the constant voltage generation circuit 2, generates a specified constant voltage, and supplies it to the load 4. In addition, the differential amplifier circuit 23 is the sub-differential amplifier of the constant voltage generation circuit 2, generates a specified constant voltage, and supplies it to the load 4.

[0038] Here, the differential amplifier circuit 21 constitutes the main differential amplifier circuit that is dominant in control under heavy load, and the differential amplifier circuit 22 is configured as the sub-differential amplifier circuit that is not dominant in control under heavy load. That is, under heavy load, the two differential amplifier circuits 21 and 22 operate. At this time, the differential amplifier circuit 21 with a large consumed current constitutes the main differential amplifier circuit, and the differential amplifier circuit 22 with a smaller consumed current than the differential amplifier circuit 21 constitutes the sub-differential amplifier circuit.

[0039] Furthermore, the differential amplifier circuit 22 detects, for example, the voltage of the monitored node 12 whose voltage changes in proportion to Vout, and together with the protection execution circuit 13 including a differential amplifier, constitutes a protection circuit that performs protection processing such as limiting the output current Iout using, for example, a known Brickwall current limiting method or Foldback current limiting method.

[0040] The output terminals of the differential amplifier circuits 21, 23, and the protection execution circuit 13 are connected to the gate of the MOS transistor Q1 that controls the output current Iout in accordance with the gate voltage. Thus, the differential amplifier circuits 21, 23, and the protection execution circuit 13 drive the MOS transistor Q1 to control the output current Iout flowing through the MOS transistor Q1. In addition, the positive electrode of the input voltage Vin is grounded via the source and drain of the MOS transistor Q1 and the current source 14.

[0041] Figure 7AIt is a diagram showing the set values of the threshold currents Ith1 and Ith2 used in the differential amplifier circuit 21 of Figure 1 . In addition, Figure 7B it is a diagram showing the set values of the threshold currents Ith3 and Ith4 used in the differential amplifier circuit 22 of Figure 1 . The control circuit 10 converts the gate voltage of the MOS transistor Q1 into the output current Iout, or operates as follows based on the current signal representing the output current Iout from the current sensor that detects the output current Iout flowing through the output voltage terminal.

[0042] (1) As shown in Figure 7A , while the output current Iout increases from the current 0 or light load to the threshold current Ith2, the control circuit 10 outputs the L-level enable signal EN1 to the differential amplifier circuit 21, and when Iout ≥ Ith2, outputs the H-level enable signal EN1 to the differential amplifier circuit 21. On the other hand, while the output current Iout decreases from the heavy load to the threshold current Ith1 (<Ith2), the control circuit 10 outputs the H-level enable signal EN1 to the differential amplifier circuit 21, and when Iout ≤ Ith1, outputs the L-level enable signal EN1 to the differential amplifier circuit 21. That is, through the Figure 7A hysteresis operation as such, the control circuit 10 controls the differential amplifier circuit 21.

[0043] (2) As shown in Figure 7B , while the output current Iout increases from the current 0 or light load to the threshold current Ith4, the control circuit 10 outputs the L-level enable signal EN2 to the differential amplifier circuit 22, and when Iout ≥ Ith4, outputs the H-level enable signal EN2 to the differential amplifier circuit 22. On the other hand, while the output current Iout decreases from the heavy load to the threshold current Ith3 (<Ith4), the control circuit 10 outputs the H-level enable signal EN2 to the differential amplifier circuit 22, and when Iout ≤ Ith3, outputs the L-level enable signal EN2 to the differential amplifier circuit 22. That is, through the Figure 7B hysteresis operation as such, the control circuit 10 controls the differential amplifier circuit 22.

[0044] In addition, the relationship of each threshold current Ith1 to Ith4 is set as follows.

[0045] Ith1 ≤ Ith3 < Ith2 (1)

[0046] Ith2 ≤ Ith4 (2)

[0047] Here, as a "simple example of setting the threshold current", the threshold currents Ith1 = Ith3 and Ith2 = Ith4 can also be set.

[0048] Figure 2 represents Figure 1 The circuit diagrams showing the detailed structures of the differential amplifier circuits 21 and 22. In Figure 2 the differential amplifier circuits 21 and 22 have the following five terminals T1 to T5.

[0049] (1) Inverting input terminal (INN) T1;

[0050] (2) Non-inverting input terminal (INP) T2;

[0051] (3) Output terminal T3;

[0052] (4) Enable signal terminal T4; and

[0053] (5) Reference voltage terminal T5.

[0054] In Figure 2 the differential amplifier circuits 21 and 22 are configured to include inverters 33, a bias voltage generation circuit 31, switches SW11, SW12, and a differential amplifier 32. Additionally, in Figure 2 among the multiple MOS transistors Q11 to Q34, the MOS transistors Q12, Q22, and Q32 are of the depletion type, but they can also be of the enhancement type, and the same applies hereinafter.

[0055] The bias voltage generation circuit 31 is configured to include a P-channel MOS transistor Q11, an N-channel MOS transistor Q12, and an N-channel MOS transistor Q13, and these MOS transistors are connected in series. The source of the MOS transistor Q11 is applied with the power supply voltage Vin, and the gate of the MOS transistor Q11 is connected to its drain. The gates of the MOS transistors Q12 and Q13 are connected to each other and connected to the terminal T5. The connection point P1 between the source of the MOS transistor Q12 and the drain of the MOS transistor Q13 is connected to the connection point P6 between the source of the MOS transistor Q22 and the drain of the MOS transistor Q23 in the differential amplifier 32 via the switch SW11. Furthermore, the source of the MOS transistor Q13 is grounded via the connection point P2 and via the current source 41. The connection point P2 is connected to the connection point P7 in the differential amplifier 32 via the switch SW12.

[0056] The bias voltage generation circuit 31 configured as above converts the reference voltage Vref applied to the terminal T5 into a specified bias voltage and applies it to the connection point P6 in the differential amplifier 32 via the switch SW11.

[0057] Figure 2The differential amplifier 32 is configured to include MOS transistors Q21, Q22, Q23, Q31, Q32, Q33, Q34, switches SW1, SW2, SW3, SW13, SW14, and current sources 42, 43. The MOS transistors Q21, connection point P4, MOS transistor Q22, connection point P6, and MOS transistor Q23 are connected in series with each other. The source of the MOS transistor Q21 is connected to the power supply voltage Vin, and the source of the MOS transistor Q23 is grounded via the switch SW2 and the current source 42. In addition, the MOS transistors Q31, connection point P5, and MOS transistors Q32, 33 are connected in series with each other. The source of the MOS transistor Q31 is connected to the power supply voltage Vin, and the source of the MOS transistor Q33 is grounded via the switch SW2 and the current source 42. Further, the gates of the MOS transistors Q21 and Q31 are connected to the connection point P3, which is connected to the power supply voltage Vin via the switch SW13 and to the connection point P4 via the switch SW1.

[0058] The gates of the MOS transistors Q32 and Q33 are connected to each other and then connected to the terminal T2. The connection point P5 is connected to the gate of the MOS transistor Q34. The gate of the MOS transistor Q34 is connected to the power supply voltage Vin and the source of the MOS transistor Q34 via the switch SW14. The drain of the MOS transistor Q34 is grounded via the connection point connected to the terminal T3, the switch SW3, and the current source 43.

[0059] The enable signals EN1 and EN2 input to the terminal T4 are input to the control terminals of the switches SW1 to SW3 and are also input to the inverter 33. The inverted enable signals / EN1 and / EN2 output from the inverter 33 are input to the control terminals of the switches SW11 to SW14. When the enable signals EN1 and EN2 of H level are input to the control terminals of the switches SW1 to SW3, the switches SW1 to SW3 are turned on. On the other hand, when the enable signals EN1 and EN2 of L level are input, the switches SW1 to SW3 are turned off. In addition, when the inverted enable signals / EN1 and / EN2 of H level are input to the control terminals of the switches SW11 to SW14, the switches SW11 to SW14 are turned on. On the other hand, when the inverted enable signals / EN1 and / EN2 of L level are input, the switches SW11 to SW14 are turned off.

[0060] In the differential amplifier circuits 21 and 22 configured as described above, when the enable signals EN1 and EN2 of H level are input, the switches SW1 to SW3 are turned on and the switches SW11 to SW14 are turned off. At this time, in a state where a prescribed bias voltage from the bias voltage generation circuit 31 is not applied to the differential amplifier 32, the differential amplifier 32 becomes an operating state. Accordingly, the differential amplifier 32 subtracts the inverted input voltage INN input to the inverted input terminal T1 from the non-inverted input voltage INP input to the non-inverted input terminal T2, and outputs an output voltage obtained by amplifying the subtracted voltage from the terminal T3. In addition, the terminal T3 of the differential amplifier circuit 21 is connected to the gate of the MOS transistor Q1 of Figure 1 and the terminal T3 of the differential amplifier circuit 22 is connected to the gate of the MOS transistor Q1 via Figure 1 the protection execution circuit 13.

[0061] Further, when the enable signals EN1 and EN2 of L level are input, the switches SW1 to SW3 are turned off and the switches SW11 to SW14 are turned on. At this time, in a state where a prescribed bias voltage from the bias voltage generation circuit 31 is applied to the differential amplifier 32, the differential amplifier 32 becomes a non-operating state. Accordingly, the differential amplifier 32 does not perform the differential amplification described above and becomes a stopped state where no output is made from the terminal T3, but since a prescribed bias voltage is applied, voltage fluctuations at the contacts P6 and P7 are suppressed, and thereby voltage fluctuations at the gates of the MOS transistors Q22 and Q23 via the parasitic capacitances of the MOS transistors Q22 and Q23 are suppressed.

[0062] That is, the differential amplifier circuits 21 and 22 perform differential amplification operations respectively during operation, and do not perform differential amplification operations during non-operation. However, at this time, a prescribed bias voltage is applied to the internal nodes (connection points P6 and P7), and thus fluctuations in the reference voltage Vref can be suppressed.

[0063] Figure 3 is a timing chart showing the stop operations of the differential amplifier circuit 21 of the constant voltage generation circuit 2 of Figure 1 and the differential amplifier circuit 22 for the protection execution circuit 13. In addition, Figure 3 shows a case of a simple setting example of the threshold current in the case where the threshold currents Ith1 = Ith3 and Ith2 = Ith4 are set.

[0064] In Figure 3During the time period T11, the enable signals EN1 and EN2 are set to the H level. Therefore, the differential amplifier circuit 21 is in an operating state, and the differential amplifier circuit 22 for protecting the execution circuit 13 becomes an operating state, and the protection circuit operates. Next, at time t1, the load changes from heavy to light, so that the output current Iout decreases and becomes output current Iout ≤ Ith3. In the control circuit 10, the enable signal EN2 becomes the L level. Therefore, the operation of the differential amplifier circuit 22 for protecting the execution circuit 13 stops. In addition, the enable signal EN1 is set to the L level. In the state where the bias voltage is applied to the differential amplifier 32, the differential amplifier 32 becomes a non-operating state. Thus, the differential amplifier circuit 21 becomes a state where it does not perform the above-described differential amplification. However, since a prescribed bias voltage is applied, the variation of the reference voltage via the parasitic capacitances of the MOS transistors Q22 and Q23 is suppressed. The above-described effect is also exhibited in the differential amplifier circuit 22. At this time, as an effect of the bias voltage, the change in the output voltage of the reference voltage source is small. Therefore, the variation of the output current Iout is also small. The differential amplifier circuit 22 for protecting the execution circuit 13 and the differential amplifier circuit 21 do not malfunction, and the output voltage Vout does not oscillate.

[0065] As described above, as Figure 2 shown, the differential amplifier circuits 21 and 22 are constituted by the "differential amplifier circuit with voltage variation suppression function". When each of the differential amplifier circuits 21 and 22 becomes a stopped state, a prescribed bias voltage is applied to each of the differential amplifiers 32 of the differential amplifier circuits 21 and 23. Therefore, the variation of the reference voltage Vref via the parasitic capacitances of the MOS transistors Q22 and Q23 is suppressed. At this time, as an effect of the bias voltage, the voltage variation of the output voltage Vout is small. Therefore, the variation of the output current Iout is also small. The differential amplifier circuits 21 and 22 and the protection execution circuit 13 do not malfunction, and the output voltage Vout does not oscillate. That is, by suppressing the change in the output voltage of the reference voltage source, the bias voltage of the differential amplifier can be set small, the deterioration of the accuracy of the output voltage Vout between modes can be suppressed, and the malfunction of the power supply circuit continuously migrating between multiple modes can be prevented.

[0066] (Modification of the Embodiment)

[0067] In the above-described embodiments, it is provided that when the differential amplifier circuit 22 for protecting the execution circuit 13 enters a stopped state, a stop control circuit that stops the operation of the differential amplifier circuit 22 used by the protection execution circuit 13, or a bias voltage generation circuit 31 that fixes the bias voltage of the differential amplifier circuit 22. The present invention is not limited thereto. The above-described functional circuits may be provided only for the differential amplifier circuit 21 and not for the differential amplifier circuit 22, or the function of stopping the operation in accordance with the output current based on the enable signal EN2 from the control circuit 10 may not be provided.

[0068] In the above-described embodiments, the differential amplifier circuit 23 is constituted by a normal differential amplifier circuit without a voltage fluctuation suppression function. The present invention is not limited thereto. The differential amplifier circuit 23 may also be constituted by a differential amplifier circuit with a voltage fluctuation suppression function, similarly to the differential amplifier circuits 21 and 22.

[0069] In the above-described embodiments, the MOS transistors Q12, Q13, the MOS transistors Q22, Q23, and the MOS transistors Q32, Q33 are connected in cascade. The present invention is not limited thereto. They may not be connected in cascade, and may be constituted by only one MOS transistor Q13, Q23, and Q33, respectively.

[0070] (Other modification examples)

[0071] In the above-described embodiments, the differential amplifier circuits 21 and 22 used in the constant voltage generation circuit 2 have been described. Hereinafter, modification examples 1, 2, and 3 of the differential amplifier circuits 21 and 22 will be described. In the following, they are denoted as differential amplifier circuits 21A, 21B, and 21C, but their structures may be similarly applied to the differential amplifier circuits 21 and 22.

[0072] (Modification example 1)

[0073] Figure 4 is a block diagram showing a structural example of the differential amplifier circuit 21A according to modification example 1. In Figure 4 , the same reference numerals are attached to the same structural elements as Figure 2 . Figure 4 The differential amplifier circuit 21A of Figure 2 has the following differences compared with the differential amplifier circuits 21 and 22 of

[0074] (1) Instead of the bias voltage generation circuit 31, a bias voltage generation circuit 31A is provided.

[0075] (2) Instead of the differential amplifier 32, a differential amplifier 32A is provided.

[0076] Hereinafter, the differences will be described.

[0077] In Figure 4 , the bias voltage generation circuit 31A is configured to include MOS transistors Q11, Q13, current sources 41, 44, and MOS transistors Q41, Q42. The bias voltage generation circuit 31A has the following differences compared with the bias voltage generation circuit 31.

[0078] (1) The MOS transistor Q12 is deleted.

[0079] (2) The current mirror circuit CM1 is formed by MOS transistors Q41, Q42, so that a bias voltage corresponding to the source potential of the MOS transistor Q13 is generated by the current mirror circuit CM1 and output to the connection point P7 via the switch SW15.

[0080] The enable signal EN1 input to the terminal T4 is input to the control terminals of the switches SW1 to SW3, and is also input to the control terminals of the switches SW13 to SW15 via the inverter 33.

[0081] According to the differential amplifier circuit 21A configured as above, in the non-operating state, a bias voltage corresponding to the source potential of the MOS transistor Q13 is generated by the current mirror circuit CM1 and output to the connection point P7 of the differential amplifier 32A, thereby suppressing the change in the output voltage of the reference voltage source.

[0082] (Modification Example 2)

[0083] Figure 5 is a block diagram showing a structural example of the differential amplifier circuit 21B according to Modification Example 2. In Figure 5 for, with respect to Figure 2 and Figure 4 the same structural elements are assigned the same reference numerals. Figure 5 The differential amplifier circuit 21B of Figure 4 has the following differences compared with the differential amplifier circuit 21A of

[0084] (1) Instead of the bias voltage generation circuit 31A, a bias voltage generation circuit including an internal reference voltage generation circuit 50 and a voltage generation circuit 60 is provided.

[0085] (2) Instead of the differential amplifier 32A, a differential amplifier 32AA is provided. In addition, compared with the differential amplifier 32A, the differential amplifier 32AA has a switch SW11 that connects the connection point P22 of the voltage generation circuit 60 to the connection point P6 of the differential amplifier 32AA instead of the switch SW15.

[0086] Thus, the differential amplifier circuit 21B is configured to include an internal reference voltage generation circuit 50, a voltage generation circuit 60, and a differential amplifier 32AA. Hereinafter, the differences will be described.

[0087] In Figure 5 Figure 5

[0088] The voltage generation circuit 60 is configured to include P-channel MOS transistors Q60 to Q62 and N-channel MOS transistors Q63 and Q64. Here, a current mirror circuit CM2 is formed by MOS transistors Q51 and Q60. In addition, a current mirror circuit is formed by MOS transistors Q61 to Q64. Thus, the voltage generation circuit 60 adjusts the output impedance by the current mirror circuit CM2 for the constant voltage from the internal reference voltage generation circuit 50 and outputs it to the differential amplifier 32AA.

[0089] The enable signal EN1 input to the terminal T4 is input to each control terminal of the switches SW1 to SW3 and is also input to each control terminal of the switches SW11, SW13, and SW14 via the inverter 33.

[0090] According to the differential amplifier circuit 21B configured as described above, in the non-operating state, a bias voltage corresponding to the drain potential of the MOS transistor Q51 is generated by the current mirror circuit CM2 and output to the connection point P6 of the differential amplifier 32AA, thereby suppressing the change in the output voltage of the reference voltage source.

[0091] (Modification Example 3)

[0092] Figure 6 is a block diagram showing a structural example of the differential amplifier circuit 21C according to Modification Example 3. Figure 6 The differential amplifier circuit 21C of Figure 2 differs from the differential amplifier circuit 21 of

[0093] (1) Instead of the bias voltage generation circuit 31, a current generation circuit including two parallel transistor circuits 70, 80 and a current source circuit 90 is provided.

[0094] (2) Instead of the differential amplifier 32, a differential amplifier 32B is provided.

[0095] Hereinafter, the differences will be described.

[0096] The differential amplifier 32B is configured to include switches SW3, SW13, SW14, SW20, MOS transistors Q21, Q31, Q32, Q33, Q34, and a current source 43. Here, the output amplifier circuit is constituted by the MOS transistor Q34 and the current source 43.

[0097] Two parallel transistor circuits 70, 80 are connected in series with each other between the MOS transistor Q21 and the current source circuit 90. Here, the parallel transistor circuit 70 is configured to include two MOS transistors Q71, Q72, and a switch SW21. In addition, the parallel transistor circuit 80 is configured to include two MOS transistors Q81, Q82, and a switch SW23. Furthermore, the current source circuit 90 is configured to include two current sources 91, 92, and a switch SW25. Thus, when the switches SW21 to SW25 are turned off (when the differential amplifier 32B is not operating), the flowing current is smaller than when the switches SW21 to SW25 are turned on (when the differential amplifier 32B is operating). In particular, when the differential amplifier 32B is not made to operate, a small current is caused to flow from the current generation circuit to the internal nodes (connection points P4, P6, P7) of the differential amplifier 32B, and its operating potential is fixed, thereby suppressing the change in the output voltage of the reference voltage source.

[0098] In addition, the MOS transistors connected to the switches in the parallel transistor circuits 70, 80 are not limited to one each, and may be multiple MOS transistors.

[0099] In the above-described embodiments and modification examples 1 and 2, when the differential amplifiers 32, 32A, 32AA are not operating, a predetermined bias voltage is applied from the bias voltage generation circuits 31, 31A and the voltage generation circuit 60 to the internal nodes of the differential amplifiers 32, 32A, 32AA, respectively, thereby fixing the operating potential of the differential amplifiers 32, 32A, 32AA (constituting an operating potential fixing circuit), and thereby suppressing the potential variation of the reference voltage. In contrast, in modification example 3, when the differential amplifier 32B is not made to operate, a predetermined small current is caused to flow to the internal nodes (connection points P4, P6, P7) of the differential amplifier 32B (current generation circuit), and its operating potential is fixed (constituting an operating potential fixing circuit), thereby suppressing the potential variation of the reference voltage.

[0100] (Further modification example)

[0101] In the above-described embodiments and modification examples, switches SW1 to SW25 are provided. Here, the switches SW1 to SW25 are constituted by semiconductor switch elements such as MOS transistors, for example.

[0102] In the above-described embodiments and modifications, the differential amplifiers 32, 32A, and 32B are used, but the present invention is not limited thereto, and an amplifier that amplifies an input voltage may also be used.

[0103] Industrial availability

[0104] As described in detail above, according to the constant voltage generation circuit of the present invention, it is possible to suppress variations in the output voltage of the reference voltage source caused by noise overlap via the coupling capacitor. As a result, the bias voltage of the differential amplifier can be set small, deterioration in the accuracy of the output voltage that occurs as the difference in the output voltage in each mode can be suppressed, and malfunction in which the power supply circuit continuously migrates between multiple modes can be prevented.

[0105] Reference numeral description

[0106] 1 DC voltage source

[0107] 2 Constant voltage generation circuit

[0108] 3 Output capacitor

[0109] 4 Load

[0110] 10 Control circuit

[0111] 11 Reference voltage generation circuit

[0112] 12 Monitored object node

[0113] 13 Protection execution circuit

[0114] 14 Current source

[0115] 21 to 23, 21A, 21B, 21C Differential amplifier circuit

[0116] 31, 31A Bias voltage generation circuit

[0117] 32, 32A, 32AA, 32B Differential amplifier

[0118] 33 Inverter

[0119] 41 to 45 Current source

[0120] 50 Internal reference voltage generation circuit

[0121] 51 Differential amplifier

[0122] 60 Voltage generation circuit

[0123] 70, 80 Parallel transistor circuit

[0124] 90 Current source circuit

[0125] Current sources 91 to 92

[0126] Connection points P1 to P22

[0127] Current mirror circuits CM1, CM2

[0128] MOS transistors Q1 to Q82

[0129] Voltage dividing resistors R1, R2

[0130] Switches SW1 to SW25

[0131] Terminals T1 to T5

Claims

1. A constant voltage generation circuit, comprising: A transistor connected between a power supply and a load to control an output current; A first amplifier circuit that drives the transistor based on a reference voltage generated based on the voltage of the power supply; A second amplifier circuit connected in parallel with the first amplifier circuit, operating faster than the first amplifier circuit, and driving the transistor based on a reference voltage from the power supply; A protection circuit that limits the output current flowing from the transistor to the load during a specified operation; And A control circuit that controls the operation of the second amplifier circuit, The second amplifier circuit is a differential amplifier circuit, including a first transistor pair that is a differential pair including an internal node that determines the operating point of the second amplifier circuit and applies a bias voltage, The control circuit controls such that the second amplifier circuit does not operate when the output current increases from a light load to a specified second threshold current, and the second amplifier circuit operates when it becomes equal to or greater than the second threshold current. On the other hand, the second amplifier circuit operates when the output current decreases from a heavy load to a specified first threshold current that is smaller than the second threshold current, and the second amplifier circuit does not operate when it becomes equal to or less than the first threshold current, The second amplifier circuit further includes: a first operating potential fixing circuit that fixes the operating potential of the internal node of the second amplifier circuit during non-operation, The first operating potential fixing circuit is: (1) A first bias voltage generation circuit that applies a specified bias voltage to the internal node of the second amplifier circuit during non-operation of the second amplifier circuit to fix the operating potential; or (2) A first current generation circuit that causes a specified current to flow through the internal node of the second amplifier circuit during non-operation of the second amplifier circuit to fix the operating potential.

2. The constant voltage generation circuit according to claim 1, The protection circuit further includes a third amplifier circuit that is a differential amplifier circuit, including a second transistor pair that is a differential pair including an internal node that determines the operating point of the third amplifier circuit and applies a bias voltage, The control circuit controls such that the third amplifier circuit does not operate when the output current increases from a light load to a specified fourth threshold current, and the third amplifier circuit operates when it becomes equal to or greater than the fourth threshold current. On the other hand, the third amplifier circuit operates when the output current decreases from a heavy load to a specified third threshold current that is smaller than the fourth threshold current, and the third amplifier circuit does not operate when it becomes equal to or less than the third threshold current.

3. The constant voltage generation circuit according to claim 2, The first threshold current is set to be equal to the third threshold current, and the second threshold current is set to be equal to the fourth threshold current.

4. The constant voltage generation circuit according to claim 2 or 3, The protection circuit further includes: a second operating potential fixing circuit that fixes the operating potential of the internal node of the third amplifier circuit during non-operation.

5. The constant voltage generation circuit according to claim 4, The second action potential fixing circuit is: (1) A second bias voltage generation circuit that applies a prescribed bias voltage to the internal node of the third amplifier circuit when the protection circuit is not operating, thereby fixing the action potential; or (2) A second current generation circuit that causes a prescribed current to flow to the internal node of the third amplifier circuit when the protection circuit is not operating, thereby fixing the action potential.

6. The constant voltage generation circuit according to claim 1, The first bias voltage generation circuit includes: A voltage generation circuit formed by connecting at least two transistors in series, which generates a prescribed bias voltage based on the reference voltage.

7. The constant voltage generation circuit according to claim 5, The second bias voltage generation circuit includes: A voltage generation circuit formed by connecting at least two transistors in series, which generates a prescribed bias voltage based on the reference voltage.

8. The constant voltage generation circuit according to claim 1, The first bias voltage generation circuit includes: A first voltage generation circuit formed by connecting at least two transistors in series, which generates a prescribed bias voltage based on the reference voltage; and A second voltage generation circuit including a current mirror circuit that generates a bias voltage corresponding to the bias voltage generated by the first voltage generation circuit and outputs it to the internal node of the second amplifier circuit.

9. The constant voltage generation circuit according to claim 1, The first bias voltage generation circuit includes: An internal reference voltage generation circuit that generates a prescribed internal reference voltage based on the reference voltage; and A voltage generation circuit that generates a prescribed bias voltage based on the internal reference voltage, adjusts the output impedance using a current mirror circuit, and outputs it to the internal node of the second amplifier circuit.

10. The constant voltage generation circuit according to claim 1, The first current generation circuit, When the second amplifier circuit is operating, causes a prescribed first current to flow to the internal node of the second amplifier circuit, When the second amplifier circuit is not operating, causes a prescribed second current smaller than the first current to flow to the internal node of the second amplifier circuit.

11. The constant voltage generation circuit according to claim 5, The second bias voltage generation circuit includes: A first voltage generation circuit formed by connecting at least two transistors in series, which generates a prescribed bias voltage based on the reference voltage; and A third voltage generation circuit including a current mirror circuit that generates a bias voltage corresponding to the bias voltage generated by the first voltage generation circuit and outputs it to the internal node of the third amplifier circuit.

12. The constant voltage generation circuit according to claim 5, The second bias voltage generation circuit includes: An internal reference voltage generation circuit that generates a prescribed internal reference voltage based on the reference voltage; and A voltage generation circuit that generates a prescribed bias voltage based on the internal reference voltage, adjusts the output impedance using a current mirror circuit, and outputs it to the internal node of the third amplifier circuit.

13. The constant voltage generation circuit according to claim 5, The second current generation circuit, When the third amplifier circuit operates, a predetermined first current is caused to flow to an internal node of the third amplifier circuit. When the third amplifier circuit does not operate, a predetermined second current smaller than the first current is caused to flow to the internal node of the third amplifier circuit.

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