Ripple suppression circuit, control method, and driving device

Abstract

A ripple suppression circuit, a control method and a driving device are disclosed. The ripple suppression circuit comprises: a first input port configured to receive an input voltage via a first diode (D2); a first output port configured to output an output voltage; a first capacitor (C2) configured to be connected between the first input port and a ground port; a first transistor (Q1) configured to be connected between the first input port and the first output port; a second diode (D4) and a second capacitor (C1) configured to be connected in series between the first input port and the ground port; a second transistor (Q2) configured to be coupled between a base of the first transistor and a connection node of the second diode (D4) and the second capacitor (C1); a third capacitor (C3) configured to be connected between the base of the second transistor and the ground port; and a voltage control circuit (100, 100a, 100b) configured to be connected to the base of the second transistor (Q2), when the input voltage drops to a minimum value, the voltage control circuit (100) makes the voltage of the base of the second transistor (Q2) higher than the input voltage, and makes the output voltage equal to the minimum value. Therefore, the power dissipation of the ripple suppression circuit is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to the field of lighting, and more specifically to a ripple suppression circuit, a control method and a driving device. BACKGROUND

[0002] This section introduces aspects that can be helpful in better understanding the aspects of the present disclosure. Thus, the statements of this section are to be read in this light and not as admissions of prior art. The present disclosure relates to a ripple suppression circuit, a control method and a driving device.

[0003] In the field of lighting technology, it is often required to configure a driving current for driving a lighting device. The lighting device is for example a LED (Light Emitting Diode).

[0004] The lighting device is driven by a driver, which outputs a direct current to the lighting device. For most low cost drivers, the output current has a high ripple factor, for example ±30% or even higher. The high ripple factor can cause the lighting device to flicker.

[0005] It is mandatory for low-ripple current to meet regulatory requirements for suppressing low-frequency ripples (100 Hz to 120 Hz) in LED lighting applications for numerous markets.

[0006] A single-stage conversion is usually used as a cost-effective solution for LED drivers, which always maintains a high power factor, but also maintains a high ripple current. It is low-accepted for the market of these high-ripple current devices. A ripple suppression circuit is developed to maintain a low cost and provide a high level of ripple suppression while maintaining a high power factor.

[0007] Figure 1 is a schematic diagram of a ripple suppression circuit according to the prior art solution. As Figure 1 shown, the ripple suppression circuit 1 comprises a capacitor C65 and a transistor Q61, C65 provides a filter of the capacitor equal to (B+1)*C 65 , where B is equal to the DC (direct current) current gain of Q61, C 65 is the capacitance of C65. Therefore, the ripple suppression circuit 1 can work as a capacitor multiplier. The output voltage of the ripple suppression circuit 1 can be provided for driving the LED. In addition, the ripple suppression circuit 1 also comprises C63, D63, D64, D65, D69, R63, R64, R66, R67, DR66 and L61; their working principle can be referred to as related art, such as WO2019 / 165589A1.

[0008] Figure 2 is a schematic diagram of the input voltage and the output voltage of the ripple suppression circuit 1. As Figure 2As shown, a ripple voltage with an amplitude of 6V is added on a DC voltage of 50V. There is a voltage drop V_drop on Q61, V_drop resulting in a difference between the output voltage and the minimum value of the input voltage. SUMMARY

[0009] The inventors of the present disclosure have found that in the ripple suppression circuit 1 as shown, the following limitations are found: the value of DR66 needs to be tuned to cover the worst case; the voltage drop on Q61 is related to the output voltage and the input voltage; the voltage drop on Q61 can be high in the worst case and results in low efficiency and potential thermal issues. Figure 1 The inventors of the present disclosure have found that in the ripple suppression circuit 1 as shown, the following limitations are found: the value of DR66 needs to be tuned to cover the worst case; the voltage drop on Q61 is related to the output voltage and the input voltage; the voltage drop on Q61 can be high in the worst case and results in low efficiency and potential thermal issues.

[0010] Generally, embodiments of the present disclosure provide a ripple suppression circuit, a control method and a driving device. In this embodiment, a voltage control circuit is used to make the output voltage equal to the minimum value, thus, the difference between the output voltage and the minimum value of the input voltage can be reduced.

[0011] In a first aspect, a ripple suppression circuit is provided, the ripple suppression circuit comprising:

[0012] a first input port configured to receive an input voltage via a first diode (D2);

[0013] a first output port configured to output an output voltage;

[0014] a first capacitor (C2) configured to be connected between the first input port and a ground port;

[0015] a first transistor (Q1) configured to be connected between the first input port and the first output port;

[0016] a second diode (D4) and a second capacitor (C1) configured to be connected in series between the first input port and the ground port;

[0017] a second transistor (Q2) configured to be coupled between a base of the first transistor and a connection node of the second diode (D4) and the second capacitor (C1);

[0018] a third capacitor (C3) configured to be connected between a base of the second transistor and the ground port; and

[0019] a voltage control circuit (100, 100a, 100b) configured to be connected to the base of the second transistor (Q2), the voltage control circuit (100) making the voltage of the base of the second transistor (Q2) higher than the input voltage and making the output voltage equal to the minimum value when the input voltage drops to the minimum value.

[0020] In one embodiment, the ripple suppression circuit according to claim 1, wherein

[0021] The voltage control circuit (100) comprises:

[0022] a first resistor (R2) configured to be connected between the collector of the second transistor and the base of the second transistor; and

[0023] a third diode (D1) and a fourth diode (D5) configured to be coupled in reverse series between the first input port and the base of the second transistor, the cathode of the third diode (D1) being connected to the first input port, the anode of the fourth diode (D5) being coupled to the base of the second transistor.

[0024] In one embodiment, the ripple suppression circuit according to claim 1, wherein

[0025] The voltage control circuit (100a) comprises:

[0026] a fourth capacitor (C4) configured to be coupled between the ground port and a connection node of the second diode (D4) and the second capacitor (C1);

[0027] a fifth diode (D11) and a sixth diode (D51) configured to be coupled in reverse series between the first input port and the fourth capacitor (C4), the cathode of the sixth diode (D51) being connected to the first port, the anode of the fifth diode (D11) being coupled to the fourth capacitor (C4);

[0028] a comparator (X1) configured to compare the voltage at the base of the second transistor (Q2) with the voltage of the anode of the fifth diode (D11) and output a comparison result; and

[0029] an optical coupler (U1) configured to be controlled by the comparison result, the optical coupler coupling the base of the second transistor (Q2) to the anode of the fifth diode (D11) when the voltage at the base of the second transistor (Q2) is lower than the voltage of the anode of the fifth diode (D11).

[0030] In one embodiment, the ripple suppression circuit according to claim 3, wherein

[0031] the input port of the optical coupler (U1) receives the comparison result,

[0032] The two output ports of the optical coupler (U1) are connected to the base of the second transistor (Q2) and a connection node of the second diode (D4) and the second capacitor (C1), respectively.

[0033] In one embodiment, the ripple suppression circuit according to claim 1, wherein,

[0034] The voltage control circuit (100b) comprises:

[0035] a controller (M1) configured to: detect the input voltage, and output a control signal, the controller outputs a first control signal when the input voltage drops to the minimum value; and

[0036] an optical coupler (U1) configured to be controlled by the control signal, the optical coupler connects the base of the second transistor (Q2) to the collector of the second transistor (Q2) when receiving the first control signal.

[0037] In one embodiment, the ripple suppression circuit according to claim 5, wherein,

[0038] The input port of the optical coupler (U1) receives the control signal,

[0039] The two output ports of the optical coupler (U1) are coupled to the base of the second transistor (Q2) and the collector of the second transistor (Q2), respectively.

[0040] In one embodiment, the ripple suppression circuit according to any one of claims 1 to 6, wherein,

[0041] The ripple suppression circuit further comprises a Zener diode (D3), the anode of the Zener diode (D3) is connected to the base of the second transistor (Q2), and the cathode of the Zener diode (D3) is connected to the collector of the second transistor (Q2).

[0042] In a second aspect, a control method for a ripple suppression circuit is provided, the ripple suppression circuit comprises:

[0043] a first input port configured to receive an input voltage via a first diode (D2);

[0044] a first output port configured to output an output voltage;

[0045] a first capacitor (C2) configured to be connected between the first input port and a ground port;

[0046] a first transistor (Q1) configured to be connected between the first input port and the first output port;

[0047] a second diode (D4) and a second capacitor (C1) configured to be connected in series between the first input port and the ground port;

[0048] a second transistor (Q2) configured to be coupled between a base of the first transistor and a connection node of the second diode (D4) and the second capacitor (C1);

[0049] a third capacitor (C3) configured to be connected between a base of the second transistor and the ground port; and

[0050] a voltage control circuit (100, 100a, 100b) configured to be connected to the base of the second transistor (Q2),

[0051] The control method comprises:

[0052] when the input voltage drops to a minimum value, the voltage control circuit (100, 100a, 100b) causes the voltage of the base of the second transistor (Q2) to be higher than the input voltage, and causes the output voltage to be equal to the minimum value.

[0053] In a third aspect, there is provided a driving device comprising a driving circuit and a ripple suppression circuit according to the first aspect of the present disclosure, the input voltage being provided by the driving circuit.

[0054] According to various embodiments of the present disclosure, the difference between the output voltage and the minimum value of the input voltage can be reduced; thus, power dissipation is reduced, and higher efficiency can be obtained in the ripple suppression circuit. BRIEF DESCRIPTION OF DRAWINGS

[0055] The above and other aspects, features, and benefits of various embodiments of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, by way of illustration in which like reference numerals or letters indicate similar, equivalent, or identical components in the several figures. The drawings are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. In the drawings:

[0056] Figure 1 is a schematic diagram of a ripple suppression circuit according to prior solutions;

[0057] Figure 2 is a schematic diagram of an input voltage and an output voltage of a ripple suppression circuit;

[0058] Figure 3is a schematic diagram of a ripple suppression circuit according to one embodiment of the present disclosure.

[0059] Figure 4 is a schematic diagram of an input voltage and an output voltage of the ripple suppression circuit 30

[0060] Figure 5 is a schematic diagram of a ripple suppression circuit according to another embodiment of the present disclosure.

[0061] Figure 6 is a schematic diagram of a ripple suppression circuit according to another embodiment of the present disclosure.

[0062] Figure 7 A flowchart illustrating a control method 700 of a ripple suppression circuit is shown. DETAILED DESCRIPTION

[0063] The present disclosure will now be discussed with reference to several exemplary embodiments. It is to be understood that the discussion of these embodiments is merely meant to provide a better understanding of the present disclosure and thus the present disclosure is not intended to be limited to any of the embodiments discussed.

[0064] As used herein, the terms "first" and "second" refer to different elements. The singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "includes," "including," "has," "having," and / or "contains," "containing," specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof. The term "based on" is understood to mean "based, at least in part, on." The terms "one embodiment" and "an embodiment" are understood to be "at least one embodiment." The term "another embodiment" is understood to be "at least one other embodiment." Other explicitly and implicitly recited definitions can be included below.

[0065] First aspect of the embodiments

[0066] In a first embodiment, a ripple suppression circuit is provided.

[0067] Figure 3 is a schematic diagram of a ripple suppression circuit according to one embodiment of the present disclosure. As shown, the ripple suppression circuit 30 includes a first input port X1-a, a first output port X2-a, a first capacitor C2, a first transistor Q1, a second diode D4, a second capacitor C1, a second transistor Q2, a third capacitor C3, and a voltage control circuit 100. Figure 3

[0068] ​In this embodiment, the first input port X1-a is configured to receive an input voltage via a first diode D2, the input voltage being denoted as Vin. The first output port X2-a is configured to output an output voltage, the output voltage being denoted as Vout.

[0069] In this embodiment, the first capacitor C2 is configured to be connected between the first input port X1-a and the ground port. The first transistor Q1 is configured to be connected between the first input port X1-a and the first output port X2-a. The second diode D4 and the second capacitor C1 are configured to be connected in series between the first input port X1-a and the ground port.

[0070] The second transistor Q2 is configured to be coupled between the base of the first transistor Q1 and the connection node A of the second diode D4 and the second capacitor C1. The third capacitor C3 is configured to be connected between the base of the second transistor Q2 and the ground port.

[0071] like Figure 3 As shown, the first transistor Q1 is a bipolar transistor, such as an NPN bipolar transistor. The second transistor Q2 is a bipolar transistor, such as an NPN bipolar transistor. The emitter of Q1 is connected to the first output port X2-a, the collector of Q1 is connected to the first input port X1-a, and the base of Q1 is connected to the emitter of Q2 via resistor R3. The collector of the second transistor Q2 is connected to node A. This embodiment is not limited to this; the first transistor Q1 and the second transistor Q2 can be other types, such as MOS FETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0072] The voltage control circuit 100 is configured to be connected to the base of the second transistor Q2. When the input voltage drops to a minimum value, the voltage control circuit 100 makes the voltage at the base of the second transistor Q2 higher than the minimum value and makes the output voltage equal to the minimum value.

[0073] According to the first aspect of the implementation scheme, the difference between the minimum values ​​of the output voltage and the input voltage can be reduced; therefore, the power dissipation of Q1 is reduced, and higher efficiency can be obtained in the ripple suppression circuit 30.

[0074] It should be noted that the operating principle of the ripple suppression circuit 30 is described from a voltage perspective. That is, the ripple suppression circuit 30 can suppress voltage ripple on the output voltage; however, it can also suppress current ripple on the output current, depending on the VI characteristics of the load on which the ripple suppression circuit 30 is located. For example, when the load of the ripple suppression circuit 30 is an LED or other electrical components with similar VI characteristics to LEDs, low ripple on the output voltage will result in low ripple on the output current driving the LED; therefore, the ripple suppression circuit 30 is used to suppress current ripple on the output current. Similarly, when the load of the ripple suppression circuit 30 is a resistor or other electrical components with similar VI characteristics to resistors, using an output voltage with low ripple to drive the LED will also suppress voltage ripple on the output voltage.

[0075] like Figure 3 As shown, in at least one embodiment, the voltage control circuit 100 includes: a first resistor R2, a third diode D1, and a fourth diode D5.

[0076] A first resistor R2 is configured to be connected between the collector and base of the second transistor Q2. Current can flow from the collector to the base of Q2 through the first resistor R2 to charge the third capacitor C3.

[0077] The third diode D1 and the fourth diode D5 are configured to be connected in reverse series between the first input port X1-a and the base of the second transistor Q2. The cathode of the third diode D1 is connected to the first input port X1-a, and the anode of the fourth diode D5 is coupled to the base of the second transistor Q2. For example, the anode of the fourth diode D5 is connected to the base of the second transistor Q2 via a resistor R4.

[0078] like Figure 3 As shown, V1 represents DC voltage, and V2 represents ripple voltage. V2 is added to V1 to simulate a DC voltage with ripple. For example, V1 is 50V, and V2 is a sine wave with an amplitude of 6V and a frequency of 100Hz.

[0079] A rippled DC voltage is rectified by diode D2. On the output side, resistor R1 is connected between output port X2-a and ground port.

[0080] like Figure 3 As shown, when the input voltage drops to its minimum value Vin_min, the base voltage of Q2 and the output voltage satisfy the following conditions:

[0081] Vo=Vb-2*Vf1 (1)

[0082] Vb = Vin_min + 2*Vf2 (2)

[0083] Vo = Vin_min + 2*Vf2 - 2*Vf1 = Vin_min (3)

[0084] In (1), (2) and (3), Vo represents the output voltage, Vb represents the voltage of the base of Q2, Vf2 represents the on voltage of D1 or D5, Vf1 represents the voltage drop between the base of Q2 and the emitter of Q2 or the voltage drop between the base of Q1 and the emitter of Q1. Vf1 is equal to Vf2.

[0085] According to (3), Vo is equal to Vin_min, thus, the difference between the output voltage and the minimum of the input voltage can be reduced. The power dissipation of the ripple suppression circuit 30 is reduced and the risk of thermal issues is reduced.

[0086] Figure 4 is a schematic diagram of the input voltage and the output voltage of the ripple suppression circuit 30. As Figure 4 shown, a ripple voltage with an amplitude of 6V is added on a DC voltage of 50V. 41 represents the input voltage, 42 represents the output voltage. The output voltage 42 is equal to the minimum of the input voltage 41. Thus, the difference between the output voltage 42 and the minimum of the input voltage 41 is reduced.

[0087] Figure 5 is a schematic diagram of a ripple suppression circuit according to another embodiment of the disclosure. As Figure 5 shown, the ripple suppression circuit 30a is a variant of the ripple suppression circuit 30, the differences of which will be described below. The description of the common elements in Figure 5 and Figure 3 is omitted.

[0088] As Figure 5 shown, the ripple suppression circuit 30a comprises a voltage control circuit 100a. The voltage control circuit 100a comprises a fourth capacitor C4, a fifth diode D11, a sixth diode D51, a comparator X1 and an optical coupler U1.

[0089] As Figure 5 shown, the fourth capacitor C4 is configured to be coupled between a ground port and a connection node A of the second diode D4 and the second capacitor C1.

[0090] The fifth diode D11 and the sixth diode D51 are configured to be coupled in reverse series between the first input port X1-a and the fourth capacitor C4. The cathode of the sixth diode D51 is connected to the first port X1-a, and the anode of the fifth diode D11 is connected to the fourth capacitor C4. In addition, the resistor R2 is connected between the anode of D11 (connection node A) and the collector of Q2 (connection node B). The resistor R2 has a huge resistance (e.g., 100 kΩ), and is used to charge the fourth capacitor C4.

[0091] The comparator X1 is configured to compare the voltage at the base of the second transistor Q2 with the voltage of the anode of the fifth diode D11, and output the comparison result. For example, the resistor R6 is connected between the anode of D11 and the "+" input port of the comparator X1, so as to detect the voltage of the anode of D11 (i.e., the voltage of connection node A); the resistor R9 is connected between the base of Q2 and the "-" input port of the comparator X1, so as to detect the voltage of the base of Q2 (i.e., Vb); the resistor R7 is connected between the "+" input port of X1 and the ground port; the resistor R8 is connected between the "-" input port of X1 and the ground port, and the resistance of R7 is equal to the resistance of R8; the voltage V3 is applied to the "+" power input port of X1, and the "-" power input port of X1 is connected to the ground port; the resistor R5 is connected to the output port of X1. When the voltage of the anode of D11 is higher than the voltage of the base of Q2, the output port of X1 outputs a signal with a high voltage as the comparison result.

[0092] The optical coupler U1 is configured to be controlled by the comparison result, and when the voltage of the anode of the fifth diode D11 is higher than the voltage at the base of the second transistor Q2, the optical coupler U1 couples the base of the second transistor Q2 to the anode of the fifth diode D11.

[0093] For example, the input port of the optical coupler U1 receives the comparison result, and the two output ports of the optical coupler U1 are respectively connected to the base of the second transistor Q2 and the connection node A of the second diode D4 and the second capacitor C1 (the collector of Q2). When the comparison result is a high voltage, the transistor in U1 is turned on, and C3 is discharged through the transistor in U1, R4 and R9 until the voltage of the base of Q2 is equal to the voltage of the connection node A.

[0094] As shown in FIG. 2, when the input voltage drops to the minimum value Vin_min, the voltage of the connection node A is (Vin_min+2*Vf21). The voltage of the base of Q2 and the output voltage (Vo) satisfy the following conditions: Figure 5 Vo = Vb - 2*Vf1 (4)

[0095] Vo = Vb - 2*Vf1 (4)

[0096] Vb = Vin_min + 2*Vf21 (5)

[0097] Vo = Vin_min + 2*Vf2 - 2*Vf1 = Vin_min (6)

[0098] In (4), (5) and (6), Vo represents the output voltage, Vb represents the voltage of the base of Q2, Vf21 represents the on voltage of D11 or D51, Vf1 represents the voltage drop between the base of Q2 and the emitter of Q2 or the voltage drop between the base of Q1 and the emitter of Q1. Vf1 is equal to Vf21.

[0099] According to (6), in the embodiment of Figure 5 Vo is equal to Vin_min, thus, the difference between the output voltage and the minimum value of the input voltage can be reduced. The power dissipation of the ripple suppression circuit 30a is reduced and the risk of thermal issues is reduced.

[0100] Figure 6 is a schematic diagram of a ripple suppression circuit according to another embodiment of the disclosure. As Figure 6 shown, the ripple suppression circuit 30b is a variant of the ripple suppression circuit 30; their differences will be described below. The description of the common elements in Figure 6 and Figure 3 is omitted.

[0101] As Figure 6 shown, the ripple suppression circuit 30b comprises a voltage control circuit 100b. The voltage control circuit 100b comprises a controller M1, a fifth diode D11 and an optical coupler U1. The voltage control circuit 100b further comprises a resistor R9 for feeding back the base voltage of Q2 to the controller M1.

[0102] The controller M1 is configured to detect the input voltage Vin and output a control signal. When the input voltage drops to the minimum value (i.e., Vin_min), the controller M1 compares (Vin_min + 2Vf1) with the base voltage (Vb) of Q2. If (Vin_min + 2Vf1) is higher than Vb, the controller M1 outputs a first control signal. When the base voltage (Vb) of Q2 is equal to (Vin_min + 2Vf1), the controller M1 stops outputting the first control signal. For example, the controller M1 is an MCU (microcontroller unit).

[0103] The optical coupler U1 is configured to be controlled by the control signal, when receiving the first control signal, the optical coupler U1 connects the base of the second transistor Q2 to the collector of the second transistor Q2.

[0104] For example, the input port of the optical coupler U1 receives the control signal, and the two output ports of the optical coupler U1 are coupled to the base of the second transistor Q2 and to the collector of the second transistor Q2, respectively. For example, when U1 receives the first control signal, the transistor in U1 is turned on, and capacitor C3 is discharged through the transistor in U1 and resistor R9 until the base voltage (Vb) of Q2 is equal to (Vin_min + 2Vf1). As shown in Figure 6 Resistor R9 serves two purposes: one purpose is to sample the base voltage (Vb) for M1, and the other purpose is to discharge C3.

[0105] As shown in Figure 6 When the input voltage drops to the minimum value Vin_min, the controller M1 controls the base voltage (Vb) of Q2 to become Vb = Vin_min + 2*Vf1, and the output voltage Vo to become Vo = Vb - 2*Vf1 = Vin_min. Vf1 represents the voltage drop between the base of Q2 and the emitter of Q2 or the voltage drop between the base of Q1 and the emitter of Q1.

[0106] According to the embodiment of Figure 6 Vo is equal to Vin_min, therefore, the difference between the output voltage and the minimum value of the input voltage can be reduced. The power dissipation of the ripple suppression circuit 30b is reduced, and the risk of thermal problems is reduced.

[0107] In Figure 3 , Figure 5 and Figure 6 , the ripple suppression circuit 100, 100a, 100b further comprises a Zener diode D3. The anode of the Zener diode D3 is connected to the base of the second transistor Q2, and the cathode of the Zener diode D3 is connected to the collector of the second transistor Q2. The Zener diode D3 can prevent the voltage drop between the collector and the base of Q2 from being too high.

[0108] Second aspect of the embodiments

[0109] A control method for a ripple suppression circuit. In one embodiment, the ripple suppression circuit of the first aspect of the embodiments is provided. Those identical to the content in the first aspect of the embodiments are omitted.

[0110] Figure 7 A flowchart of the control method 700 of the ripple suppression circuit is shown.

[0111] As shown in Figure 7 The method 700 comprises:

[0112] Block 701 : When the input voltage drops to the minimum value, the voltage control circuit (100, 100a, 100b) makes the voltage of the base of the second transistor (Q2) higher than the input voltage, and makes the output voltage equal to the minimum value.

[0113] According to a second aspect of embodiments, the difference between the output voltage and the minimum value of the input voltage can be reduced; thus, the power dissipation of Q1 and the ripple suppression circuit is reduced, and a higher efficiency can be obtained in the ripple suppression circuit.

[0114] Third aspect of the embodiments

[0115] In one embodiment, a driving device is provided. The driving device comprises a driving circuit and a ripple suppression circuit according to the first aspect of embodiments.

[0116] In this embodiment, the ripple suppression circuit receives an input voltage provided by the driving circuit, and outputs a signal with a low ripple factor. This signal with a low ripple factor can be provided to the lighting device, so that the flicker of the lighting device can be reduced.

[0117] The driving circuit can be formed by a flyback converter or a resonant half-bridge converter or an LLC converter comprising a transformer. Instead of a transformer, a part of the switching converter can come from an inductor, for example a buck converter or a boost converter forming the driving circuit. The timing of the driving circuit, in particular of the transformer, by at least one controllable switch clocked at a high frequency can depend on a control signal input to a control input of the driving circuit. For example, the frequency and / or the duty cycle of the controllable switches of the driving circuit can be adjusted depending on the control signal input to the input of the driving circuit.

[0118] The driving circuit can generate a driving current or a driving voltage for the lighting device. The driving circuit can output the driving current or the driving voltage for the lighting device at a first input port X1-a in order to output the input voltage to the ripple suppression circuit 30 (or 30a, 30b).

[0119] Furthermore, although the operations are shown in a specific order, this should not be construed as requiring such operations to be performed in the shown specific order or in a sequential order, or as requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the foregoing discussion, these specific implementation details should not be construed as limiting the scope of this disclosure, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0120] Although this disclosure has been described in language specific to structural features and / or methodological actions, it should be understood that this disclosure, as defined by the appended claims, is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. A ripple suppression circuit, comprising: The first input port is configured to receive the input voltage via a first diode (D2); The first output port is configured to output the output voltage; A first capacitor (C2) is configured to be connected between the first input port and the ground port; A first transistor (Q1) is configured to be connected between the first input port and the first output port; A second diode (D4) and a second capacitor (C1) are configured to be connected in series between the first input port and the ground port; The second transistor (Q2) is configured to be coupled between the base of the first transistor and the connection node of the second diode (D4) and the second capacitor (C1); A third capacitor (C3) is configured to be connected between the base of the second transistor and the ground port; and A voltage control circuit (100a), configured to be connected to the base of the second transistor (Q2), when the input voltage drops to a minimum value, causes the voltage at the base of the second transistor (Q2) to be higher than the input voltage, and causes the output voltage to be equal to the minimum value, wherein... The voltage control circuit (100a) includes: A fourth capacitor (C4) is configured to be coupled between the ground port and the connection node of the second diode (D4) and the second capacitor (C1); A fifth diode (D11) and a sixth diode (D51) are configured to be connected in reverse series between the first input port and the fourth capacitor (C4), with the cathode of the sixth diode (D51) connected to the first input port and the anode of the fifth diode (D11) coupled to the fourth capacitor (C4). The comparator (X1) is configured to compare the voltage at the base of the second transistor (Q2) with the voltage at the anode of the fifth diode (D11) and output the comparison result. and An optical coupler (U1), configured to be controlled by the comparison result, couples the base of the second transistor (Q2) to the anode of the fifth diode (D11) when the voltage at the base of the second transistor (Q2) is lower than the voltage at the anode of the fifth diode (D11).

2. The ripple suppression circuit according to claim 1, wherein, The input port of the optical coupler (U1) receives the comparison result. The two output ports of the optical coupler (U1) are respectively connected to the base of the second transistor (Q2) and the connection node of the second diode (D4) and the second capacitor (C1).

3. A ripple suppression circuit, comprising: The first input port is configured to receive the input voltage via a first diode (D2); The first output port is configured to output the output voltage; A first capacitor (C2) is configured to be connected between the first input port and the ground port; A first transistor (Q1) is configured to be connected between the first input port and the first output port; A second diode (D4) and a second capacitor (C1) are configured to be connected in series between the first input port and the ground port; The second transistor (Q2) is configured to be coupled between the base of the first transistor and the connection node of the second diode (D4) and the second capacitor (C1); A third capacitor (C3) is configured to be connected between the base of the second transistor and the ground port; and A voltage control circuit (100b), configured to be connected to the base of the second transistor (Q2), when the input voltage drops to a minimum value, causes the voltage at the base of the second transistor (Q2) to be higher than the input voltage, and causes the output voltage to be equal to the minimum value, wherein... The voltage control circuit (100b) includes: A controller (M1) is configured to detect the input voltage and output a control signal, wherein when the input voltage drops to the minimum value, the controller outputs a first control signal; and An optical coupler (U1) is configured to be controlled by the control signal, wherein when the first control signal is received, the optical coupler connects the base of the second transistor (Q2) to the collector of the second transistor (Q2).

4. The ripple suppression circuit according to claim 3, wherein, The input port of the optical coupler (U1) receives the control signal. The two output ports of the optical coupler (U1) are respectively coupled to the base and collector of the second transistor (Q2).

5. The ripple suppression circuit according to any one of claims 1 to 4, wherein, The ripple suppression circuit also includes a Zener diode (D3), the anode of which is connected to the base of the second transistor (Q2), and the cathode of which is connected to the collector of the second transistor (Q2).

6. A driving device comprising a ripple suppression circuit according to any one of claims 1 to 5.

7. A control method for a ripple suppression circuit, the ripple suppression circuit comprising: The first input port is configured to receive the input voltage via a first diode (D2); The first output port is configured to output the output voltage; A first capacitor (C2) is configured to be connected between the first input port and the ground port; A first transistor (Q1) is configured to be connected between the first input port and the first output port; A second diode (D4) and a second capacitor (C1) are configured to be connected in series between the first input port and the ground port; The second transistor (Q2) is configured to be coupled between the base of the first transistor and the connection node of the second diode (D4) and the second capacitor (C1); A third capacitor (C3) is configured to be connected between the base of the second transistor and the ground port; and A voltage control circuit (100a) is configured to be connected to the base of the second transistor (Q2), wherein, The voltage control circuit (100a) includes: A fourth capacitor (C4) is configured to be coupled between the ground port and the connection node of the second diode (D4) and the second capacitor (C1); A fifth diode (D11) and a sixth diode (D51) are configured to be connected in reverse series between the first input port and the fourth capacitor (C4), with the cathode of the sixth diode (D51) connected to the first input port and the anode of the fifth diode (D11) coupled to the fourth capacitor (C4). A comparator (X1) is configured to compare the voltage at the base of the second transistor (Q2) with the voltage at the anode of the fifth diode (D11) and output the comparison result; and An optical coupler (U1), configured to be controlled by the comparison result, couples the base of the second transistor (Q2) to the anode of the fifth diode (D11) when the voltage at the base of the second transistor (Q2) is lower than the voltage at the anode of the fifth diode (D11). The control method includes: When the input voltage drops to its minimum value, the voltage control circuit (100a) makes the base voltage of the second transistor (Q2) higher than the input voltage and makes the output voltage equal to the minimum value.

8. A control method for a ripple suppression circuit, the ripple suppression circuit comprising: The first input port is configured to receive the input voltage via a first diode (D2); The first output port is configured to output the output voltage; A first capacitor (C2) is configured to be connected between the first input port and the ground port; A first transistor (Q1) is configured to be connected between the first input port and the first output port; A second diode (D4) and a second capacitor (C1) are configured to be connected in series between the first input port and the ground port; The second transistor (Q2) is configured to be coupled between the base of the first transistor and the connection node of the second diode (D4) and the second capacitor (C1); A third capacitor (C3) is configured to be connected between the base of the second transistor and the ground port; and A voltage control circuit (100b) is configured to be connected to the base of the second transistor (Q2), wherein, The voltage control circuit (100b) includes: Controller (M1), configured to: detect the input voltage and output a control signal, wherein when the input voltage drops to a minimum value, the controller outputs a first control signal; and An optical coupler (U1), configured to be controlled by the control signal, connects the base of the second transistor (Q2) to the collector of the second transistor (Q2) upon receiving the first control signal. The control method includes: When the input voltage drops to the minimum value, the voltage control circuit (100b) makes the voltage at the base of the second transistor (Q2) higher than the input voltage and makes the output voltage equal to the minimum value.

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