A polysilicon fuse-type non-volatile memory and its fabrication method

Abstract

This invention provides a polysilicon fuse-type non-volatile memory and its fabrication method. The memory includes multiple memory cells, each comprising a polysilicon fuse. Each polysilicon fuse includes sequentially connected first, second, and third fuse segments. The first and third fuse segments are made of doped polysilicon, while the second fuse segment is made of intrinsic polysilicon. This invention utilizes ion implantation to dope the polysilicon, creating a sandwich-like polysilicon region: a low-resistivity polysilicon region + an intrinsic polysilicon narrow spot + a low-resistivity polysilicon region. This structure effectively controls the programming position of the memory cells, ensuring a deterministic and controllable fuse-breaking position, thus effectively improving the resistance distribution after programming. This structure also effectively improves data stability before and after programming, preventing data loss due to disconnection and reconnection. Furthermore, the upper region of this structure utilizes a conductive capping layer to shield the data storage portion of the memory cells, enhancing data security.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology and relates to a polysilicon fuse type non-volatile memory and its fabrication method. Background Technology

[0002] Using polyfusible fuses to adjust chip electrical parameters is a common method to reduce the impact of process variations on circuit performance parameters. As process feature sizes shrink, polyfusible fuses become easier to adjust. Polyfusible fuse-based non-volatile memory cell adjustment technology has gradually developed into a technique that can be adjusted after packaging. It is easier to integrate, requires no special components or additional layers, and is fully compatible with logic processes, finding widespread application in deep submicron processes. (In the formula...) In this context, MTTF is the average fusing time, A is a constant, J is the current density, T is the temperature, and E is the thermal conductivity. a The activation energy is approximately 0.9 eV, k is the Boltzmann constant, and n is a model parameter between 1 and 2. It is easy to see that the MTTF time is mainly related to the J current density, which in turn is affected by the cross-sectional area of ​​the polycrystalline fuse and the magnitude of the current, being proportional to the current magnitude and inversely proportional to the cross-sectional area.

[0003] like Figure 1 The diagram shows a common structure of a polysilicon fuse-type non-volatile memory cell. Here, "fuse" represents a polysilicon fuse, M1 represents the first select transistor, M2 represents the second select transistor, WWL represents the write word line, RWL represents the read word line, BL represents the bit line, and PL represents the power supply line. This structure has two operating modes: read mode and write mode. Specific operation methods are shown in Table 1, where "Program mode" represents programming mode, "Read mode" represents read mode, VDD represents the operating voltage, "Floating" represents floating, VPP represents the programming / erase voltage, and "sense amp" represents the comparator amplifier. In programming mode, the first select transistor M1 is turned on, and the second select transistor M2 is turned off. In read mode, the first select transistor M1 is turned off, and the second select transistor M2 is turned on. The core programming function unit consists of a first selection transistor M1 and a polycrystalline fuse. When the first selection transistor M1 is turned on, the programming current flows through the polycrystalline fuse and the first selection transistor M1. A precise current can cause irreversible damage to the polycrystalline fuse, completely destroying its polycrystalline structure and changing its resistance from a small value (about tens of ohms) to a large value (tens of kilohms or more). This thousand-fold change in resistance can be detected by a detection circuit.

[0004] WWL RWL BL PL Program mode VDD 0 Floating VPP Read mode 0 VDD sense amp 0

[0005] Table 1

[0006] like Figure 2 The diagram shows a layout of a polycrystalline non-volatile memory cell, including an ion implantation region 101, a metal lead-out region 102, a polycrystalline region 103, and a contact region 104. Actual research has found that in traditional fuse cells, when the burn-out point after adjustment occurs near both ends of the fuse (first end 105 and second end 106), due to the chemical properties of the fuse, it diffuses outwards. This means that the adjusted resistance has a certain probability of reconnecting after being opened, causing the resistance to decrease from a large value to several hundred ohms or a few kilohms, thus making the adjusted data uncontrollable.

[0007] Furthermore, research on the working principle of existing polysilicon fuse-type non-volatile memory cells reveals that the melting position of the fuse device varies randomly, sometimes near the end of the fuse and sometimes near the middle. This introduces uncertainty into the final adjustment result: sometimes the melting point is tens of kilobytes per second, sometimes hundreds of kilobytes per second, and sometimes several megabytes per second. This distribution reduces the current "0" and "1" window range of the bit cell, increasing design complexity and affecting the stability of stored data. Additionally, existing polysilicon fuse-type non-volatile memory cells show noticeable burn-out marks, which is detrimental to data protection. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a polycrystalline fuse-type non-volatile memory and its manufacturing method, which solves the problems in the prior art such as the uncertainty of the fuse position leading to uncontrollable results, the uncertainty of the resistance distribution after fuse breaking leading to large dispersion of results, obvious fuse traces, and lack of shielding layer, which is not conducive to data confidentiality.

[0009] To achieve the above and other related objectives, the present invention provides a polysilicon fuse-type non-volatile memory, which includes a plurality of memory cells. Each memory cell includes a polysilicon fuse, and the polysilicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the three fuse segments are all made of doped polysilicon, and the second fuse segment is made of intrinsic polysilicon.

[0010] Optionally, the length of the second fuse segment is less than the length of the first fuse segment, and the length of the second fuse segment is less than the length of the third fuse segment.

[0011] Optionally, the second fuse segment is located at the halfway point or the golden section point of the polycrystalline silicon fuse.

[0012] Optionally, the memory cell further includes a conductive cover layer located above the polysilicon fuse, the conductive cover layer blocking the second fuse segment on the vertical projection of the plane where the polysilicon fuse is located; the material of the conductive cover layer includes conductive metal or polysilicon.

[0013] Optionally, the memory cell further includes a first conductive material layer and an insulating dielectric layer, wherein the first conductive material layer is located on the upper surface of the polysilicon fuse, the insulating dielectric layer is located on the upper surface of the first conductive material layer, and the conductive cover layer is located on the upper surface of the insulating dielectric layer.

[0014] Optionally, the memory unit further includes a doped polysilicon connection portion connected to both ends of the polysilicon fuse and a second conductive material layer electrically connected to the doped polysilicon connection portion.

[0015] Optionally, the memory cell further includes a substrate and an isolation dielectric layer located on the substrate, wherein the polysilicon fuse is located on the isolation dielectric layer.

[0016] Optionally, the substrate has a first well region and a second well region, the first well region is located in the second well region, the vertical projection of the second fuse segment of the polysilicon fuse on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is the same as the doping type of the substrate.

[0017] This invention also provides a method for fabricating a polysilicon fuse-type non-volatile memory, comprising the following steps:

[0018] Forming an intrinsic polycrystalline silicon layer;

[0019] Ion implantation is performed on a predetermined region of the intrinsic polycrystalline silicon layer to obtain a polycrystalline silicon fuse. The polycrystalline silicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the three fuse segments are all made of doped polycrystalline silicon, and the second fuse segment is made of intrinsic polycrystalline silicon.

[0020] Optionally, the ion implantation of the preset region of the intrinsic polysilicon layer includes: performing the ion implantation using a mask having at least an opening pattern of a first ion implantation region and an opening pattern of a second ion implantation region, wherein the opening of the first ion implantation region exposes the first fuse segment, the opening of the second ion implantation region exposes the third fuse segment, and the second fuse segment is covered by the mask.

[0021] Optionally, the method further includes the following steps: forming a first conductive material layer on the upper surface of the intrinsic polysilicon layer, forming an insulating dielectric layer on the upper surface of the first conductive material layer, and forming a conductive capping layer on the upper surface of the insulating dielectric layer.

[0022] Optionally, the method further includes the following steps: providing a substrate, forming an isolation dielectric layer on the substrate, and forming the intrinsic polysilicon layer on the isolation dielectric layer.

[0023] Optionally, the method further includes the following steps: forming a first well region and a second well region in the substrate, wherein the first well region is located in the second well region, the vertical projection of the second fuse segment of the polysilicon fuse on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is the same as the doping type of the substrate.

[0024] As described above, the polycrystalline fuse-type non-volatile memory and its fabrication method of the present invention utilize the ion implantation doping process of polycrystalline material to generate a sandwich-like polycrystalline region, namely a low-resistivity polycrystalline region + intrinsic polycrystalline narrow point + low-resistivity polycrystalline region structure. This structure can effectively control the programming position of the memory cell, ensuring that the fuse point does not occur at either end, but only near the polycrystalline narrow point. In other words, the fuse position is deterministic and controllable, thereby effectively improving the resistance distribution of the memory cell after programming, reducing the dispersion of the resistance distribution, improving the robustness of the design, and increasing the design width of the window interval between the "0" and "1" states of the cell. Simultaneously, this structure can also effectively improve the data stability before and after programming the memory cell, preventing data loss due to disconnection and reconnection. Furthermore, the upper region of this structure cleverly utilizes a metal layer or polycrystalline layer to shield the data storage portion of the memory cell, effectively improving the data confidentiality of the memory cell. Attached Figure Description

[0025] Figure 1 It is shown as a polycrystalline fuse-type non-volatile memory cell structure.

[0026] Figure 2 This is shown as a layout of a polycrystalline non-volatile memory cell.

[0027] Figure 3 The diagram shown represents a layout of a memory cell in the polycrystalline fuse-type non-volatile memory of the present invention.

[0028] Figure 4 The diagram shown is a three-dimensional cross-sectional view of a storage cell of the polycrystalline fuse-type non-volatile memory of the present invention.

[0029] Figure 5 The diagram shown is a cross-sectional view of another three-dimensional structure of the storage cell of the polycrystalline fuse-type non-volatile memory of the present invention.

[0030] Component designation explanation

[0031] 101 Ion Implantation Region

[0032] 102 Metal Lead-out Area

[0033] 103 Polycrystalline region

[0034] 104 Contact Area

[0035] 105 First End

[0036] 106 Second End

[0037] 201 First ion implantation region

[0038] 202 Second ion implantation region

[0039] 203 polycrystalline silicon layer

[0040] 203a First Doped Polycrystalline Silicon Connector

[0041] 203b Polycrystalline Silicon Fuse

[0042] 203c Second Doped Polycrystalline Silicon Connector

[0043] 203d First Doped Polycrystalline Region

[0044] 203e Undoped polycrystalline region

[0045] 203f Second Doped Polycrystalline Region

[0046] 204a First Contact Section

[0047] 204b Second Contact Section

[0048] 205a, 205b Second conductive material layer

[0049] 206, 206a, 206b conductive coating

[0050] 207 First Trap Zone

[0051] 208 substrate

[0052] 209 Isolation Medium Layer

[0053] 210 Second Well Region

[0054] 211 First conductive material layer

[0055] 212 Insulating dielectric layer

[0056] 213 Third Contact Section Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] Example 1

[0060] This embodiment provides a polysilicon fuse-type non-volatile memory, including multiple memory cells. Each memory cell includes a polysilicon fuse, and the polysilicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the three fuse segments are all made of doped polysilicon, and the second fuse segment is made of intrinsic polysilicon.

[0061] As an example, one end of the second fuse segment of the polysilicon fuse is connected to the first fuse segment, and the other end of the second fuse segment is connected to the third fuse segment.

[0062] Specifically, since the first and third fuse segments are doped and have low resistance, while the second fuse segment uses undoped intrinsic polysilicon and has high resistance, when the polysilicon fuse is blown, the heat will be concentrated in the second fuse segment with higher resistance. This can effectively control the programming position of the memory cell, so that the melting point will not occur at both ends of the fuse, but only near the position of the second fuse segment. That is, the melting position is deterministic and controllable, which can effectively improve the resistance distribution of the memory cell after programming, reduce the dispersion of the cell resistance distribution after programming, improve the robustness of the design, and increase the design width of the window interval between the cell "0" and "1" states.

[0063] As an example, the length of the second fuse segment is less than the length of the first fuse segment, and the length of the second fuse segment is less than the length of the third fuse segment. The relatively short length of the second fuse segment makes the second fuse segment a polycrystalline silicon narrow point. The polycrystalline region here has lower conductivity and is more prone to melting and electromigration. By forming a specific region, the melting point can be effectively controlled at this narrow point, and the stability and reliability of the adjustment results can be effectively improved.

[0064] As an example, the second fuse segment can be located at halfway point of the polysilicon fuse, at the golden ratio point (0.618 ratio point or 0.382 ratio point) or other suitable positions, so that there are sufficient chemical reaction diffusion areas on both sides of the second fuse segment. This can avoid the phenomenon of fuse device breaking and reconnecting as mentioned above, thereby effectively improving the data stability before and after the memory cell is programmed and preventing data loss due to breaking and reconnecting.

[0065] For example, please refer to Figure 3 The image shows a layout of the memory cell, including a first ion implantation region 201 and a second ion implantation region 202 spaced apart, and includes a polysilicon layer, a contact layer, and a second conductive material layer. A slit is formed between the first ion implantation region 201 and the second ion implantation region 202. The polysilicon layer includes a first doped polysilicon connector 203a, a polysilicon fuse 203b, and a second doped polysilicon connector 203c connected in sequence. The first doped polysilicon connector 203a is located in the first ion implantation region 201, and the second doped polysilicon connector 203c is located in the second ion implantation region 202. The polysilicon fuse 203b includes a first fuse segment connected in sequence. The second fuse segment and the third fuse segment are provided. The first fuse segment is located in the first ion implantation region 201, the second fuse segment is located in the slit between the first ion implantation region 202 and the second ion implantation region 202, and the third fuse segment is located in the second ion implantation region 202. The contact layer includes at least one first contact portion 204a on the first doped polysilicon connection portion 203a and at least one second contact portion 204b on the second doped polysilicon connection portion 203c. The second conductive material layer includes a second conductive material layer 205a on the first contact portion 204a and a second conductive material layer 205b on the second contact portion 204b.

[0066] As an example, such as Figure 3 As shown, the second doped polysilicon connection portion 203c has a width gradient section, which is connected to the polysilicon fuse 203b and gradually increases in width in the direction away from the polysilicon fuse 203b.

[0067] As an example, the storage cell further includes a first conductive material layer 211 located on the upper surface of the polysilicon layer. Figure 3 Not shown in the image. Figure 4(As illustrated), to reduce the contact resistance of the polycrystalline silicon layer, the material of the first conductive material layer 211 may include metal silicide, polycrystalline silicon, or other suitable conductive materials. In this embodiment, the first conductive material layer 211 is preferably made of metal silicide. During the formation of the metal silicide, the exposed silicon surface of the polycrystalline silicon layer is covered by metal silicide, that is, the metal silicide completely covers the polycrystalline silicon layer.

[0068] As an example, such as Figure 3 As shown, the storage unit further includes a conductive cover layer 206 located above the polysilicon fuse 203c. The vertical projection of the conductive cover layer 206 onto the plane where the polysilicon fuse 203c is located at least blocks the second fuse segment. In this embodiment, the vertical projection of the conductive cover layer 206 onto the plane where the polysilicon fuse 203c is located blocks the entire polysilicon fuse 203b and also blocks the width gradient section of the second doped polysilicon connection portion 203c. The conductive cover layer 206 is made of conductive metal or polysilicon, which can effectively block the data storage portion of the storage unit and effectively improve the data confidentiality of the storage unit.

[0069] As an example, such as Figure 3 As shown, the storage unit further includes a first well region 207, and the vertical projection of the second fuse segment of the polysilicon fuse 203b is located within the first well region 207.

[0070] For example, please refer to Figure 4 and Figure 5 All are shown as three-dimensional structural cross-sectional views of the storage unit. Compared with the layout description, the three-dimensional structural cross-sectional views more clearly show the actual situation of the present invention. Figure 4 In the middle, the conductive cover layer 206a is made of conductive metal. Figure 5 In the middle, the conductive capping layer 206b is made of polycrystalline silicon.

[0071] Specifically, such as Figure 4 and Figure 5 As shown, the memory cell further includes a substrate 208 and an isolation dielectric layer 209. The polysilicon layer 203 is located on the isolation dielectric layer 209, and the polysilicon layer 203 includes a first doped polysilicon region 203d, an undoped polysilicon region 203e, and a second doped polysilicon region 203f. The first doped polysilicon region 203d includes a first doped polysilicon connection portion 203a and the first fuse segment of the polysilicon fuse 203b. The undoped polysilicon region 203e serves as the second fuse segment of the polysilicon fuse 203b. The second doped polysilicon region 203f includes the third fuse segment of the polysilicon fuse 203b and the second doped polysilicon connection portion 203c.

[0072] As an example, such as Figure 4 and Figure 5 As shown, a second well region 210 is provided in the substrate 208, and a first well region 207 is located in the second well region 210. The doping type of the first well region 207 is opposite to that of the second well region 210. The vertical projection of the second fuse segment of the polysilicon fuse 203b on the substrate 208 is located within the first well region 207. The doping type of the first well region 207 is opposite to that of the substrate 208, and the doping type of the second well region 210 is the same as that of the substrate 208.

[0073] As an example, such as Figure 4 and Figure 5 As shown, the memory cell further includes a first conductive material layer 211 and an insulating dielectric layer 212. The first conductive material layer 211 is located on the upper surface of the polysilicon layer 203. The insulating dielectric layer 212 at least completely covers the upper surface of the first conductive layer 211. The second conductive material layer 205a is electrically connected to the first conductive layer 211 through a first contact portion 204a penetrating the insulating dielectric layer 212, and the second conductive material layer 205b is electrically connected to the first conductive layer 211 through a second contact portion 204b penetrating the insulating dielectric layer 212. A conductive cover layer 206a is provided on the upper surface of the insulating dielectric layer 212.

[0074] As an example, such as Figure 4 As shown, the conductive cover layer 206a, made of conductive metal, extends above the second conductive material layer 205a and is electrically connected to the first and second conductive material layers 205a through a third contact portion 213 penetrating the insulating dielectric layer 212; as Figure 5 As shown, the conductive capping layer 206b, made of polycrystalline silicon, is located horizontally between the second conductive material layer 205a and the second conductive material layer 205b.

[0075] It should be noted that the various details of the layout and three-dimensional structure can be adjusted as needed, and are not limited to... Figure 3 , Figure 4 and Figure 5 The above is for reference only. Additionally, Figure 4 and Figure 5 The insulating dielectric layer 212 described in the figure is not fully illustrated. In fact, insulating dielectrics are provided between the contact parts and between different conductive layers.

[0076] In this embodiment of the polysilicon fuse-type non-volatile memory, the polysilicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first and third fuse segments are both made of doped polysilicon, while the second fuse segment is made of intrinsic polysilicon. The second fuse segment forms an intrinsic polysilicon narrow point, effectively controlling the melting point at this narrow point, thus significantly improving the stability and reliability of the tuning results. Simultaneously, this structure can effectively improve the data stability before and after programming the memory cell, preventing data loss due to reconnection after a break. Furthermore, the upper region of this structure cleverly utilizes a conductive capping layer made of conductive metal or polysilicon to shield the data storage portion of the memory cell, effectively improving the data confidentiality of the memory cell.

[0077] Example 2

[0078] This embodiment provides a method for fabricating a polysilicon fuse-type non-volatile memory, including the following steps:

[0079] S1: Formation of an intrinsic polycrystalline silicon layer;

[0080] S2: Ion implantation is performed on a preset region of the intrinsic polysilicon layer to obtain a polysilicon fuse. The polysilicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the third fuse segment are both made of doped polysilicon, and the second fuse segment is made of intrinsic polysilicon.

[0081] As an example, in step S2, the ion implantation is performed using a mask with at least an opening pattern of a first ion implantation region and an opening pattern of a second ion implantation region, wherein the opening of the first ion implantation region exposes the first fuse segment, the opening of the second ion implantation region exposes the third fuse segment, and the second fuse segment is covered by the mask.

[0082] As an example, the length of the second fuse segment is less than the length of the first fuse segment, and the length of the second fuse segment is less than the length of the third fuse segment.

[0083] As an example, the second fuse segment is located at the halfway point of the polysilicon fuse, the golden section point, or other suitable positions so that there is sufficient chemical reaction diffusion area on both sides of the second fuse segment. This can avoid the phenomenon of disconnection and reconnection, thereby effectively improving the data stability before and after the memory cell is programmed and preventing data loss due to disconnection and reconnection.

[0084] As an example, the method further includes the step of forming a conductive capping layer over the polysilicon fuse, wherein the conductive capping layer, in its vertical projection onto the plane of the polysilicon fuse, shields the second fuse segment. The conductive capping layer is made of conductive metal or polysilicon, effectively shielding the data storage portion of the storage unit and significantly improving the data security of the storage unit.

[0085] As an example, the method further includes the following steps: forming a first conductive material layer on the upper surface of the intrinsic polysilicon layer, forming an insulating dielectric layer on the upper surface of the first conductive material layer, wherein the conductive capping layer is formed on the upper surface of the insulating dielectric layer. The first conductive material layer can reduce the contact resistance between the polysilicon and the contact portion.

[0086] As an example, when ion implantation is performed on a preset region of the intrinsic polysilicon layer, doped polysilicon connectors are also obtained at both ends of the polysilicon fuse, so that electrical signals can be applied to both ends of the polysilicon fuse through the doped polysilicon connectors.

[0087] As an example, it also includes forming a second conductive material layer that is electrically connected to the doped polysilicon interconnect.

[0088] As an example, the method further includes the following steps: providing a substrate, forming an isolation dielectric layer on the substrate, and forming the intrinsic polysilicon layer on the isolation dielectric layer.

[0089] As an example, the method further includes the following steps: forming a first well region and a second well region in the substrate, the first well region being located in the second well region, the vertical projection of the second fuse segment of the polysilicon fuse on the substrate being located in the first well region, the doping type of the first well region being opposite to the doping type of the substrate, and the doping type of the second well region being the same as the doping type of the substrate.

[0090] In summary, the polycrystalline fuse-type non-volatile memory and its fabrication method of the present invention utilize ion implantation to dope the polycrystalline material, creating a sandwich-like polycrystalline region: a low-resistivity polycrystalline region + an intrinsic polycrystalline narrow point + a low-resistivity polycrystalline region. This structure effectively controls the programming location of the memory cell, preventing the fuse point from occurring at either end and limiting it to the vicinity of the polycrystalline narrow point. This deterministic and controllable fuse location effectively improves the resistance distribution of the memory cell after programming, reducing the dispersion of the resistance distribution and enhancing the robustness of the design. It also increases the design width of the window interval between the "0" and "1" states of the cell. Furthermore, this structure effectively improves the data stability of the memory cell before and after programming, preventing data loss due to reconnection after a break. In addition, the upper region of this structure cleverly utilizes a metal layer or polycrystalline layer to shield the data storage portion of the memory cell, effectively improving data confidentiality. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A polycrystalline fuse-type non-volatile memory, comprising multiple memory cells, characterized in that: The memory unit includes a polysilicon fuse, which includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the three fuse segments are all made of doped polysilicon, and the second fuse segment is made of intrinsic polysilicon. The memory unit further includes a conductive cover layer located above the polysilicon fuse, the conductive cover layer shielding the second fuse segment from its vertical projection onto the plane where the polysilicon fuse is located; the material of the conductive cover layer includes conductive metal or polysilicon. The memory unit further includes a first conductive material layer and an insulating dielectric layer. The first conductive material layer is located on the upper surface of the polysilicon fuse, the insulating dielectric layer is located on the upper surface of the first conductive material layer, and the conductive cover layer is located on the upper surface of the insulating dielectric layer.

2. The polysilicon fuse-type non-volatile memory according to claim 1, characterized in that: The length of the second fuse segment is less than the length of the first fuse segment, and the length of the second fuse segment is less than the length of the third fuse segment.

3. The polysilicon fuse-type non-volatile memory according to claim 1, characterized in that: The second fuse segment is located at the halfway point or the golden section point of the polycrystalline silicon fuse.

4. The polysilicon fuse-type non-volatile memory according to claim 1, characterized in that: The memory unit further includes a doped polysilicon connection portion connected to both ends of the polysilicon fuse and a second conductive material layer electrically connected to the doped polysilicon connection portion.

5. The polysilicon fuse-type non-volatile memory according to claim 1, characterized in that: The memory cell further includes a substrate and an isolation dielectric layer located on the substrate, wherein the polysilicon fuse is located on the isolation dielectric layer.

6. The polysilicon fuse-type non-volatile memory according to claim 5, characterized in that: The substrate has a first well region and a second well region, the first well region is located in the second well region, the vertical projection of the second fuse segment of the polysilicon fuse on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is the same as the doping type of the substrate.

7. A method for fabricating a polysilicon fuse-type non-volatile memory, characterized in that, Includes the following steps: Forming an intrinsic polycrystalline silicon layer; Ion implantation is performed on a predetermined region of the intrinsic polycrystalline silicon layer to obtain a polycrystalline silicon fuse. The polycrystalline silicon fuse includes a first fuse segment, a second fuse segment, and a third fuse segment connected in sequence. The first fuse segment and the three fuse segments are all made of doped polycrystalline silicon, and the second fuse segment is made of intrinsic polycrystalline silicon. The method further includes the following steps: forming a first conductive material layer on the upper surface of the intrinsic polysilicon layer, forming an insulating dielectric layer on the upper surface of the first conductive material layer, forming a conductive capping layer on the upper surface of the insulating dielectric layer, wherein the conductive capping layer blocks the second fuse segment in the vertical projection of the plane where the polysilicon fuse is located; the material of the conductive capping layer includes conductive metal or polysilicon.

8. The method for fabricating a polysilicon fuse-type non-volatile memory according to claim 7, characterized in that, The ion implantation of the predetermined region of the intrinsic polysilicon layer includes: performing the ion implantation using a mask having at least an opening pattern of a first ion implantation region and an opening pattern of a second ion implantation region, wherein the opening of the first ion implantation region exposes the first fuse segment, the opening of the second ion implantation region exposes the third fuse segment, and the second fuse segment is covered by the mask.

9. The method for fabricating a polysilicon fuse-type non-volatile memory according to claim 7, characterized in that, It also includes the following steps: A substrate is provided, and an isolation dielectric layer is formed on the substrate, wherein the intrinsic polysilicon layer is formed on the isolation dielectric layer.

10. The method for fabricating a polycrystalline fuse-type non-volatile memory according to claim 9, characterized in that, It also includes the following steps: A first well region and a second well region are formed in the substrate, the first well region is located in the second well region, the vertical projection of the second fuse segment of the polysilicon fuse on the substrate is located in the first well region, the doping type of the first well region is opposite to the doping type of the substrate, and the doping type of the second well region is the same as the doping type of the substrate.

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