Display substrate and display panel

Abstract

A display substrate and a display panel. The display substrate comprises: a base substrate (10); a plurality of sub-pixels (12) arranged on the base substrate (10); each of the plurality of sub-pixels (12) comprises a light-emitting element (121) and a pixel circuit (120) for driving the light-emitting element to emit light; the pixel circuit (120) comprises a driving sub-circuit (200), a data writing sub-circuit (230), a threshold compensation sub-circuit (240), an anti-leakage electronic circuit (270) and a storage sub-circuit (280); the storage sub-circuit (280) comprises a storage capacitor (Cst1); the storage capacitor comprises a first electrode plate (CC1), a second electrode plate (CC2) and a third electrode plate (CC3); the first electrode plate (CC1) and the third electrode plate (CC3) are electrically connected to each other and are located in different layers relative to the base substrate; the second electrode plate (CC2) at least partially overlaps with the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate. The display substrate can increase the size of the storage capacitor without increasing the occupied space.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display panel. Background Art

[0002] With the rapid development of organic light-emitting diodes (OLEDs) in the display field, people's requirements for display effects are becoming increasingly higher. Due to their advantages such as high display quality, the application range of high-resolution display devices is also expanding. In the display field, a key technology is the design of pixel circuits. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; wherein each of the plurality of sub-pixels comprises a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, and the pixel circuit comprises a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, an anti-leakage electronic circuit and a storage sub-circuit; the driving sub-circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light-emitting element; the data writing sub-circuit is connected to the first terminal, the data line and the scan signal line of the driving sub-circuit, and is configured to write the data signal provided by the data line into the first terminal of the driving sub-circuit in response to a gate scan signal provided by the scan signal line; the threshold compensation sub-circuit is connected to the second terminal of the driving sub-circuit, the anti-leakage electronic circuit and the scan signal line, and is configured to respond to the gate scan signal provided by the scan signal line. The gate scanning signal provided by the scanning signal line writes the compensation signal based on the data signal into the control end of the driving sub-circuit; the anti-leakage electronic circuit is connected to the control end of the driving sub-circuit, the threshold compensation sub-circuit, the storage sub-circuit and the anti-leakage control signal line, and is configured to suppress leakage of the control end of the driving sub-circuit; the storage sub-circuit is connected to the control end and the first voltage line of the driving sub-circuit, and is configured to store the compensation signal and maintain it at the control end of the driving sub-circuit, wherein the storage sub-circuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are located in different layers relative to the base substrate, and the second electrode plate at least partially overlaps with the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the second electrode plate is located between the first electrode plate and the third electrode plate; the first electrode plate is connected to the control end of the driving sub-circuit, the second electrode plate is connected to the first voltage line, and the third electrode plate is connected to the control end of the driving sub-circuit.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the threshold compensation sub-circuit includes a threshold compensation transistor, and the data writing sub-circuit includes a data writing transistor; the active layer of the threshold compensation transistor and the active layer of the data writing transistor are formed integrally, and the positive projections of the active layer of the threshold compensation transistor and the active layer of the data writing transistor on the base substrate are respectively located on both sides of the positive projection of the storage capacitor on the base substrate; the gate of the threshold compensation transistor and the gate of the data writing transistor are parallel in a first direction, and the gate of the threshold compensation transistor and the gate of the data writing transistor are formed integrally with the scanning signal line.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the leakage prevention electronic circuit includes an leakage prevention transistor, the active layer of the leakage prevention transistor, the active layer of the threshold compensation transistor and the active layer of the data writing transistor all extend along the second direction and are arranged side by side along the first direction, and the first direction and the second direction intersect; the orthographic projection of the active layer of the leakage prevention transistor on the base substrate is located on the side of the orthographic projection of the active layer of the threshold compensation transistor on the base substrate away from the orthographic projection of the active layer of the data writing transistor on the base substrate.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the gate of the anti-leakage transistor and the anti-leakage control signal line are formed integrally, the anti-leakage control signal line extends along the first direction, and the orthographic projection of the anti-leakage control signal line on the base substrate is located between the orthographic projection of the scanning signal line on the base substrate and the orthographic projection of the storage capacitor on the base substrate.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the anti-leakage control signal line includes a first sub-control signal line and a second sub-control signal line, and the orthographic projection of the first sub-control signal line on the base substrate and the orthographic projection of the second sub-control signal line on the base substrate at least partially overlap.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the gate of the anti-leakage transistor includes a first gate and a second gate, the first gate is formed integrally with the first sub-control signal line, and the second gate is formed integrally with the second sub-control signal line, and in a direction perpendicular to the base substrate, the active layer of the anti-leakage transistor is located between the first gate and the second gate.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the active layer of the anti-leakage transistor and the third electrode plate are located on the same layer; the material of the active layer of the anti-leakage transistor and the third electrode plate includes oxide semiconductor material.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel circuit also includes a first reset sub-circuit; wherein, the first reset sub-circuit is connected to the threshold compensation sub-circuit, the anti-leakage electronic circuit, the first initial signal line and the first reset control signal terminal, and is configured to apply the initial voltage provided by the first initial signal line to the control terminal of the driving sub-circuit through the anti-leakage electronic circuit in response to the reset control signal received by the first reset control signal terminal.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first reset sub-circuit includes a first reset transistor; the active layer of the first reset transistor is integrally formed with the active layer of the threshold compensation transistor; the orthographic projection of the active layer of the first reset transistor on the base substrate is located on a side of the orthographic projection of the active layer of the threshold compensation transistor on the base substrate away from the orthographic projection of the storage capacitor on the base substrate.

[0013] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a first connecting electrode, wherein the first end of the first connecting electrode is integrally formed with the first electrode of the first reset transistor and the first electrode of the threshold compensation transistor, and is respectively connected to the active layer of the threshold compensation transistor and the active layer of the first reset transistor through a via hole penetrating the insulating layer; the second end of the first connecting electrode is integrally formed with the first electrode of the anti-leakage transistor, and is connected to the active layer of the anti-leakage transistor through a via hole penetrating the insulating layer.

[0014] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a second connecting electrode, wherein the first end of the second connecting electrode is integrally formed with the second electrode of the anti-leakage transistor, and is connected to the active layer of the anti-leakage transistor through a via hole penetrating the insulating layer; the second end of the second connecting electrode is connected to the first electrode plate of the storage capacitor through a via hole penetrating the insulating layer; and the third end of the second connecting electrode is connected to the third electrode plate of the storage capacitor through a via hole penetrating the insulating layer.

[0015] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a parasitic capacitor, which is connected to the second electrode of the anti-leakage transistor and the scanning signal line; wherein, the first electrode plate of the parasitic capacitor is formed integrally with the scanning signal line, the second electrode plate of the parasitic capacitor and the first electrode plate of the parasitic capacitor at least partially overlap in a direction perpendicular to the base substrate, the second electrode plate of the parasitic capacitor and the third electrode plate of the storage capacitor are located on the same layer, and the orthographic projection of the second electrode plate of the parasitic capacitor on the base substrate is located between the orthographic projection of the active layer of the threshold compensation transistor on the base substrate and the orthographic projection of the active layer of the data writing transistor on the base substrate; the second electrode plate of the parasitic capacitor is connected to the fourth end of the second connecting electrode through a via hole penetrating the insulating layer.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the driving subcircuit includes a driving transistor, and the gate of the driving transistor is integrally formed with the first electrode plate of the storage capacitor; the active layer of the driving transistor, the active layer of the data writing transistor and the active layer of the threshold compensation transistor are integrally formed, and the orthographic projection of the active layer of the driving transistor on the base substrate is located between the orthographic projection of the active layer of the data writing transistor on the base substrate and the orthographic projection of the active layer of the threshold compensation transistor on the base substrate.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, the first light-emitting control subcircuit is connected to the first voltage line, the first end of the driving subcircuit and the light-emitting control signal line, and is configured to apply the first voltage provided by the first voltage line to the first end of the driving subcircuit in response to the light-emitting control signal provided by the light-emitting control signal line; the second light-emitting control subcircuit is connected to the second end of the driving subcircuit, the first end of the light-emitting element and the light-emitting control signal line, and is configured to respond to the light-emitting control signal provided by the light-emitting control signal line so that the driving current is applied to the first end of the light-emitting element; wherein the light-emitting control signal line extends along the first direction, and the orthographic projection of the light-emitting control signal line on the substrate is located on the side of the orthographic projection of the storage capacitor on the substrate away from the orthographic projection of the scanning signal line on the substrate.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first light-emitting control subcircuit includes a first light-emitting control transistor, and the second light-emitting control subcircuit includes a second light-emitting control transistor; the active layer of the first light-emitting control transistor, the active layer of the second light-emitting control transistor, the active layer of the data writing transistor, the active layer of the threshold compensation transistor and the active layer of the driving transistor are formed integrally, and the orthographic projection of the active layer of the driving transistor on the base substrate is located between the orthographic projection of the active layer of the data writing transistor and the active layer of the first light-emitting control transistor on the base substrate and the orthographic projection of the active layer of the second light-emitting control transistor and the active layer of the threshold compensation transistor on the base substrate.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the anti-leakage control signal provided by the anti-leakage control signal line is the same as or different from the light-emitting control signal provided by the light-emitting control signal line.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first voltage line includes a first sub-voltage line extending along the second direction and a second sub-voltage line extending along the first direction, and the first sub-voltage line and the second sub-voltage line are located in different layers; the orthographic projection of the first sub-voltage line on the base substrate is located between the orthographic projection of the active layer of the data writing transistor on the base substrate and the orthographic projection of the active layer of the threshold compensation transistor on the base substrate, and at least partially overlaps with the orthographic projection of the second electrode plate of the parasitic capacitor on the base substrate; the second sub-voltage line is formed integrally with the second electrode plate of the storage capacitor.

[0021] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a third connecting electrode, wherein the first end of the third connecting electrode is integrally formed with the first electrode of the first light-emitting control transistor, and is connected to the active layer of the first light-emitting control transistor through a via hole penetrating the insulating layer, the second end of the third connecting electrode is connected to the second electrode plate of the storage capacitor through the via hole penetrating the insulating layer; the third end of the third connecting electrode is connected to the first protrusion of the first sub-voltage line through the via hole penetrating the insulating layer.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first sub-voltage line also includes a second protrusion, the second protrusion is in the shape of a "U". The orthographic projection of the second protrusion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the anti-leakage transistor on the base substrate.

[0023] At least one embodiment of the present disclosure further provides a display panel, comprising the display substrate as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] Figure 1 A schematic block diagram of a display substrate provided for some embodiments of the present disclosure;

[0026] Figure 2A A schematic structural diagram of a pixel circuit provided in some embodiments of the present disclosure;

[0027] Figure 2B A circuit timing diagram of a pixel circuit provided in some embodiments of the present disclosure;

[0028] Figure 2C A circuit timing diagram of another pixel circuit provided in some embodiments of the present disclosure;

[0029] Figure 3 A schematic diagram of a layout of a pixel circuit provided in some embodiments of the present disclosure;

[0030] Figures 4A-4O A schematic diagram of various structural layers of a pixel circuit provided in some embodiments of the present disclosure;

[0031] Figure 5A for Figure 3 Schematic diagram of the cross-sectional structure splicing corresponding to the second light-emitting control transistor, the anti-leakage transistor and the storage capacitor;

[0032] Figure 5B Another cross-sectional schematic diagram provided for some embodiments of the present disclosure;

[0033] Figure 5C Another cross-sectional schematic diagram provided for some embodiments of the present disclosure;

[0034] Figure 6 A schematic diagram of a partial structural stacking provided for some embodiments of the present disclosure;

[0035] Figure 7 A schematic diagram of a partial structural stacking provided for some embodiments of the present disclosure;

[0036] Figure 8 A schematic diagram of a partial structural stack-up provided for some embodiments of the present disclosure; and

[0037] Figure 9 A schematic diagram of a display panel provided according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0040] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0041] When operating pixel circuits based on LTPS (Low Temperature Poly-silicon), the stability of the gate voltage of the driving transistor (DTFT) is crucial, as this gate voltage stability impacts display quality, such as display uniformity and flicker. In existing LTPS-based pixel circuits, the leakage current of the compensation transistor (STFT) cannot meet the requirements of low-frequency operation (1-30Hz), resulting in reduced compensation capability and display issues such as increased flicker.

[0042] Oxide semiconductor thin-film transistors (Oxide TFTs) have the characteristics of good hysteresis characteristics and low leakage current (below 1e-14A), while also having low mobility, which can compensate for the above shortcomings. Therefore, oxide semiconductor thin-film transistors can be used to replace the compensation transistor STFT prepared based on LTPS to achieve low leakage performance and ensure the stability of the gate voltage of the driving transistor DTFT. However, based on the existing process, the size of the oxide semiconductor thin-film transistor is larger than the transistor prepared based on LTPS, and the film layer is different, which involves adding vias, insulating layers and other problems. There are difficulties in pixel layout and improvement is needed.

[0043] Furthermore, in the display industry, demand for higher resolution is increasing, leading to a trend toward higher pixel density (Pixels Per Inch, PPI) in display panels. For example, mainstream displays have resolutions exceeding 460 PPI. This high pixel density reduces the layout space for pixels, resulting in smaller pixel storage capacitors. However, this smaller storage capacitor destabilizes the gate potential of the drive transistor, affecting display uniformity and causing flicker.

[0044] At least some embodiments of the present disclosure provide a display substrate and a display panel, wherein the display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate; each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit including a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, an anti-leakage electronic circuit and a storage sub-circuit; the driving sub-circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light-emitting element; the data writing sub-circuit is connected to the first terminal of the driving sub-circuit, a data line and a scan signal line, and is configured to write a data signal provided by the data line to the first terminal of the driving sub-circuit in response to a gate scan signal provided by the scan signal line; the threshold compensation sub-circuit is connected to the second terminal of the driving sub-circuit, the anti-leakage electronic circuit and the scan signal line The storage subcircuit is connected and configured to write a compensation signal based on the data signal into the control end of the driving subcircuit in response to a gate scanning signal provided by the scanning signal line; the leakage prevention electronic circuit is connected to the control end of the driving subcircuit, the threshold compensation subcircuit, the storage subcircuit and the leakage prevention control signal line, and is configured to suppress leakage of the control end of the driving subcircuit; the storage subcircuit is connected to the control end of the driving subcircuit and the first voltage line, and is configured to store the compensation signal and maintain it at the control end of the driving subcircuit, the storage subcircuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are located in different layers relative to the substrate, and the second electrode plate at least partially overlaps with the first electrode plate and the third electrode plate in a direction perpendicular to the substrate.

[0045] In the display substrate provided in the embodiment of the present disclosure, by adopting a storage capacitor with at least three layers of electrode plates in the pixel circuit, the size of the storage capacitor can be effectively increased without increasing the occupancy, the capacitance value of the storage capacitor can be increased, and the gate potential stability of the driving transistor can be improved, thereby alleviating the problem of insufficient pixel capacitance under high pixel density requirements.

[0046] Several embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0047] Figure 1A schematic block diagram of a display substrate provided in some embodiments of the present disclosure is provided. Figure 2A A schematic structural diagram of a pixel circuit provided in some embodiments of the present disclosure is shown. Figure 2B A circuit timing diagram of a pixel circuit provided in some embodiments of the present disclosure.

[0048] For example, Figure 1 As shown, the display substrate 100 provided by the embodiment of the present disclosure includes a base substrate 10 and a plurality of sub-pixels 12, a first voltage line, a data line, a scanning signal line, a light emitting control signal line, an initial signal line and an anti-leakage control signal line arranged on the base substrate 10. It should be noted that, Figure 1 The first voltage line, the data line, the scan signal line, the light emitting control signal line, the initial signal line, and the leakage prevention control signal line are not shown.

[0049] For example, the display substrate 100 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel, etc. The display substrate 100 may be an array substrate.

[0050] For example, the base substrate 10 may be a flexible substrate or a rigid substrate. For example, the base substrate 10 may be made of glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0051] For example, each sub-pixel 12 includes a light-emitting element 121 and a pixel circuit 120 , and the light-emitting element 121 is located on a side of the pixel circuit 120 away from the base substrate 10 . Figure 1 The sub-pixel 12 shown is only for illustrating that each sub-pixel 12 includes two components: a light-emitting element 121 and a pixel circuit 120, and is not used to limit the positional relationship between the light-emitting element 121 and the pixel circuit 120. In some examples, the light-emitting element 121 and the pixel circuit 120 are arranged to overlap in a direction perpendicular to the base substrate 10.

[0052] For example, the pixel circuit 120 is configured to drive the light emitting element 121 to emit light. Figure 2A and Figure 2B The pixel circuit and its operating principle are explained.

[0053] For example, Figure 2A As shown, the pixel circuit 120 includes a driving subcircuit 200, a first reset subcircuit 210, a second reset subcircuit 220, a data writing subcircuit 230, a threshold compensation subcircuit 240, a first light-emitting control subcircuit 250, a second light-emitting control subcircuit 260, an anti-leakage electronic circuit 270 and a storage subcircuit 280.

[0054] For example, Figure 2AAs shown, the driving sub-circuit 200 includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the light-emitting element 121. For example, the control terminal of the driving sub-circuit 200 is connected to the first node N1, the first terminal is connected to the second node N2, and the second terminal is connected to the third node N3.

[0055] The data writing sub-circuit 230 is connected to the first end of the driving sub-circuit 200, the data line Vda and the scanning signal line Ga, and is configured to write the data signal provided by the data line Vda into the first end of the driving sub-circuit 200 in response to the gate scanning signal provided by the scanning signal line Ga.

[0056] The threshold compensation sub-circuit 240 is connected to the second end of the driving sub-circuit 200, the leakage prevention electronic circuit 270 and the scanning signal line Ga, and is configured to write a compensation signal based on the data signal into the control end of the driving sub-circuit 200 in response to the gate scanning signal provided by the scanning signal line Ga.

[0057] The leakage prevention circuit 270 is connected to the control terminal of the driving sub-circuit 200 , the threshold compensation sub-circuit 240 , the storage sub-circuit 280 and the leakage prevention control signal line EM2 , and is configured to suppress leakage at the control terminal of the driving sub-circuit 200 .

[0058] The first light-emitting control sub-circuit 250 is connected to the first voltage line VDD, the first end of the driving sub-circuit 200 and the light-emitting control signal line EM1, and is configured to apply the first voltage provided by the first voltage line VDD to the first end of the driving sub-circuit 200 in response to the light-emitting control signal provided by the light-emitting control signal line EM1.

[0059] The second light-emitting control sub-circuit 260 is connected to the second end of the driving sub-circuit 200, the first end of the light-emitting element 121 and the light-emitting control signal line EM1, and is configured to respond to the light-emitting control signal provided by the light-emitting control signal line EM1 so that the driving current is applied to the first end of the light-emitting element 121.

[0060] The first reset sub-circuit 210 is connected to the threshold compensation sub-circuit 240, the leakage prevention electronic circuit 270, the first initial signal line Vinit1 and the first reset control signal terminal Re1, and is configured to apply the initial voltage provided by the first initial signal line to the control terminal of the driving sub-circuit 200 through the leakage prevention electronic circuit 270 in response to the reset control signal received by the first reset control signal terminal Re1.

[0061] For example, when the first reset sub-circuit 240 transmits the initial voltage output by the first initial signal line Vinit1 to the control end of the driving sub-circuit 200 to initialize the control end of the driving sub-circuit 200, the anti-leakage electronic circuit 270 is configured to be turned on under the control of the anti-leakage control signal, so that the initial voltage is transmitted to the control end of the driving sub-circuit 200 (that is, the first node N1) via the anti-leakage electronic circuit 270 to initialize the control end of the driving sub-circuit 200.

[0062] The second reset sub-circuit 220 is connected to the second initial signal line Vinit2, the second reset control signal terminal Re2 and the first end of the light-emitting element 121, and is configured to apply the initial voltage provided by the second initial signal line Vinit2 to the first end of the light-emitting element 121 in response to the reset control signal received by the second reset control signal terminal Re2.

[0063] For example, the initial voltage provided by the first initial signal line Vinit1 and the initial voltage provided by the second initial signal line Vinit2 may be the same or different.

[0064] The storage sub-circuit 280 is connected to the control terminal of the driving sub-circuit 200 and the first voltage line VDD, and is configured to store the compensation signal and hold it at the control terminal of the driving sub-circuit 200 .

[0065] For example, the storage subcircuit 200 includes a storage capacitor Cst1, which includes a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate and the third electrode plate are electrically connected to each other and are located in different layers relative to the substrate. The second electrode plate at least partially overlaps with the first electrode plate and the third electrode plate in a direction perpendicular to the substrate. By setting at least three stacked electrode plates and electrically connecting the first electrode plate and the third electrode plate to each other, that is, the first electrode plate and the third electrode plate have the same potential and are different from the potential of the second electrode plate, a three-layer storage capacitor is formed. In this way, the area of the storage capacitor can be increased without increasing the occupied space, thereby increasing the capacitance value of the storage capacitor Cst1. For example, the capacitance value of the storage capacitor in the embodiment of the present disclosure can be increased by about 60% to 80% from the capacitance value of the existing two-layer capacitor. For example, a capacitance value of 60fF can be increased to a capacitance value of 96fF-108fF, for example, to 100fF. The embodiments of the present disclosure are not limited to this.

[0066] In an embodiment of the present disclosure, in a pixel circuit including a driving subcircuit 200, a first reset subcircuit 210, a second reset subcircuit 220, a data writing subcircuit 230, a threshold compensation subcircuit 240, a first light-emitting control subcircuit 250, a second light-emitting control subcircuit 260, an anti-leakage electronic circuit 270 and a storage subcircuit 280, a storage capacitor having at least three layers of electrode plates is used. This can effectively increase the size of the storage capacitor without increasing the occupied space, increase the capacitance value of the storage capacitor, and thereby improve the gate potential stability of the driving transistor, thereby alleviating the problem of insufficient storage capacitor under high pixel density requirements.

[0067] For example, the pixel circuit 120 may further include a parasitic capacitor Cst2, which is connected to the control terminal of the driver sub-circuit 200 and the scan signal line Ga, and is configured to adjust the voltage of the control terminal of the driver sub-circuit 200 in response to the scan signal provided by the scan signal line Ga. For example, according to the principle of charge conservation, the parasitic capacitor can increase the voltage of the control terminal of the driver sub-circuit 200 when the scan signal provided by the scan signal line Ga changes from a low level to a high level. The driving current of the pixel circuit is related to the voltage of the control terminal of the driver sub-circuit 200, and the voltage of the control terminal of the driver sub-circuit 200 is related to the data signal provided by the data line Vda. The voltage of the data signal provided by the data line Vda has an upper limit, such as about 6V or 7V. If a lower driving current is desired, the data line Vda needs to provide a higher data signal voltage. Therefore, in actual use, this requirement may exceed the upper limit of the data signal voltage, thereby failing to achieve the ideal driving current. However, if the parasitic capacitor Cst2 is used to increase the voltage of the control terminal of the driving sub-circuit 200, then the data line Vda can provide a slightly lower data signal voltage. Therefore, under the action of the parasitic capacitor Cst2, a lower driving current can also be achieved, avoiding the voltage requirement of the data signal exceeding its voltage upper limit and failing to achieve a lower driving current.

[0068] For example, Figure 2A As shown, the second electrode of the light emitting element 121 is electrically connected to the second voltage line VSS to receive the second voltage.

[0069] For example, the light-emitting element 121 may be a light-emitting diode, etc. The light-emitting diode may be a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) or a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), etc. The light-emitting element 121 is configured to receive a light-emitting signal (for example, a driving current) when in operation and emit light with an intensity corresponding to the light-emitting signal. The light-emitting element 121 may include a first electrode, a second electrode and a light-emitting layer arranged between the first electrode and the second electrode. The first electrode of the light-emitting element 121 may be an anode, and the second electrode of the light-emitting diode may be a cathode. It should be noted that in the embodiments of the present disclosure, the light-emitting layer of the light-emitting element may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer and an electron transport layer, etc. Generally, the light-emitting element 121 has a light-emitting threshold voltage, and emits light when the voltage between the first electrode and the second electrode of the light-emitting element 121 is greater than or equal to the light-emitting threshold voltage. In practical applications, the specific structure of the light emitting element 121 may be designed and determined according to the actual application environment, and is not limited here.

[0070] For example, Figure 2A As shown, the driving sub-circuit 200 includes a driving transistor T3, the first reset sub-circuit 210 includes a first reset transistor T1, the second reset sub-circuit 220 includes a second reset transistor T7, the data writing sub-circuit 230 includes a data writing transistor T4, the threshold compensation sub-circuit 240 includes a threshold compensation transistor T2, the first light-emitting control sub-circuit 250 includes a first light-emitting control transistor T5, the second light-emitting control sub-circuit 260 includes a second light-emitting control transistor T6, and the anti-leakage electronic circuit 270 includes an anti-leakage transistor T8.

[0071] The control terminal of the driver sub-circuit 200 includes the gate of the driver transistor T3, the first terminal of the driver sub-circuit 200 includes the first electrode of the driver transistor T3, and the second terminal of the driver sub-circuit 200 includes the second electrode of the driver transistor T3. The gate of the driver transistor T3 is electrically connected to the first node N1, the first electrode of the driver transistor T3 is electrically connected to the second node N2, and the second electrode of the driver transistor T3 is electrically connected to the third node N3.

[0072] The gate of the data writing transistor T4 is electrically connected to the scanning signal line Ga, the first electrode of the data writing transistor T4 is electrically connected to the data line Vda, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2, that is, electrically connected to the first electrode of the driving transistor T3.

[0073] The gate of the threshold compensation transistor T2 is electrically connected to the scan signal line Ga, the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the anti-leakage transistor T8, and the second electrode of the threshold compensation transistor T2 is electrically connected to the third node N3, that is, electrically connected to the second electrode of the driving transistor T3.

[0074] The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM1 to receive the light-emitting control signal, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first voltage line VDD to receive the first voltage, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2, that is, electrically connected to the first electrode of the driving transistor T3.

[0075] The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM1 to receive the light-emitting control signal, the first electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, that is, electrically connected to the first electrode of the light-emitting element 121, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, that is, electrically connected to the second electrode of the driving transistor T3.

[0076] The gate of the first reset transistor T1 is electrically connected to the first reset control signal terminal Re1, the first electrode of the first reset transistor T1 is electrically connected to the first electrode of the threshold compensation transistor T2 and the first electrode of the anti-leakage transistor T8, and the second electrode of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1.

[0077] The gate of the second reset transistor T7 is electrically connected to the second reset control signal terminal Re2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4, that is, electrically connected to the first electrode of the light emitting element 121.

[0078] The gate of the anti-leakage transistor T8 is electrically connected to the anti-leakage control signal line EM2, the first electrode of the anti-leakage transistor T8 is electrically connected to the first electrode of the threshold compensation transistor T2 and the first electrode of the first reset transistor T1, and the second electrode of the anti-leakage transistor T8 is electrically connected to the first node N1, that is, electrically connected to the gate of the driving transistor T3.

[0079] For example, when the anti-leakage transistor T8 is not provided in the pixel circuit, the leakage path of the gate of the driving transistor T3 is through transistors T1 and T2. To suppress leakage current, in some examples, the first reset transistor T1 and the threshold compensation transistor T2 can be configured as dual-gate transistors. When the anti-leakage transistor T8 is provided in the pixel circuit, the leakage path of the gate of the driving transistor T3 is through transistors T8-T1 and T8-T2. Compared with the leakage path of transistors T1 and T2 in the original pixel circuit, the leakage current of the path is lower. Since the leakage current of the anti-leakage transistor T8 is a key reference indicator, the first reset transistor T1 and the threshold compensation transistor T2 can be configured as single-gate transistors to save space. The anti-leakage transistor T8 can be an oxide semiconductor thin-film transistor (Oxide TFT). Oxide semiconductor thin-film transistors have good hysteresis characteristics and low leakage current (less than 1e-14A). At the same time, they have low mobility. Therefore, oxide semiconductor thin-film transistors can be used to ensure the stability of the gate voltage of the driving transistor.

[0080] For example, the first electrode plate CC1 and the third electrode plate CC3 of the storage capacitor Cst1 are both electrically connected to the control terminal of the driving sub-circuit 200, and the second electrode plate CC2 of the storage capacitor Cst1 is electrically connected to the first voltage line VDD to receive the first voltage. The second electrode plate is located between the first electrode plate and the third electrode plate in a direction perpendicular to the substrate.

[0081] For example, one of the voltage outputted by the first voltage line VDD and the voltage outputted by the second voltage line VSS is a high voltage, and the other is a low voltage. Figure 2A In the embodiment shown, the voltage output by the first voltage line VDD is a constant first voltage, which is a positive voltage; and the voltage output by the second voltage line VSS is a constant second voltage, which is a negative voltage, etc. For example, in some examples, the second voltage line VSS can be grounded.

[0082] It should be noted that the transistors adopted in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, polycrystalline silicon thin film transistors, etc. For example, in the description of the embodiments of the present disclosure, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the first reset transistor T1, and the second reset transistor T7 may all be low temperature poly-silicon (LTPS) thin film transistors, and the anti-leakage transistor T8 may be an oxide semiconductor thin film transistor. The source and drain of the transistor may be symmetric in structure, so there may be no difference in their physical structures. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. Therefore, the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0083] For example, in specific implementation, in the embodiments of the present disclosure, the initial voltage Vi output by the first initial signal line Vinit1 and the second initial signal line Vinit2 and the voltage Vs output by the second voltage line VSS may satisfy the following formula: Vi - Vs < VEL. VEL represents the light emission threshold voltage of the light emitting element 121. In some embodiments, the initial voltages of the first initial signal line Vinit1 and the second initial signal line Vinit2 may be different. For example, the initial voltage of the first initial signal line Vinit1 is less than the initial voltage of the second initial signal line Vinit2. For example, the initial voltage of the first initial signal line Vinit1 is 0.5V to 1V less than the initial voltage of the second initial signal line Vinit2.

[0084] For example, the first reset control signal terminal Re1 of the pixel circuit in the yth row (y is an integer greater than 1) and the second reset control signal terminal Re2 of the pixel circuit in the y-1th row are connected to the first reset signal line (not shown in the figure); the first reset control signal terminal Re1 of the pixel circuit in the y+1th row and the second reset control signal terminal Re2 of the pixel circuit in the yth row are connected to the second reset signal line (not shown in the figure). That is, each row of sub-pixels is connected to two reset signal lines (the first reset signal line and the second reset signal line) to connect to the first reset control signal terminal Re1 and the second reset control signal terminal Re2, respectively. For example, one reset signal line (e.g., the first reset signal line) is electrically connected to the gate of the first reset transistor T1 in the sub-pixels of the current row (i.e., the first reset control signal terminal Re1) to provide the first reset control signal. The first reset signal line is also electrically connected to the gate of the second reset transistor T7 in the sub-pixels of the previous row (i.e., the second reset control signal terminal Re2) to provide the second reset control signal to the sub-pixels of the previous row. Another reset signal line (e.g., the second reset signal line) is electrically connected to the gate of the first reset transistor T1 corresponding to the pixel circuit of the next row (i.e., the pixel circuit row where the scan line that is sequentially turned on after the scan signal line of the current row is located) to provide the first reset control signal to the sub-pixels of the next row. The second reset signal line is also electrically connected to the gate of the second reset transistor T7 in the pixel circuit of the current row (i.e., the second reset control signal terminal Re2). That is, every two adjacent rows of sub-pixels share one reset signal line.

[0085] For example, the second electrode of the first reset transistor T1 of the pixel circuit in the yth row (y is an integer greater than 1) and the first electrode of the second reset transistor T7 of the pixel circuit in the y-1th row are connected to the first initial signal line Vinit1; the second electrode of the first reset transistor T1 of the pixel circuit in the y+1th row and the first electrode of the second reset transistor T7 of the pixel circuit in the yth row are connected to the second initial signal line Vinit2. That is, each row of sub-pixels is connected to two corresponding initial signal lines (the first initial signal line and the second initial signal line) to respectively connect to the first reset transistor T1 and the second reset transistor T7. For example, one initial signal line (e.g., the first initial signal line Vinit1) is electrically connected to the first reset transistor T1 in the sub-pixels in the current row to provide a first initial voltage. The first initial signal line Vinit1 is also connected to the second reset transistor T7 in the sub-pixels in the previous row to provide a second initial signal for the sub-pixels in the previous row. Another initial signal line (e.g., the second initial signal line Vinit2) is electrically connected to the first reset transistor T1 corresponding to the pixel circuit in the next row (i.e., the pixel circuit row where the scan line that is sequentially turned on after the scan signal line in the current row is located) to provide a first initial control signal for the sub-pixels in the next row. The second initial signal line Vinit2 is also electrically connected to the second reset transistor T7 in the pixel circuit in the current row. That is, every two adjacent rows of sub-pixels share one initial signal line.

[0086] The following combination Figure 2B describe Figure 2A The working process of the pixel circuit shown.

[0087] For example, Figure 2B As shown, Re1 represents a first reset control signal provided by a first reset control signal line, Re2 represents a second reset control signal provided by a second reset control signal line, Ga represents a gate scan signal output by a scan signal line Ga, EM1 represents a light-emission control signal output by a light-emission control signal line EM1, EM2 represents an anti-leakage control signal output by an anti-leakage control signal line EM2, and Vda represents a data signal output by a data line Vda. It should be noted that in the embodiments of the present disclosure, the reference numerals Re1, Re2, Ga, EM1, EM2, Vda, and VDD represent both signal lines and signals on the signal lines.

[0088] For example, the working process of a pixel circuit in a display frame includes three phases: an initialization phase T10 , a data writing and compensation phase T20 , and a light emitting phase T30 .

[0089] During initialization phase T10, the first reset control signal Re1 and the second reset control signal Re2 are at a low level, while the light-emission control signal EM1, the leakage prevention control signal EM2, and the gate scan signal Ga are at a high level. The first reset transistor T1 is turned on by the low level of the first reset control signal Re1, and the leakage prevention transistor T8 is turned on by the high level of the leakage prevention control signal EM2. This allows the initial voltage transmitted on the first initialization signal line Vinit1 to be supplied to the gate of the driving transistor T1, thereby initializing the gate of the driving transistor T1. Simultaneously, the second reset transistor T7 is turned on by the second reset control signal Re2, so that the initial voltage output by the second initialization signal line Vinit2 is supplied to the first electrode of the light-emitting element 121, thereby initializing the first electrode of the light-emitting element 121. Furthermore, during this phase, the first and second light-emission control transistors T5 and T6 are turned off by the high level of the light-emission control signal EM1, and the data write transistor T4 is turned off by the high level of the scan signal Ga.

[0090] During the data writing and compensation phase T20, the first and second reset control signals Re1 and Re2 are at a high level, the emission control signal EM1 and the anti-leakage control signal EM2 are at a high level, and the gate scan signal Ga is at a low level. The data writing transistor T4 and the threshold compensation transistor T2 are both turned on in response to the low level of the gate scan signal Ga. Furthermore, the anti-leakage transistor T8 is turned on in response to the high level of the anti-leakage control signal EM2, allowing the data signal Vda transmitted on the data line to charge the gate of the driving transistor T3 until the gate voltage of the driving transistor T3 reaches Vda + Vth. The gate voltage Vda + Vth of the driving transistor T3 is stored in the storage capacitor Cst1. Vth represents the threshold voltage of the driving transistor T3, and Vda represents the voltage of the data signal. Furthermore, during this phase, the first reset transistor T1 is turned off in response to the low level of the first reset control signal Re1, the second reset transistor T7 is turned off in response to the low level of the second reset control signal Re2, and the first and second emission control transistors T5 and T6 are both turned off in response to the high level of the emission control signal EM1.

[0091] During light-emitting phase T30, the first and second reset control signals Re1 and Re2 are at a high level, the light-emitting control signal EM1 and the leakage prevention control signal EM2 are at a low level, and the gate scan signal Ga is at a high level. In response to the low level of the light-emitting control signal EM1, both the first and second light-emitting control transistors T5 and T6 are turned on. The turned-on first light-emitting control transistor T5 supplies the voltage of the first voltage line VDD to the first electrode of the driving transistor T3, causing the voltage of the first electrode of the driving transistor T3 to be VDD and the voltage of the gate of the driving transistor T3 to be Vda + Vth. This saturates the driving transistor T3, causing the driving transistor T3 to generate a driving current Ids: Ids = K*((Vda + Vth - VDD) - Vth)² = K*(Vda - VDD)², where K is a structural constant related to process and design. This driving current Ids is supplied to the light-emitting element 121 via the turned-on second light-emitting control transistor T6, driving the light-emitting element 121 to emit light. Furthermore, during this phase, the first reset transistor T1 is turned off in response to the low level of the first reset control signal Re1, and the second reset transistor T7 is turned off in response to the low level of the second reset control signal Re2. The data write transistor T2 and the threshold compensation transistor T4 are both turned off in response to the high level of the gate scan signal Ga. The leakage prevention transistor T8 is turned off in response to the low level of the leakage prevention control signal EM2.

[0092] In another embodiment, when a parasitic capacitor Cst2 is provided in the pixel circuit, during the light-emitting stage T30, when the gate scanning signal Ga jumps from a low level to a high level, according to the principle of charge conservation of capacitance, the gate of the driving transistor T3 is coupled to the gate through the parasitic capacitor Cst2, causing the gate voltage of the driving transistor T3 to increase, for example, by Vcs, where Vcs is, for example, 0.4 V to 0.5 V. Since Vda + Vth is less than VDD in the above-mentioned calculation formula for Ids, and therefore Vda + Vth - VDD is a negative value, if the gate voltage of the driving transistor T3 increases by Vcs on the basis of Vda + Vth, the absolute value of Vda + Vth + Vcs - VDD is less than the absolute value of Vda + Vth - VDD, thereby reducing the driving current Ids.

[0093] The driving current Ids is related to the data signal Vda. The voltage upper limit of the data signal provided by the data line Vda is, for example, around 6V or 7V. If a lower driving current is to be achieved, the data line Vda needs to provide a higher data signal voltage, which may exceed the voltage upper limit of the data signal during actual use. After adding the parasitic capacitor Cst2, the parasitic capacitor Cst2 is used to increase the voltage of the gate of the driving transistor T3 during the light-emitting stage T30, so that the data line Vda can provide a slightly lower data signal voltage, thereby reducing the requirements for the data signal provided by the data line Vda. Therefore, under the action of the parasitic capacitor Cst2, a lower driving current can also be achieved, avoiding the voltage of the data signal Vda exceeding its voltage upper limit.

[0094] For example, in some examples, the leakage prevention control signal provided by the leakage prevention control signal line EM2 can be the same as the light emission control signal provided by the light emission control signal line EM1. For example, the driving timing of the leakage prevention transistor T8 and the first light emission control transistor T5 and the second light emission control transistor T6 can be the same, so the same signal can be used to simultaneously drive the leakage prevention transistor T8, the first light emission control transistor T5, and the second light emission control transistor T6.

[0095] For example, in other examples, the anti-leakage control signal provided by the anti-leakage control signal line EM2 may be different from the light-emitting control signal provided by the light-emitting control signal line EM1. The anti-leakage control signal EM2 is used to independently control the conduction and cutoff of the anti-leakage transistor T8, and the light-emitting control signal EM1 controls the conduction and cutoff of the first light-emitting control transistor T5 and the second light-emitting control transistor T6. In the light-emitting stage T30, the driving timing of the anti-leakage transistor T8 and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 may be different. For example, the anti-leakage control signal of the anti-leakage transistor T8 is always maintained at a low level in the light-emitting stage T30, while the light-emitting control signals of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are generally maintained at a low level in the light-emitting stage T30, and may jump to a high level once every predetermined period of time (such as Figure 2C (as shown) to reduce the light-emission duration of light-emitting element 121, thereby reducing the brightness of light-emitting element 121 within a short period of time, thereby reducing the power consumption of the pixel circuit. Due to the persistence of vision phenomenon, the user does not perceive the change in brightness of light-emitting element 121. Therefore, during the light-emitting stage T30, the driving timing of the anti-leakage transistor T8, the first light-emission control transistor T5, and the second light-emission control transistor T6 can be different. Therefore, the anti-leakage control signal line EM2 is used to independently control the anti-leakage transistor T8.

[0096] Figure 3 A schematic diagram of a layout of a pixel circuit provided in some embodiments of the present disclosure is provided. Figures 4A-4OSchematic diagram of each layer of a pixel circuit provided in some embodiments of the present disclosure. Figure 3 and 4A -4O, the stacked structure of one pixel circuit 120 is taken as an example for description.

[0097] Figure 3 for Figure 2A As shown in the layout diagram of the pixel circuit, the display substrate may include a first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer, a source and drain metal layer, a fourth conductive layer and an anode layer. Figures 4A-4O A schematic diagram of various structural layers of a pixel circuit provided in some embodiments of the present disclosure, wherein: Figure 4A is a schematic diagram of the first active semiconductor layer 310, Figure 4B is a schematic diagram of the first conductive layer 320, Figure 4C is a schematic diagram of the overlap of the first active semiconductor layer 310 and the first conductive layer 320, Figure 4D is a schematic diagram of the second conductive layer 330, Figure 4E The second conductive layer 330 and Figure 4C The schematic diagram of the overlapping stacked structure shown is Figure 4F is a schematic diagram of the second active semiconductor layer 340, Figure 4G is a schematic diagram of the third conductive layer 350, Figure 4H The second active semiconductor layer 340 and the third conductive layer 350 are connected to Figure 4E The schematic diagram of the overlapping stacked structure shown is Figure 4I is a schematic diagram of the source and drain metal layer 360, Figure 4J Schematic diagram of the insulating layer via. Figure 4K Schematic diagram of the overlap between the source and drain metal layer 360 and the insulating layer via hole. Figure 4L The source and drain metal layers 360 and Figure 4H The schematic diagram of the overlapping stacked structure shown is Figure 4M is a schematic diagram of an insulating layer via between the source-drain metal layer 360 and the fourth conductive layer 370, Figure 4N shows a schematic diagram of the fourth conductive layer 370, Figure 4O The fourth conductive layer 370 is shown Figure 4L Schematic diagram of the overlapping stacked structures shown.

[0098] For example, in a direction perpendicular to the base substrate 10, the first active semiconductor layer 310 is located between the base substrate 10 and the first conductive layer 320, the first conductive layer 320 is located between the first active semiconductor layer 310 and the second conductive layer 330, the second conductive layer 330 is located between the first conductive layer 320 and the second active semiconductor layer 340, the second active semiconductor layer 340 is located between the second conductive layer 330 and the third conductive layer 350, the third conductive layer 350 is located between the second active semiconductor layer 340 and the source-drain metal layer 360, the source-drain metal layer 360 is located between the third conductive layer 350 and the fourth conductive layer 370, and the fourth conductive layer 370 is located between the source-drain metal layer 360 and the anode layer (not shown).

[0099] For example, Figure 3 As shown, the first reset signal line Re1, the first initial signal line Vinit1, the scan signal line Ga, the anti-leakage control signal line EM2, the light-emitting control signal line EM1, the second reset signal line Re2 and the second initial signal line Vinit2 extend along the first direction X and are arranged in sequence from top to bottom along a second direction Y intersecting the first direction X.

[0100] For example, in some embodiments, the first direction X and the second direction Y are perpendicular to each other. The first direction X may be parallel to the horizontal direction, and the second direction Y may be parallel to the vertical direction.

[0101] For example, in the second direction Y, the storage capacitor Cst1 is located between the light emitting control signal line EM1 and the scanning signal line Ga or the leakage prevention control signal line EM2. Figure 3 As shown, the orthographic projection of the light emitting control signal line EM1 on the base substrate 10 is located on a side of the orthographic projection of the storage capacitor Cst1 on the base substrate 10 away from the orthographic projection of the scanning signal line Ga on the base substrate 10. In addition, in the second direction Y, the storage capacitor Cst1 is located between the first reset signal line Re1 and the second reset signal line Re2, for example, Figure 3 As shown, the orthographic projection of the storage capacitor Cst1 on the base substrate is located between the orthographic projection of the first reset signal line Re1 on the base substrate and the orthographic projection of the second reset signal line Re2 on the base substrate.

[0102] For example, in the second direction Y, the first initial signal line Vinit1 is located between the first reset signal line Re1 and the second reset signal line Re2, for example, Figure 3As shown, the orthographic projection of the first initial signal line Vinit1 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate. For example, in the second direction Y, the second initial signal line Vinit2 is located on the side of the second reset signal line Re2 away from the first reset signal line Re1, for example, Figure 3 As shown, the orthographic projection of the second initial signal line Vinit2 on the base substrate is located on a side of the orthographic projection of the second reset signal line Re2 on the base substrate away from the orthographic projection of the first reset signal line Re1 on the base substrate.

[0103] For example, the leakage prevention control signal line EM2 extends along the first direction X. In the second direction Y, the leakage prevention control signal line EM2 is located between the scan signal line Ga and the storage capacitor Cst1, for example, Figure 3 As shown, the orthographic projection of the leakage prevention control signal line EM2 on the base substrate 10 is located between the orthographic projection of the scanning signal line Ga on the base substrate 10 and the orthographic projection of the storage capacitor Cst1 on the base substrate 10 .

[0104] For example, Figure 3 As shown, the first voltage line VDD includes a first sub-voltage line VDD1 extending along the second direction Y and a second sub-voltage line VDD2 extending along the first direction X. The first sub-voltage line VDD1 and the second sub-voltage line VDD2 are located in different layers. For example, the second sub-voltage line VDD2 is located in the second conductive layer 330, and the first sub-voltage line VDD1 is located in the fourth conductive layer 370. The first sub-voltage line VDD1 and the second sub-voltage line VDD2 located in different layers are connected by vias penetrating the insulating layer, so that the first voltage line VDD is grid-wired on the base substrate. That is, on the entire display substrate, the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are arranged in a grid shape, so that the resistance of the first voltage line VDD is small and the voltage drop is low, thereby improving the stability of the power supply voltage provided by the first voltage line VDD.

[0105] For example, the data line Vda extends along the second direction Y, and the data line Vda and the first sub-voltage line VDD1 are arranged along the first direction X.

[0106] For example, Figure 3 As shown, in the first direction X, the data writing transistor T4 and the first light emitting control transistor T5 are located on one side of the storage capacitor Cst1, for example Figure 3 The first reset transistor T1, the threshold compensation transistor T2, the second light emitting control transistor T6 and the second reset transistor T7 are located on the other side of the storage capacitor Cst1, for example Figure 3In the second direction Y, the data writing transistor T4, the first reset transistor T1 and the threshold compensation transistor are located on one side of the storage capacitor Cst1, for example Figure 3 The first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are located on the other side of the storage capacitor Cst1, for example Figure 3 Underside shown.

[0107] For example, Figure 3 As shown, in the first direction X, the anti-leakage transistor T8 is located on the side of the threshold compensation transistor T2 that is away from the data write transistor T4. For example, the orthogonal projection of the anti-leakage transistor T8 on the substrate is located on the side of the orthogonal projection of the threshold compensation transistor T2 that is away from the orthogonal projection of the data write transistor T4 on the substrate. In the second direction Y, the anti-leakage transistor T8 is located on the side of the storage capacitor Cst1 that is away from the light control signal line EM1. For example, the orthogonal projection of the anti-leakage transistor T8 on the substrate is located on the side of the orthogonal projection of the storage capacitor Cst1 that is away from the orthogonal projection of the light control signal line EM1 on the substrate. The threshold compensation transistor T2, the data write transistor T4, and the anti-leakage transistor T8 extend along the second direction Y and are arranged along the first direction X.

[0108] For example, Figure 3 As shown, in the first direction X, the parasitic capacitor Cst2 is located between the data write transistor T4 and the threshold compensation transistor T2. For example, the orthographic projection of the parasitic capacitor Cst2 on the substrate is located between the orthographic projection of the data write transistor T4 and the orthographic projection of the threshold compensation transistor T2 on the substrate. In the second direction Y, the parasitic capacitor Cst2 is located on the side of the storage capacitor Cst1 away from the light-emission control signal line EM1. For example, the orthographic projection of the parasitic capacitor Cst2 on the substrate is located on the side of the orthographic projection of the storage capacitor Cst1 on the substrate away from the orthographic projection of the light-emission control signal line EM1 on the substrate. The orthographic projection of the parasitic capacitor Cst2 on the substrate at least partially overlaps with the orthographic projection of the scan signal line Ga on the substrate.

[0109] For example, Figure 4A The first active semiconductor layer 310 is shown in FIG. Figure 4AAs shown, the first active semiconductor layer 310 can be patterned using a semiconductor material on a substrate. The first active semiconductor layer includes active layers A1-A7 of transistors T1-T7, with the active layers of transistors T1-T7 located on the same layer. The active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2, the active layer A6 of the second emission control transistor T6, and the active layer A7 of the second reset transistor T7 can be formed integrally, and can also be formed integrally with the active layer A3 of the drive transistor T3, the active layer A4 of the data write transistor T4, and the active layer A5 of the first emission control transistor T5. The active layer of each transistor can include a source region, a drain region, and a channel region located between the source and drain regions.

[0110] For example, in the first direction X, the active layer A4 of the data writing transistor T4 and the active layer A5 of the first light emission control transistor T5 are located on a first side of the active layer A3 of the driving transistor T3, for example Figure 4A The active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2, the active layer A6 of the second light emission control transistor T6 and the active layer A7 of the second reset transistor T7 are located on the second side of the active layer A3 of the driving transistor T3, for example Figure 4A Right side shown.

[0111] For example, in the second direction Y, the active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2 and the active layer A4 of the data writing transistor T4 are located on the third side of the active layer A3 of the driving transistor T3, for example Figure 4A The active layer A5 of the first light emission control transistor T5, the active layer A6 of the second light emission control transistor T6 and the active layer A7 of the second reset transistor T7 are located on the fourth side of the active layer A3 of the driving transistor T3, for example Figure 4A Underside shown.

[0112] For example, the active semiconductor layer 310 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities. In the embodiment of the present disclosure, the doped source region corresponds to the source of the transistor, and the doped drain region corresponds to the drain of the transistor.

[0113] For example, Figure 4B The first conductive layer 320 is shown in FIG. Figure 4BAs shown, the first reset signal line Re1, the second reset signal line Re2, the emission control signal line EM1, and the scan signal line Ga are all located in the first conductive layer 320. Furthermore, the first conductive layer 320 may further include a first electrode plate CC1 of the storage capacitor Cst1, as well as the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2, the gate of the data write transistor T4, the gate of the first emission control transistor T5, the gate of the second emission control transistor T6, the gate of the second reset transistor T7, and the gate of the drive transistor T3. Furthermore, the first conductive layer 320 may further include a first electrode plate CCa of the parasitic capacitor Cst2.

[0114] For example, the scanning signal line Ga is electrically connected to the gate of the threshold compensation transistor T2 and the gate of the data writing transistor T4, so as to control the threshold compensation transistor T2 and the data writing transistor T4 to be turned on or off; the light-emitting control signal line EM1 is electrically connected to the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6, so as to control the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on or off; the first reset signal line Re1 is electrically connected to the gate of the first reset transistor T1, so as to control the first reset transistor T1 to be turned on or off; the second reset signal line Re2 is electrically connected to the gate of the second reset transistor T7, so as to control the second reset transistor T7 to be turned on or off.

[0115] For example, Figure 4B As shown, the scanning signal line Ga is connected to the first electrode plate CCa of the parasitic capacitor. For example, the first electrode plate CCa of the parasitic capacitor is formed integrally with the scanning signal line Ga.

[0116] For example, Figure 4C FIG. 3 is a schematic diagram showing the stacking position relationship between the first conductive layer 320 and the first active semiconductor layer 310. Figure 4C As shown, the scan signal line Ga overlaps with the active layer A2 of the threshold compensation transistor T2 and the active layer A4 of the data write transistor T4. The emission control signal line EM1 overlaps with the active layer A5 of the first emission control transistor T5 and the active layer A6 of the second emission control transistor T6. The first reset signal line Re1 overlaps with the active layer A1 of the first reset transistor T1, and the second reset signal line Re2 overlaps with the active layer A7 of the second reset transistor T7. The first electrode plate CC1 of the storage capacitor overlaps with the active layer A3 of the drive transistor T3.

[0117] For example, Figure 4CAs shown, the gate of the threshold compensation transistor T2 and the gate of the data write transistor T4 are integrally formed with the scan signal line Ga, and the gates of the threshold compensation transistor T2 and the data write transistor T4 are parallel in a first direction. The gate of the threshold compensation transistor T2 may be the portion where the scan signal line Ga overlaps with the active layer A2 of the threshold compensation transistor T2, and the gate of the data write transistor T4 may be the portion where the scan signal line Ga overlaps with the active layer A4 of the data write transistor T4. The gate of the first emission control transistor T5 and the gate of the second emission control transistor T6 are integrally formed with the emission control signal line EM1. The gate of the first emission control transistor T5 may be the portion where the emission control signal line EM1 overlaps with the active layer A5 of the first emission control transistor T5, and the gate of the second emission control transistor T6 may be the portion where the emission control signal line EM1 overlaps with the active layer A6 of the second emission control transistor T6. The gate of the first reset transistor T1 is integrally formed with the first reset signal line Re1, and the gate of the first reset transistor T1 may be the portion where the first reset signal line Re1 overlaps with the active layer A1 of the first reset transistor T1. The gate of the second reset transistor T7 is integrally formed with the second reset signal line Re2. The gate of the second reset transistor T7 may be the portion where the second reset signal line Re2 overlaps with the active layer A2 of the second reset transistor T2. The gate of the drive transistor T3 may be the first electrode plate CC1 of the storage capacitor Cst1. That is, the gate of the drive transistor T3 is integrally formed with the first electrode plate CC1 of the storage capacitor.

[0118] For example, the first reset signal line Re1 is formed integrally with the gate of the first reset transistor T1 of the pixel circuit of the y-th row and the gate of the second reset transistor T7 of the pixel circuit of the y-1-th row, that is, the first reset signal line Re1 is formed integrally with the gate of the first reset transistor T1 in the sub-pixel of this row and the gate of the second reset transistor T7 in the sub-pixel of the previous row.

[0119] For example, the second reset signal line Re2 is formed integrally with the gate of the first reset transistor T1 of the pixel circuit of the y+1th row and the gate of the second reset transistor T7 of the pixel circuit of the yth row, that is, the second reset signal line Re2 is formed integrally with the gate of the second reset transistor T7 in the sub-pixels of this row and the gate of the first reset transistor T1 in the sub-pixels of the next row.

[0120] For example, Figure 4CAs shown, in a direction perpendicular to the substrate 10, the portion of the first active semiconductor layer 310 covered by the first electrode plate CC1 of the storage capacitor Cst1 forms the active channel region of the drive transistor T3, which can be in the shape of a "X". The portion of the first active semiconductor layer 310 covered by the emission control signal line EM1 forms the active channel region of the first emission control transistor T5 and the active channel region of the second emission control transistor T6. The portion of the first active semiconductor layer 310 covered by the scan signal line Ga forms the active channel region of the threshold compensation transistor T2 and the active channel region of the data write transistor T4. The portion of the first active semiconductor layer 310 covered by the first reset signal line Re1 forms the active channel region of the first reset transistor T1. The portion of the first active semiconductor layer 310 covered by the second reset signal line Re2 forms the active channel region of the second reset transistor T7.

[0121] For example, Figure 3 and Figure 4C As shown, in the first direction X, the orthographic projections of the active layer A2 of the threshold compensation transistor T2 and the active layer A4 of the data write transistor T4 on the substrate are respectively located on both sides of the orthographic projection of the storage capacitor Cst1 on the substrate. The orthographic projection of the active layer A3 of the drive transistor T3 on the substrate is located between the orthographic projection of the active layer A4 of the data write transistor T4 on the substrate and the orthographic projection of the active layer A2 of the threshold compensation transistor T2 on the substrate. The orthographic projection of the active layer A3 of the drive transistor T3 on the substrate is located between the orthographic projections of the active layer A4 of the data write transistor T4 and the active layer A5 of the first emission control transistor T5 on the substrate, and the orthographic projections of the active layer A6 of the second emission control transistor T6 and the active layer A2 of the threshold compensation transistor T2 on the substrate.

[0122] For example, in the second direction Y, the orthogonal projection of the active layer A1 of the first reset transistor T1 on the substrate is located on a side of the orthogonal projection of the active layer A2 of the threshold compensation transistor T2 on the substrate away from the orthogonal projection of the storage capacitor Cst1 on the substrate. The orthogonal projection of the active layer A7 of the second reset transistor T7 on the substrate is located on a side of the orthogonal projection of the active layer A6 of the second light emission control transistor T6 on the substrate away from the orthogonal projection of the active layer A1 of the first reset transistor T1 on the substrate.

[0123] For example, Figure 4C As shown, in the second direction Y, the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2 and the gate of the data writing transistor T4 are all located on the first side of the gate of the driving transistor T3. For example, Figure 4Cthe gate of the second reset transistor T7, the gate of the first emission control transistor T5 and the gate of the second emission control transistor T6 are located on the second side of the gate of the driving transistor T3, for example, Figure 4C Underside shown.

[0124] For example, in some examples, the gate of the anti-leakage transistor T8 and the anti-leakage control signal line EM2 are formed integrally. In the second direction Y, the gate of the anti-leakage transistor T8 is located on a side of the gate of the driving transistor T3 away from the gate of the second light emitting control transistor T6, for example, Figure 3 The leakage prevention control signal line EM2 includes a first sub-control signal line EM21 and a second sub-control signal line EM22.

[0125] Figure 4D Schematic diagram of the second conductive layer 330 is shown, as shown in Figure 4D As shown, the second conductive layer 330 includes a second electrode plate CC2 of the storage capacitor and a first sub-control signal line EM21, wherein the second electrode plate CC2 of the storage capacitor is integrally formed with the second sub-voltage line VDD2. The first sub-control signal line EM21 extends along the first direction X.

[0126] Figure 4E Schematic diagram of the stacking position relationship of the first active semiconductor layer 310, the first conductive layer 320 and the second conductive layer 330. Figure 4C and 4E As shown, the orthographic projection of the second electrode plate CC2 of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC1 of the storage capacitor on the substrate. Figure 4C and 4E As shown, in the second direction Y, the first sub-control signal line EM21 is located between the second electrode plate CC2 and the scanning signal line Ga. For example, the orthographic projection of the first sub-control signal line EM21 on the base substrate is located between the orthographic projection of the second electrode plate CC2 on the base substrate and the orthographic projection of the scanning signal line Ga on the base substrate.

[0127] Figure 4F A schematic diagram of the second active semiconductor layer 340 is shown, as shown in FIG. Figure 4FAs shown, the second active semiconductor layer 340 includes the active layer A8 of the anti-leakage transistor T8, the third electrode plate CC3 of the storage capacitor, and the second electrode plate CCb of the parasitic capacitor. The material of the second active semiconductor layer 340 is, for example, an oxide semiconductor material, and the oxide semiconductor material is, for example, an indium gallium zinc oxide (IGZO) material, etc., and the embodiments of the present disclosure are not limited to this. That is, the materials of the active layer A8 of the leakage transistor, the third electrode plate CC3 of the storage capacitor, and the second electrode plate CCb of the parasitic capacitor include oxide semiconductor materials. For example, only the second active semiconductor layer 340 uses an oxide semiconductor material, that is, in the transistors T1 to T8, the oxide semiconductor material is, for example, only present in the anti-leakage transistor T8.

[0128] For example, the anti-leakage transistor T8 uses an oxide semiconductor thin film transistor, and the transistors T1 to T7 use polysilicon thin film transistors. The active layer A8 of the anti-leakage transistor T8 and the active layers A1 to A7 of the transistors T1 to T7 are located in different layers, that is, the oxide semiconductor thin film transistor and the polysilicon thin film transistor are located in different film layers.

[0129] For example, Figure 3 、 Figure 4C and Figure 4F As shown, the active layer A8 of the anti-leakage transistor T8, the active layer A2 of the threshold compensation transistor T2, and the active layer A4 of the data writing transistor T4 all extend along the second direction Y and are arranged side by side along the first direction X. For example, a portion of the active layer A2 of the threshold compensation transistor T2 has a protrusion and a bend, but extends as a whole along the second direction Y. The orthographic projection of the active layer A8 of the anti-leakage transistor on the substrate is located on the side of the orthographic projection of the active layer A2 of the threshold compensation transistor on the substrate away from the orthographic projection of the active layer A4 of the data writing transistor on the substrate. Based on the extension direction and relative position of the active layer A2 of the threshold compensation transistor T2 and the active layer A8 of the anti-leakage transistor T8, the occupied area of the pixel circuit can be saved, and it is convenient to connect the two electrodes of the anti-leakage transistor T8 to the threshold compensation transistor T2 and the storage capacitor respectively, avoiding winding and further reducing the occupied area.

[0130] Figure 4G Schematic diagram of the third conductive layer 340 is shown, as shown in Figure 4G As shown, the third conductive layer 340 includes a second sub-control signal line EM22 , and the second sub-control signal line EM22 extends along the first direction X.

[0131] For example, the leakage prevention control signal line EM2 includes a first sub-control signal line EM21 and a second sub-control signal line EM22. The first sub-control signal line EM21 is located in the second conductive layer 330, and the second sub-control signal line EM22 is located in the third conductive layer 350. Figure 4H As shown, the orthographic projection of the first sub-control signal line EM21 on the substrate at least partially overlaps with the orthographic projection of the second sub-control signal line EM22 on the substrate.

[0132] Figure 4H For Figure 4E Schematic diagram of stacking the second active semiconductor layer 340 and the third conductive layer 350 on the basis of Figure 4H As shown, in a direction perpendicular to the substrate, the first sub-control signal line EM21 and the second sub-control signal line EM22 at least partially overlap with the active layer A8 of the anti-leakage transistor T8.

[0133] For example, Figure 5A The BB` part shows the corresponding Figure 3 Schematic diagram of the cross-sectional structure of the leakage-proof transistor T8. Figure 4H and Figure 5A As shown in the BB' portion of FIG, the gate of the anti-leakage transistor T8 includes a first gate gc81 and a second gate gc82. The first gate gc81 is integrally formed with the first sub-control signal line EM21. The first gate gc81 may be the portion where the first sub-control signal line EM21 overlaps with the active layer A8 of the anti-leakage transistor T8. The second gate gc82 is integrally formed with the second sub-control signal line EM22. The second gate gc82 may be the portion where the second sub-control signal line EM22 overlaps with the active layer A8 of the anti-leakage transistor T8. In a direction perpendicular to the substrate, the active layer A8 of the anti-leakage transistor is located between the first gate gc81 and the second gate gc82. Based on this solution, implementing the anti-leakage transistor T8 as a dual-gate transistor can improve the reliability of the anti-leakage transistor T8, for example, by enhancing its resistance to high temperature and high humidity. Furthermore, the two gates of the anti-leakage transistor T8 and the active layer A8 are arranged perpendicular to the substrate, which can save space.

[0134] For example, Figure 5A The CC` part shows the corresponding Figure 3 The cross-sectional structure diagram of the storage capacitor Cst1 is as follows: Figure 4H and Figure 5A As shown in the CC' portion of FIG, the first electrode plate CC1 of the storage capacitor is located on the first conductive layer 320. Figure 4D and Figure 5A As shown in the CC' portion of FIG, the second electrode plate CC2 of the storage capacitor is located on the second conductive layer 330. Figure 4F and Figure 5A As shown in the CC' portion, the third electrode plate CC3 is located in the second active semiconductor layer 340. In a direction perpendicular to the substrate, the first electrode plate CC1, the second electrode plate CC2 and the third electrode plate CC3 at least partially overlap to form a storage capacitor Cst1.

[0135] For example, Figure 4F and 4H As shown, the second electrode plate CCb of the parasitic capacitor is located in the second active semiconductor layer 340, on the same layer as the third electrode plate CC3 of the storage capacitor. The first electrode plate CCa of the parasitic capacitor is integrally formed with the scan signal line Ga. The second electrode plate CCb of the parasitic capacitor at least partially overlaps with the first electrode plate CCa of the parasitic capacitor in a direction perpendicular to the substrate to form a parasitic capacitor Cst2. The orthographic projection of the second electrode plate CCb of the parasitic capacitor on the substrate is located between the orthographic projection of the active layer of the threshold compensation transistor T2 and the orthographic projection of the active layer of the data write transistor T4 on the substrate.

[0136] For example, at least one insulating layer is disposed between each two adjacent layers of the first active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the second active semiconductor layer 340, the third conductive layer 350, the source-drain metal layer 360, the fourth conductive layer 370, and the anode layer (not shown). Figure 5A As shown, there is a first insulating layer 510 between the first active semiconductor layer 310 and the first conductive layer 320, a second insulating layer 520 between the first conductive layer 320 and the second conductive layer 330, a third insulating layer 530 and a buffer layer 540 between the second conductive layer 330 and the second active semiconductor layer 340, a fourth insulating layer 550 between the second active semiconductor layer 340 and the third conductive layer 350, a fifth insulating layer 560 between the third conductive layer 350 and the source-drain metal layer 360, a sixth insulating layer 570 between the source-drain metal layer 360 and the fourth conductive layer 370, and a planarization layer 580 between the fourth conductive layer 370 and the anode layer.

[0137] For example, the first insulating layer 510 to the sixth insulating layer 570, the buffer layer 540 and the planarization layer 580 are all made of insulating materials, such as inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials, so the buffer layer 540 and the planarization layer 580 can also serve as insulating layers.

[0138] Figure 4ISchematic diagram of the source-drain metal layer 360 is shown, and the source-drain metal layer 360 includes a first connection electrode Co1, a second connection electrode Co2, a third connection electrode Co3, a fourth connection electrode Co4, a fifth connection electrode Co5, a first initial signal line Vinit1 and a second initial signal line Vinit1.

[0139] Figure 4J A schematic diagram of an insulating layer via hole is shown, where each of the plurality of insulating layer via holes V21 - V28 and V31 - V34 penetrates through a plurality of insulating layers. Figure 4K Schematic diagram showing the stacking of the source and drain metal layer 360 and the insulating layer vias, Figure 4L For Figure 4H Schematic diagram of stacking source and drain metal layers 360 on the basis.

[0140] like Figures 4I to 4L As shown, the first electrode sc1 of the first reset transistor T1 and the first electrode sc2 of the threshold compensation transistor T2 are the same electrode. The first end of the first connection electrode Co1 is integrally formed with the first electrode sc1 of the first reset transistor T1 and the first electrode sc2 of the threshold compensation transistor T2, and is connected to the active layer A2 of the threshold compensation transistor T2 and the active layer A1 of the first reset transistor T1 via a via V21 that penetrates the insulating layer. The second end of the first connection electrode Co1 is integrally formed with the first electrode fc8 of the anti-leakage transistor T8, and is connected to the active layer A8 of the anti-leakage transistor T8 via a via V31 that penetrates the insulating layer.

[0141] For example, the via hole V21 penetrates the insulating layers between the source-drain metal layer 360 and the first active semiconductor layer 310, namely, the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first end of the first connection electrode Co1 is connected to the source region or the drain region corresponding to the threshold compensation transistor T2 in the first active semiconductor layer 310. The via hole V31 penetrates the insulating layers between the source-drain metal layer 360 and the second active semiconductor layer 340, namely, the fourth insulating layer 550 and the fifth insulating layer 560, so that the second end of the first connection electrode Co1 is connected to the source region or the drain region corresponding to the leakage protection transistor T8 in the second active semiconductor layer 340.

[0142] For example, a first end of the second connection electrode Co2 is integrally formed with the second electrode sc8 of the anti-leakage transistor T8 and is connected to the active layer A8 of the anti-leakage transistor T8 via a via V32 penetrating the insulating layer. A second end of the second connection electrode Co2 is connected to the first electrode plate CC1 of the storage capacitor via a via V24 penetrating the insulating layer, and a third end of the second connection electrode is connected to the third electrode plate CC3 of the storage capacitor via a via V33 penetrating the insulating layer.

[0143] For example, the via hole V32 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, that is, the fourth insulating layer 550 and the fifth insulating layer 560, so that the first end of the second connection electrode Co2 is connected to the source region or the drain region corresponding to the leakage protection transistor T8 in the second active semiconductor layer 340. The via hole V33 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, that is, the fourth insulating layer 550 and the fifth insulating layer 560, so that the third end of the second connection electrode Co2 is connected to the third electrode plate CC3 in the second active semiconductor layer 340.

[0144] For example, the via hole V24 penetrates the insulating layer between the source-drain metal layer 360 and the first conductive layer 320, that is, the second insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540. Figure 4D As shown, the second electrode plate CC2 of the storage capacitor is provided with a first conductive layer via hole V11, as shown in FIG. Figure 4F As shown, the third electrode plate CC3 of the storage capacitor is provided with a second conductive layer via hole V12. In a direction perpendicular to the substrate, the first conductive layer via hole V11, the second conductive layer via hole V12 and the insulating layer via hole V24 at least partially overlap. Figure 5A As shown, the second end of the second connection electrode Co2 is connected to the storage capacitor first electrode plate CC1 in the first conductive layer 320 through the via V24 of the second insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, the via V11 of the first conductive layer and the via V12 of the second conductive layer.

[0145] For example, Figure 5B Another cross-sectional schematic diagram provided for some embodiments of the present disclosure, Figure 5B and Figure 5A The difference is in the CC` part, such as Figure 5B As shown, the third electrode plate CC3 may not be provided with a via hole, and the first electrode plate CC1 and the third electrode plate CC3 may be connected through a via hole. For example, a penetrating insulating layer via hole may be provided in the insulating layer (the second insulating layer 520, the third insulating layer 530, and the buffer layer 540) between the third electrode plate CC3 and the first electrode plate CC1. The third electrode plate CC3 may be connected to the first electrode plate CC1 in the first conductive layer 320 through the insulating layer via hole and the via hole of the second electrode plate CC2. Since the third electrode plate CC3 is connected to the second connection electrode Co2, the connection between the first electrode plate CC1 and the second connection electrode Co2 can be achieved.

[0146] For example, Figure 5C Another cross-sectional schematic diagram provided for some embodiments of the present disclosure, Figure 5C and Figure 5A and Figure 5B The difference is in the CC` part, such as Figure 5C As shown, a region overlapping with the first electrode plate CC1 and not overlapping with the third electrode plate CC3 can be provided on the second connecting electrode Co2, and an insulating layer via is provided through the insulating layer corresponding to the region (the second insulating layer 520 to the fifth insulating layer 560 and the buffer layer 540). The second connecting electrode Co2 is connected to the first electrode plate CC1 in the first conductive layer 320 through the insulating layer via without passing through the third electrode plate CC3, and there is no need to provide a via on the third electrode plate CC3.

[0147] like Figure 5C As shown, in some embodiments, a region overlapping with the first electrode plate CC1 and not overlapping with the third electrode plate CC3 and the second electrode plate CC2 can be further provided on the second connecting electrode Co2, and an insulating layer via is provided through the insulating layer corresponding to the region (the second insulating layer 520 to the fifth insulating layer 560 and the buffer layer 540), and the second connecting electrode Co2 is directly connected to the first electrode plate CC1 in the first conductive layer 320 through the insulating layer via without passing through the third electrode plate CC3 and the second electrode plate CC2, and there is no need to provide a via on the third electrode plate CC3 and the second electrode plate CC2.

[0148] For example, the second electrode plate CCb of the parasitic capacitor is connected to the fourth end of the second connection electrode Co2 through a via V34 that penetrates the insulating layer. The via V34 penetrates the insulating layers between the source-drain metal layer 360 and the second active semiconductor layer 340, that is, the fourth insulating layer 550 and the fifth insulating layer 560, so that the fourth end of the second connection electrode Co2 is connected to the second electrode plate CCb of the parasitic capacitor in the second active semiconductor layer 340.

[0149] For example, the first end of the third connection electrode Co3 is integrally formed with the first electrode fc5 of the first light-emitting control transistor T5, and is connected to the active layer A5 of the first light-emitting control transistor T5 through a via V26 penetrating the insulating layer, and the second end of the third connection electrode Co3 is connected to the second electrode plate CC2 of the storage capacitor through a via V25 penetrating the insulating layer.

[0150] For example, the via hole V26 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, that is, the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first end of the third connection electrode Co3 is connected to the source region or the drain region corresponding to the first light emission control transistor T5 in the first active semiconductor layer 310. The via hole V25 penetrates the insulating layer between the source-drain metal layer 360 and the second conductive layer 330, that is, the third insulating layer 530 to the fifth insulating layer 560 and the buffer layer 540, so that the second end of the third connection electrode Co3 is connected to the second electrode plate CC2 in the second conductive layer 320.

[0151] For example, the fourth connection electrode Co4 is integrally formed with the first electrode sc4 of the data write transistor T4 and is connected to the active layer A4 of the data write transistor T4 via a via V22 that penetrates the insulating layer. For example, the via V22 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, that is, the first insulating layer 510 to the fifth insulating layer 560, so that the first end of the fourth connection electrode Co4 is connected to the source region or the drain region of the first active semiconductor layer 310 corresponding to the data write transistor T4.

[0152] For example, the fifth connection electrode Co5 is integrally formed with the first electrode sc6 of the second emission control transistor T6 and is connected to the active layer A6 of the second emission control transistor T6 via a via V27 that penetrates the insulating layer. The via V27 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, that is, the first insulating layer 510 to the fifth insulating layer 560, so that the first end of the fifth connection electrode Co5 is connected to the source region or the drain region of the first active semiconductor layer 310 corresponding to the second emission control transistor T6.

[0153] For example, the first initial signal line Vinit1 is integrally formed with the second electrode fc1 of the first reset transistor T1 and is connected to the active layer A1 of the first reset transistor T1 via a via V21 that penetrates the insulating layer. For example, the via V21 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, namely, the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first initial signal line Vinit1 is connected to the source region or the drain region of the first active semiconductor layer 310 corresponding to the first reset transistor T1.

[0154] For example, the first initial signal line Vinit1 extends along the first direction X, and the orthographic projection of the first initial signal line Vinit1 on the base substrate is located between the orthographic projection of the first reset signal line Re1 and the orthographic projection of the second reset signal line Re2 on the base substrate.

[0155] For example, the first initial signal line Vinit1 is formed integrally with the second electrode of the first reset transistor T1 of the pixel circuit of the y-th row and the first electrode of the second reset transistor T7 of the pixel circuit of the y-1-th row, that is, the first initial signal line Vinit1 is formed integrally with the second electrode of the first reset transistor T1 in the sub-pixels of this row and the first electrode of the second reset transistor T7 in the sub-pixels of the previous row.

[0156] For example, the second initial signal line Vinit2 is integrally formed with the first electrode fc7 of the second reset transistor T7 and is connected to the active layer A2 of the second reset transistor T2 via a via V28 that penetrates the insulating layer. For example, the via V28 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, that is, the first insulating layer 510 to the fifth insulating layer 560, so that the second initial signal line Vinit2 is connected to the source region or the drain region of the first active semiconductor layer 310 corresponding to the second reset transistor T7.

[0157] For example, the second initial signal line Vinit2 extends along the first direction X, and the orthographic projection of the second initial signal line Vinit2 on the substrate is located on a side of the orthographic projection of the second reset signal line Re2 on the substrate away from the orthographic projection of the first reset signal line Re1 on the substrate.

[0158] For example, the second initial signal line Vinit2 is formed integrally with the second electrode of the first reset transistor T1 of the pixel circuit of the y+1th row and the first electrode of the second reset transistor T7 of the pixel circuit of the yth row, that is, the first initial signal line Vinit1 is formed integrally with the first electrode of the second reset transistor T7 in the sub-pixels of this row and the second electrode of the first reset transistor T1 in the sub-pixels of the next row.

[0159] For example, the first initial signal line Vinit1 and the second initial signal line Vinit2 can be connected by a connecting line extending along the second direction Y. The connecting line can be set in the fourth conductive layer or other layers, and the connecting line can be connected to the first initial signal line Vinit1 and the second initial signal line Vinit2 through a via penetrating the insulating layer, so that the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are electrically connected. In the embodiment of the present disclosure, the vertically extending connecting line and the horizontally extending first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 located in different layers are connected by using a jumper connection method, so that the initial signal line Vinit is grid-wired on the substrate substrate and has a mesh structure, so that the resistance of the initial signal line Vinit is small and the voltage drop (IR drop) is low, so that the distribution of the initial signal line Vinit on the substrate substrate is more uniform, thereby improving the stability of the initial voltage provided by the initial signal line Vinit.

[0160] Figure 4M Schematic diagram showing the insulating layer via holes V41 to V43 between the source and drain metal layer 360 and the fourth conductive layer 370, Figure 4N The fourth conductive layer 370 is shown Figure 4M The schematic diagram of the insulation layer via stack shown is as follows: Figure 4O For Figure 4LSchematic diagram of stacking a fourth conductive layer 370 on the basis.

[0161] like Figures 4M to 4O As shown, the fourth conductive layer 370 includes a data line Vda, a first sub-voltage line VDD1, and a sixth connection electrode Co6. The data line Vda and the first sub-voltage line VDD1 are located in the same layer, and both extend along the second direction Y. The data line Vda and the first sub-voltage line VDD1 are arranged along the first direction X. The sixth connection electrode Co6 is located in the same layer as the first sub-voltage line VDD1. In the first direction X, the sixth connection electrode Co6 is located on a side of the first sub-voltage line VDD1 away from the data line Vda.

[0162] For example, Figure 3 and Figure 4N As shown, the orthographic projection of the first sub-voltage line VDD1 on the substrate is located between the orthographic projection of the active layer of the data writing transistor T4 on the substrate and the orthographic projection of the active layer of the threshold compensation transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the second electrode plate of the parasitic capacitor Cst2 on the substrate. The first sub-voltage line VDD1 also at least partially overlaps with the orthographic projection of the storage capacitor Cst1 on the substrate.

[0163] For example, Figure 4K and 4N As shown, the first sub-voltage line VDD1 has a first protrusion P1, and the third end of the third connection electrode Co3 is connected to the first protrusion P1 of the first sub-voltage line VDD1 via a via V42 that penetrates the insulating layer, and the via V42 penetrates the sixth insulating layer 570. The first sub-voltage line VDD1 is connected to the third connection electrode Co3 of the source-drain metal layer 360, and the third connection electrode Co3 is connected to the first electrode fc5 of the first emission control transistor T5 and the second electrode plate CC2 of the storage capacitor, thereby electrically connecting the first sub-voltage line VDD1 to the first electrode fc5 of the first emission control transistor T5 and the second electrode plate CC2 of the storage capacitor.

[0164] For example, Figure 4K 、 4N As shown in Figures 4O, the first sub-voltage line VDD1 further has a second protrusion P2 in the shape of a U.S. character. The orthographic projection of the second protrusion P2 on the substrate at least partially overlaps with the orthographic projection of the active layer A8 of the leakage protection transistor T8 on the substrate, shielding the leakage protection transistor T8 from light. The leakage protection transistor T8 is an oxide semiconductor thin-film transistor, which is sensitive to light. The second protrusion P2 covers the leakage protection transistor T8, shielding it from light and reducing its impact on the transistor.

[0165] For example, Figure 4K 、 4N As shown in FIG40 , the orthographic projection of the data line Vda on the base substrate at least partially overlaps with the orthographic projection of the active layer of the data write transistor T4 and the orthographic projection of the active layer of the first emission control transistor T5 on the base substrate. For example, the data line Vda is close to the active layer A4 of the data write transistor T4 and the active layer A5 of the first emission control transistor T5, thereby facilitating the connection between the data line Vda and the data write transistor T4, avoiding wiring, and reducing the size of the display panel.

[0166] For example, Figure 4K 、 4N As shown in Figures 40 and 41, the fourth connection electrode Co4 is connected to the data line Vda via a via V41 that penetrates the insulating layer. The via V41 penetrates the sixth insulating layer 570. The fourth connection electrode Co4 has a third protrusion P3. In a direction perpendicular to the base substrate, the third protrusion P3 at least partially overlaps with the via V41 in the insulating layer. The third protrusion P3 of the data line Vda is connected to the first electrode sc4 of the data write transistor on the fourth connection electrode Co4 through the via V41, thereby electrically connecting the data line Vda to the first electrode sc4 of the data write transistor T4. The orthographic projection of the via V41 on the base substrate may at least partially overlap with the via V22 in a direction perpendicular to the base substrate, but the embodiments of the present disclosure are not limited to this.

[0167] For example, Figure 4K 、 4N As shown in Figures 40 and 41, the fifth connection electrode Co5 and the sixth connection electrode Co6 at least partially overlap in a direction perpendicular to the base substrate. The fifth connection electrode Co5 is connected to the sixth connection electrode Co6 via a via V43 that penetrates the insulating layer. The via V43 penetrates the sixth insulating layer 570. The orthographic projection of the via V43 on the base substrate may at least partially overlap with the via V21 in a direction perpendicular to the base substrate, but the embodiments of the present disclosure are not limited thereto.

[0168] Figure 5A The AA` part shows the corresponding Figure 3 The cross-sectional structure diagram of the second light emitting control transistor T6 is shown in FIG. Figure 4O and Figure 5A As shown in the AA' part, the sixth connection electrode Co6 is connected to the first end (for example, the first electrode) of the light-emitting element 121 through the via V51 penetrating the insulating layer. For example, the via V51 penetrates the flat layer 580, thereby connecting the first electrode sc6 of the second light-emitting control transistor T6 to the first electrode of the light-emitting element 121 through the sixth connection electrode Co6.

[0169] For example, Figure 4KAs shown, in the second direction Y, the orthographic projection of the via hole V51 on the base substrate and the orthographic projection of the light-emitting control signal line EM1 on the base substrate at least partially overlap. Of course, the embodiments of the present disclosure are not limited to this. The position of the via hole V51 can be flexibly set to adapt to pixel circuits with various pixel arrangements. In addition, the position of the via hole V51 can be flexibly adjusted according to the setting position of the first electrode of the light-emitting element, so that the via hole V51 is closer to the first electrode of the light-emitting element, reducing the routing of the first electrode of the light-emitting element, and making the connection between the first electrode of the light-emitting element and the first electrode of the second light-emitting control transistor T6 more flexible.

[0170] For example, the anode layer may include a first electrode (ie, an anode) of the light emitting element 121 .

[0171] For example, the multiple sub-pixels in the display panel may include a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G. For example, the light-emitting element 121 in the red sub-pixel R emits red light, the light-emitting element 121 in the blue sub-pixel B emits blue light, and the light-emitting element 121 in the green sub-pixel G emits green light. For example, the area of the first electrode of a blue sub-pixel B is larger than the area of the first electrode of a green sub-pixel G, and larger than the area of the first electrode of a red sub-pixel R.

[0172] Figure 5A It consists of three parts: AA` part, BB` part and CC` part, AA` part corresponds to Figure 3 The second light emitting control transistor T6 (ie Figure 4O Schematic diagram of the cross-section structure at the middle section line AA', the BB' part corresponds to Figure 3 The anti-leakage transistor T8 (ie Figure 4O Schematic diagram of the cross-section structure at the middle section line BB'), CC' part corresponds to Figure 3 Storage capacitor Cst1 (i.e. Figure 4O Schematic diagram of the cross-sectional structure at the center section line CC'. Figure 5A This is a schematic diagram of the splicing of these three parts of the interface structure.

[0173] For example, Figure 5A As shown, the base substrate 10 includes a multi-layer structure, and the multi-layer structure is made of flexible materials.

[0174] For example, an active semiconductor layer 310 is formed on the base substrate 10. Figure 5A An active layer A6 of the second light emission control transistor T6 in the active semiconductor layer 310 is shown.

[0175] For example, a first insulating layer 510 is formed on one side of the base substrate 10 of the active semiconductor layer 310 , and a first conductive layer 320 is formed on the side of the first insulating layer 510 away from the active semiconductor layer 310 . Figure 5A The light emission control signal line EM1 and the first electrode plate CC1 of the storage capacitor in the first conductive layer 320 are shown.

[0176] For example, the second insulating layer 520 is formed on a side of the first conductive layer 320 away from the first insulating layer 510 , and the second conductive layer 330 is formed on a side of the second insulating layer 520 away from the first conductive layer 320 . Figure 5A The first gate gc81 (first sub-control signal line EM21 ) of the leakage protection transistor T8 and the second electrode plate CC2 of the storage capacitor in the second conductive layer 330 are shown.

[0177] For example, a third insulating layer 530 is formed on a side of the second conductive layer 330 away from the second insulating layer 520, a buffer layer 540 is formed on a side of the third insulating layer 530 away from the second conductive layer 330, and a second active semiconductor layer 340 is formed on a side of the buffer layer 540 away from the third insulating layer 530. Figure 5A The active layer A8 of the anti-leakage transistor T8 and the third electrode plate CC3 of the storage capacitor in the second active semiconductor layer 340 are shown.

[0178] For example, a fourth insulating layer 550 is formed on a side of the second active semiconductor layer 340 away from the buffer layer 540 , and a third conductive layer 350 is formed on a side of the fourth insulating layer 550 away from the second active semiconductor layer 340 . Figure 5A The second gate gc81 (second sub-control signal line EM22 ) of the leakage protection transistor in the third conductive layer 350 is shown.

[0179] For example, a fifth insulating layer 560 is formed on a side of the third conductive layer 350 away from the fourth insulating layer 550 , and a source-drain metal layer 360 is formed on a side of the fifth insulating layer 560 away from the third conductive layer 350 . Figure 5A The source-drain electrode sc6 (integrally formed with the fifth connection electrode Co5) connected to the active layer of the second light-emitting control transistor T6 in the source-drain metal layer 360, the source-drain electrode fc8 (integrally formed with the first connection electrode Co1) connected to the active layer of the anti-leakage transistor T8, the third connection electrode Co3 connected to the second electrode plate CC2 of the storage capacitor, and the source-drain electrode sc8 (integrally formed with the second connection electrode Co2) connected to the first electrode plate CC1 and the third electrode plate CC3 of the storage capacitor and the active layer of the anti-leakage transistor T8 are shown.

[0180] For example, a sixth insulating layer 570 is formed on a side of the source / drain metal layer 360 away from the fifth insulating layer 560 , and a fourth conductive layer 370 is formed on a side of the sixth insulating layer 570 away from the source / drain metal layer 360 . Figure 5A The sixth connection electrode Co6 connected to the fifth connection electrode Co5 and the first sub-voltage line VDD1 connected to the third connection electrode Co3 in the fourth conductive layer 370 are shown.

[0181] For example, the planarization layer 580 is formed on a side of the fourth conductive layer 370 away from the sixth insulating layer 570 , and the first electrode of the light emitting element 121 is formed on a side of the planarization layer 580 away from the fourth conductive layer 370 .

[0182] Figure 5B and Figure 5C Another cross-sectional schematic diagram provided by some embodiments of the present disclosure, Figure 5B and Figure 5C and Figure 5A The difference lies in the CC` part, please refer to the above Figure 5B and Figure 5C Description.

[0183] For example, the parameters of the storage capacitor Cst1 in different sub-pixels on the display substrate 100 may be different.

[0184] For example, in some embodiments, the parameters of the storage capacitor Cst1 of different color sub-pixels (red sub-pixel R, blue sub-pixel B, and green sub-pixel G) are different. Since the brightness requirements or charging speed requirements of the three color sub-pixels of RGB are different, the storage capacitors Cst1 of the three sub-pixels can be set differently. For example, the parameters of the storage capacitor Cst1 of the blue sub-pixel B can be different from the parameters of the storage capacitor Cst1 of the red sub-pixel R. The driving current required by the light-emitting element of the blue sub-pixel B can be greater than the driving current required by the light-emitting element of the red sub-pixel R. During the light-emitting phase, the gate voltage of the driving transistor decreases, which can increase the driving current. Therefore, the gate voltage of the driving transistor of the blue sub-pixel B can be lower than the gate voltage of the driving transistor of the red sub-pixel R. In other words, the required capacitance value of the storage capacitor Cst1 of the blue sub-pixel B is lower than the required capacitance value of the storage capacitor Cst1 of the red sub-pixel R. Therefore, the area of the electrode plate of the storage capacitor Cst1 of the blue sub-pixel B can be set to be smaller than the area of the electrode plate of the storage capacitor Cst1 of the red sub-pixel R. For example, the area of the third electrode plate CC3 of the blue sub-pixel B located on the second active semiconductor layer 340 can be smaller than the area of the third electrode plate CC3 of the red sub-pixel R located on the second active semiconductor layer 340. In turn, the capacitance value of the storage capacitor Cst1 of the blue sub-pixel B can be smaller than the capacitance value of the storage capacitor Cst1 of the red sub-pixel R, so that the blue sub-pixel B has a lower charging rate than the red sub-pixel R, thereby obtaining a higher driving current and higher brightness. In some embodiments, the parameters of the storage capacitor Cst1 of the red sub-pixel R can be the same as the parameters of the storage capacitor Cst1 of the green sub-pixel G.

[0185] For example, in one pixel arrangement, the pixel driving circuits corresponding to the red sub-pixel R, green sub-pixel G and blue sub-pixel B are arranged so that the driving circuit corresponding to the green sub-pixel G is in one column, and the driving circuits corresponding to the red sub-pixel R and blue sub-pixel B are in one column.

[0186] Figure 6 Schematic diagram of partial structural stacking provided for some embodiments of the present disclosure, for example Figure 6 Schematic diagram of the stacking of the second electrode plate CC2 and the third electrode plate CC3 of a plurality of sub-pixels or the stacking of the second electrode plate CC2 and the first electrode plate CC1. Figure 6As shown, the pixel circuits of the plurality of sub-pixels may be arranged alternately in the following manner: one column 601 is the pixel circuit of the green sub-pixel G, and the adjacent column 602 is the pixel circuit corresponding to the red sub-pixel R and the blue sub-pixel B. For example, in some embodiments, the area of the third electrode plate CC3 in the pixel circuit of the G sub-pixel (green sub-pixel) may be made larger than the area of the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel (red sub-pixel or blue sub-pixel), for example, the area of the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel is reduced from the original size S to the size S'. In this way, the storage capacitance value of the pixel circuit of the G sub-pixel may be greater than the storage capacitance value of the pixel circuit shared by the RB sub-pixels, so that the G sub-pixel has a higher charging rate than the RB sub-pixel, so as to obtain a lower driving current and lower brightness, thereby balancing the display difference caused by the excessive brightness of the G sub-pixel.

[0187] In some examples, for example, the area of the first electrode plate CC1 in the pixel circuit of the G sub-pixel (green sub-pixel) can be made larger than the area of the first electrode plate CC1 in the pixel circuit of the R / B sub-pixel (red sub-pixel or blue sub-pixel), for example, the area of the first electrode plate CC1 in the pixel circuit of the R / B sub-pixel is reduced from the original size S to the size S`, so that the storage capacitance value of the pixel circuit of the G sub-pixel can be greater than the storage capacitance value of the pixel circuit corresponding to the R / B sub-pixel, so that the G sub-pixel has a higher charging rate than the RB sub-pixel, so as to obtain a lower driving current and lower brightness, thereby balancing the display difference caused by the excessive brightness of the G sub-pixel.

[0188] In some examples, for example, continue with reference to Figure 6 , the first electrode plate CC1 and the third electrode plate CC3 ( Figure 6 Only one is shown in the figure) is larger than the area of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel (red sub-pixel or blue sub-pixel). For example, the area of the first electrode plate CC1 in the pixel circuit of the R / B sub-pixel is further reduced from S`, or the area of the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel is further reduced from S`, so as to alleviate the display difference.

[0189] In some examples, the area of the first electrode plate CC1 in the pixel circuit of the G sub-pixel can be made larger than the area of the first electrode plate CC1 in the pixel circuit of the R / B sub-pixel. For example, the area of the first electrode plate CC1 in the pixel circuit corresponding to the RB sub-pixel can be reduced.

[0190] In some examples, the areas of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the G sub-pixel can be made larger than the areas of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel. For example, the areas of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the R / B sub-pixel can be reduced.

[0191] For example, in some embodiments, reference Figure 7 Considering that the brightness of the G sub-pixel is higher than that of the R / B pixel, the storage capacitance of the G sub-pixel can be appropriately reduced, so that the G sub-pixel is easier to turn off, which is also beneficial to improving the display effect; for example, the area of the first electrode plate CC1 and / or the area of the third electrode plate CC3 of the G sub-pixel can be set to be smaller than the area of the first electrode plate CC1 and / or the area of the third electrode plate CC3 of the R / B sub-pixel, which is similar to the above embodiment and will not be repeated here.

[0192] For example, in some embodiments, reference Figure 8 For electronic devices with under-display cameras, the storage capacitor Cst1 of the sub-pixels in camera area B on the display substrate can have different parameters than the storage capacitor Cst1 of the sub-pixels in other areas A, such as the normal display area. For example, the material and length requirements of the lead wires driving the pixel circuits in the camera area may differ from those in the pixel circuits in other areas. Therefore, the storage capacitor Cst1 of the sub-pixels in camera area B can be configured differently from the storage capacitor Cst1 of the sub-pixels in other areas A. For example, because the sub-pixels in camera area B require longer leads than those in other areas A, resulting in higher resistance and a higher drive current, the electrode plate area of the storage capacitor Cst1 of the sub-pixels in camera area B can be smaller than that of the sub-pixels in other areas. For example, the area of the third electrode plate of the storage capacitor Cst1 of the sub-pixels in camera area B can be smaller than that of the sub-pixels in other areas. This can result in a lower capacitance value for the storage capacitor Cst1 of the sub-pixels in camera area B than that of the sub-pixels in other areas, allowing the sub-pixels in camera area B to have a lower charge rate than those in other areas A, thereby achieving a higher drive current.

[0193] For example, in some embodiments, when the display substrate is applied to an electronic device with an under-screen camera, differentiated designs of G pixels and storage capacitors Cst1 of R and B pixels may be simultaneously adopted. For example, the sub-pixels in the camera area B adopt the differentiated designs of G pixels and storage capacitors Cst1 of R and B pixels in the aforementioned embodiment; or the sub-pixels in other areas A adopt the differentiated designs of G pixels and storage capacitors Cst1 of R and B pixels in the aforementioned embodiment, which will not be repeated here.

[0194] For example, in addition to adjusting the performance of the storage capacitor Cst1 of different sub-pixels by adjusting the electrode plate area of the storage capacitor Cst1, the performance of the storage capacitor Cst1 can also be adjusted by adjusting the electrode plate film thickness of the storage capacitor Cst1 of different sub-pixels, the spacing between adjacent electrode plates (for example, the spacing between the first electrode plate and the second electrode plate and / or the spacing between the second electrode plate and the third electrode plate), the shape of the electrode plate and other parameters to meet the different performance requirements of different sub-pixels for the storage capacitor Cst1.

[0195] At least one embodiment of the present disclosure further provides a display panel. Figure 9 A schematic diagram of a display panel provided by at least one embodiment of the present disclosure. Figure 9 As shown, the display panel 700 includes the display substrate 100 provided by any embodiment of the present disclosure, for example, Figure 1 The display substrate 100 shown in FIG.

[0196] For example, the display panel 700 may be a liquid crystal display panel or an organic light emitting diode (OLED) display panel. For example, when the display panel 700 is a liquid crystal display panel, the display substrate 100 may be an array substrate or a color filter substrate. When the display panel 700 is an organic light emitting diode display panel, the display substrate 100 may be an array substrate.

[0197] For example, the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, etc. In addition, the display panel 700 may be not only a flat panel but also a curved panel or even a spherical panel.

[0198] For example, the display panel 700 may also have a touch function, that is, the display panel 700 may be a touch display panel.

[0199] For example, the display panel 700 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0200] For example, the display panel 700 may be a flexible display panel, so as to meet various practical application requirements. For example, the display panel 700 may be applied to a curved screen, etc.

[0201] It should be noted that the display panel 700 may also include other components, such as a data driver circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure. For the sake of clarity and brevity, the embodiments of the present disclosure do not illustrate all components of the display panel 700. To achieve the basic functions of the display panel 700, those skilled in the art may provide and configure other structures not shown according to specific needs, which are not limited in the embodiments of the present disclosure.

[0202] Regarding the technical effects of the display panel 700 provided in the above embodiment, reference may be made to the technical effects of the display substrate 100 provided in the embodiment of the present disclosure, which will not be repeated here.

[0203] Regarding this disclosure, the following points need to be explained:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0205] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe the embodiments of the present invention are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0206] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0207] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels arranged on the base substrate; Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, and the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, an anti-leakage electronic circuit, and a storage sub-circuit; The driving subcircuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light emitting element; The data writing sub-circuit is connected to the first terminal of the driving sub-circuit, the data line and the scan signal line, and is configured to write the data signal provided by the data line into the first terminal of the driving sub-circuit in response to the gate scan signal provided by the scan signal line; The threshold compensation sub-circuit is connected to the second terminal of the driving sub-circuit, the leakage prevention electronic circuit and the scanning signal line, and is configured to write a compensation signal based on the data signal into the control terminal of the driving sub-circuit in response to a gate scanning signal provided by the scanning signal line; The leakage prevention electronic circuit is connected to the control terminal of the driving sub-circuit, the threshold compensation sub-circuit, the storage sub-circuit and the leakage prevention control signal line, and is configured to suppress leakage of the control terminal of the driving sub-circuit; The storage sub-circuit is connected to the control terminal of the driving sub-circuit and the first voltage line, and is configured to store the compensation signal and keep it at the control terminal of the driving sub-circuit. In which, the storage subcircuit includes a storage capacitor, and the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are located in different layers relative to the base substrate, and the second electrode plate at least partially overlaps with the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.

2. The display substrate according to claim 1, wherein In a direction perpendicular to the base substrate, the second electrode plate is located between the first electrode plate and the third electrode plate; The first electrode plate is connected to the control end of the driving sub-circuit, the second electrode plate is connected to the first voltage line, and the third electrode plate is connected to the control end of the driving sub-circuit.

3. The display substrate according to claim 1 or 2, wherein: The threshold compensation sub-circuit includes a threshold compensation transistor, and the data writing sub-circuit includes a data writing transistor; The active layer of the threshold compensation transistor and the active layer of the data writing transistor are formed integrally, and the orthographic projections of the active layer of the threshold compensation transistor and the active layer of the data writing transistor on the base substrate are respectively located on both sides of the orthographic projection of the storage capacitor on the base substrate; The gate of the threshold compensation transistor and the gate of the data writing transistor are parallel in a first direction, and the gate of the threshold compensation transistor and the gate of the data writing transistor are integrally formed with the scanning signal line.

4. The display substrate according to claim 3, wherein: The leakage prevention electronic circuit includes an anti-leakage transistor, an active layer of the anti-leakage transistor, an active layer of the threshold compensation transistor, and an active layer of the data writing transistor all extend along a second direction and are arranged side by side along the first direction, and the first direction and the second direction intersect; The orthographic projection of the active layer of the leakage protection transistor on the substrate is located on a side of the orthographic projection of the active layer of the threshold compensation transistor on the substrate away from the orthographic projection of the active layer of the data writing transistor on the substrate.

5. The display substrate according to claim 4, wherein: The gate of the anti-leakage transistor and the anti-leakage control signal line are formed integrally, the anti-leakage control signal line extends along the first direction, and the orthographic projection of the anti-leakage control signal line on the base substrate is located between the orthographic projection of the scanning signal line on the base substrate and the orthographic projection of the storage capacitor on the base substrate.

6. The display substrate according to claim 4, wherein: The anti-leakage control signal line includes a first sub-control signal line and a second sub-control signal line. The orthographic projection of the first sub-control signal line on the base substrate and the orthographic projection of the second sub-control signal line on the base substrate at least partially overlap.

7. The display substrate according to claim 6, wherein: The gate of the anti-leakage transistor includes a first gate and a second gate, The first gate is formed integrally with the first sub-control signal line, and the second gate is formed integrally with the second sub-control signal line. In a direction perpendicular to the substrate, the active layer of the leakage protection transistor is located between the first gate and the second gate.

8. The display substrate according to any one of claims 4 to 7, wherein: The active layer of the anti-leakage transistor and the third electrode plate are located on the same layer; The active layer of the anti-leakage transistor and the third electrode plate are made of oxide semiconductor materials.

9. The display substrate according to any one of claims 4 to 7, wherein: The pixel circuit further includes a first reset subcircuit; Among them, the first reset sub-circuit is connected to the threshold compensation sub-circuit, the leakage prevention electronic circuit, the first initial signal line and the first reset control signal terminal, and is configured to apply the initial voltage provided by the first initial signal line to the control terminal of the driving sub-circuit through the leakage prevention electronic circuit in response to the reset control signal received by the first reset control signal terminal.

10. The display substrate according to claim 9, wherein: The first reset subcircuit includes a first reset transistor; The active layer of the first reset transistor and the active layer of the threshold compensation transistor are formed integrally; The orthographic projection of the active layer of the first reset transistor on the substrate is located on a side of the orthographic projection of the active layer of the threshold compensation transistor on the substrate away from the orthographic projection of the storage capacitor on the substrate.

11. The display substrate according to claim 10, further comprising: a first connecting electrode, wherein the first end of the first connecting electrode is integrally formed with the first electrode of the first reset transistor and the first electrode of the threshold compensation transistor, and is respectively connected to the active layer of the threshold compensation transistor and the active layer of the first reset transistor through a via hole penetrating the insulating layer; The second end of the first connecting electrode is formed integrally with the first electrode of the anti-leakage transistor, and is connected to the active layer of the anti-leakage transistor through a via hole penetrating the insulating layer.

12. The display substrate according to claim 11, further comprising: the second connecting electrode, The first end of the second connecting electrode is integrally formed with the second electrode of the anti-leakage transistor and is connected to the active layer of the anti-leakage transistor through a via hole penetrating the insulating layer; The second end of the second connecting electrode is connected to the first electrode plate of the storage capacitor through a via hole penetrating the insulating layer; The third end of the second connecting electrode is connected to the third electrode plate of the storage capacitor through a via hole penetrating the insulating layer.

13. The display substrate according to claim 12, further comprising: a parasitic capacitor connected to the second electrode of the anti-leakage transistor and the scanning signal line; Wherein, the first electrode plate of the parasitic capacitor is formed integrally with the scanning signal line. The second electrode plate of the parasitic capacitor at least partially overlaps with the first electrode plate of the parasitic capacitor in a direction perpendicular to the base substrate, the second electrode plate of the parasitic capacitor and the third electrode plate of the storage capacitor are located on the same layer, and an orthographic projection of the second electrode plate of the parasitic capacitor on the base substrate is located between an orthographic projection of the active layer of the threshold compensation transistor on the base substrate and an orthographic projection of the active layer of the data writing transistor on the base substrate; The second electrode plate of the parasitic capacitor is connected to the fourth end of the second connection electrode through a via hole penetrating the insulating layer.

14. The display substrate according to claim 13, wherein: The driving sub-circuit includes a driving transistor, The gate of the driving transistor is integrally formed with the first electrode plate of the storage capacitor; The active layer of the driving transistor, the active layer of the data writing transistor and the active layer of the threshold compensation transistor are formed integrally, and the orthographic projection of the active layer of the driving transistor on the base substrate is located between the orthographic projection of the active layer of the data writing transistor on the base substrate and the orthographic projection of the active layer of the threshold compensation transistor on the base substrate.

15. The display substrate according to claim 14, wherein: The pixel circuit further includes a first light emitting control subcircuit and a second light emitting control subcircuit. The first light-emitting control sub-circuit is connected to the first voltage line, the first terminal of the driver sub-circuit, and the light-emitting control signal line, and is configured to apply a first voltage provided by the first voltage line to the first terminal of the driver sub-circuit in response to a light-emitting control signal provided by the light-emitting control signal line; The second light emitting control sub-circuit is connected to the second end of the driving sub-circuit, the first end of the light emitting element, and the light emitting control signal line, and is configured to respond to a light emitting control signal provided by the light emitting control signal line so that the driving current is applied to the first end of the light emitting element; The light-emitting control signal line extends along the first direction, and the orthographic projection of the light-emitting control signal line on the base substrate is located on a side away from the orthographic projection of the storage capacitor on the base substrate and away from the orthographic projection of the scanning signal line on the base substrate.

16. The display substrate according to claim 15, wherein: The first light emission control subcircuit includes a first light emission control transistor, and the second light emission control subcircuit includes a second light emission control transistor; The active layer of the first light-emitting control transistor, the active layer of the second light-emitting control transistor, the active layer of the data writing transistor, the active layer of the threshold compensation transistor and the active layer of the driving transistor are formed integrally, and the orthographic projection of the active layer of the driving transistor on the base substrate is located between the orthographic projections of the active layer of the data writing transistor and the active layer of the first light-emitting control transistor on the base substrate and the orthographic projections of the active layer of the second light-emitting control transistor and the active layer of the threshold compensation transistor on the base substrate.

17. The display substrate according to claim 15 or 16, wherein: The anti-leakage control signal provided by the anti-leakage control signal line is the same as or different from the light-emitting control signal provided by the light-emitting control signal line.

18. The display substrate according to claim 16, wherein: The first voltage line includes a first sub-voltage line extending along the second direction and a second sub-voltage line extending along the first direction, The first sub-voltage line and the second sub-voltage line are located in different layers; An orthographic projection of the first sub-voltage line on the base substrate is located between an orthographic projection of the active layer of the data writing transistor on the base substrate and an orthographic projection of the active layer of the threshold compensation transistor on the base substrate, and at least partially overlaps with an orthographic projection of the second electrode plate of the parasitic capacitor on the base substrate; The second sub-voltage line is formed integrally with the second electrode plate of the storage capacitor.

19. The display substrate according to claim 18, further comprising: The third connecting electrode, The first end of the third connection electrode is integrally formed with the first electrode of the first light emission control transistor and is connected to the active layer of the first light emission control transistor through a via hole penetrating the insulating layer. The second end of the third connecting electrode is connected to the second electrode plate of the storage capacitor through a via hole penetrating the insulating layer; The third end of the third connection electrode is connected to the first protrusion of the first sub-voltage line through a via hole penetrating the insulating layer.

20. The display substrate according to claim 19, wherein The first sub-voltage line further includes a second protrusion, which is in a U-shaped shape, and an orthographic projection of the second protrusion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the anti-leakage transistor on the base substrate.

21. A display panel comprising the display substrate according to any one of claims 1 to 20.

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