Wafer level vacuum packaged MEMS device and method of fabrication thereof
By forming top deep holes and comb-like structures on SOI silicon wafers, and combining high-vacuum bonding and etching to form isolated islands, the problems of large electrode lead-out area and complex processes in wafer-level vacuum packaging of MEMS devices are solved, achieving small-volume packaging and efficient production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN ZHIMO TECH CO LTD
- Filing Date
- 2022-10-24
- Publication Date
- 2026-06-26
AI Technical Summary
Existing wafer-level vacuum packaging for MEMS devices suffers from problems such as large electrode lead-out area, complex processes, and high bonding difficulty.
Using SOI silicon wafers as substrates, deep reactive ion etching is used to form top deep holes and anchor points, conductive materials are deposited to form a comb structure, and high vacuum bonding and etching are combined to form isolation islands, achieving vertical electrical connection and hermetic packaging.
It effectively reduces the area occupied by electrode leads and hermetic packaging, simplifies the process flow, reduces packaging costs and improves yield.
Smart Images
Figure CN115709970B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a wafer-level vacuum-packaged MEMS device and its fabrication method, belonging to the field of microelectromechanical systems (MEMS) packaging technology. Background Technology
[0002] Many high-precision MEMS devices, such as MEMS resonators, MEMS gyroscopes, and MEMS accelerometers, require operation in high vacuum and low-stress environments. MEMS vacuum packaging can meet these requirements, including device-level packaging and wafer-level packaging. Device-level packaging is relatively mature, but it is more expensive and the process is more complex. In contrast, wafer-level packaging has simpler processes and lower costs. Wafer-level packaging bonding technologies mainly include silicon-glass anodic bonding, silicon-silicon fused bonding, and gold-silicon eutectic bonding. In these vacuum packaging solutions, the internal and external electrical connections of MEMS devices can easily affect the hermeticity of the vacuum packaging structure; therefore, the electrode lead-out method of the vacuum packaging structure is crucial.
[0003] In existing technologies, there are many ways to bring out electrodes in the wafer-level vacuum packaging structure of MEMS devices, mainly including:
[0004] Chinese patent applications CN101780942A and CN101941673A disclose wafer-level vacuum packaging methods for MEMS devices and microelectromechanical systems, respectively. Both methods involve first fabricating V-shaped vias on a silicon or glass cover plate, then fabricating lead-out electrodes for the MEMS device within the vias, and finally fabricating a metal ring between the V-shaped vias and the electrodes to ensure hermeticity. The electrode lead-out methods and hermetic packaging methods in these two prior art applications occupy a significant amount of space.
[0005] Chinese patent application CN102556956A discloses a vacuum packaging structure and fabrication method for MEMS devices. It adopts electrode lateral lead-out technology, which leads the electrodes of MEMS devices to external pads through isolation islands and metal or polysilicon leads. However, the lead-out electrodes are outside the device, which wastes a lot of cover plate area.
[0006] Chinese patent application CN102583220A discloses a wafer-level vacuum packaged infrared detector and its fabrication method. It adopts through-silicon via (TSV) technology, which achieves vertical electrode lead-out through processes such as preparing through-silicon vias, through-hole insulating layers, and through-hole metallization. This can save packaging area. However, TSV technology is complex and costly. Moreover, the through-hole insulating layer is relatively thin and has a large unfolded area, which introduces a large parasitic capacitance between the electrodes and reduces the performance of the device.
[0007] Chinese patent application CN103879952A discloses a method for fabricating a vacuum packaging structure for MEMS devices. This method employs a vertical electrode lead-out technique, involving etching a closed annular groove in a lower substrate perpendicular to the MEMS device to form an island-shaped support structure, and then opening windows to lead out electrodes. The electrodes are surrounded by an insulating layer and an epitaxial layer for electrical isolation. However, this technique is complex, requiring two wafer bonding processes, and the wafers for the structural layers are typically thin, making bonding difficult.
[0008] Therefore, providing a novel wafer-level vacuum-packaged MEMS device and its fabrication method has become a pressing technical problem to be solved in this field. Summary of the Invention
[0009] To address the problems of large footprint, complex processes, and difficult bonding in existing technologies for electrode lead-out and hermetic packaging, the present invention aims to provide a wafer-level vacuum-packaged MEMS device and its fabrication method.
[0010] To achieve the above objectives, in one aspect, the present invention provides a method for fabricating a wafer-level vacuum-packaged MEMS device, wherein the fabrication method includes:
[0011] Step 1: Using an SOI silicon wafer as a substrate, the SOI silicon wafer includes a top silicon layer, a buried oxide layer, and a substrate silicon layer from top to bottom. Deep etching is performed on the top silicon layer and the buried oxide layer to form a top deep hole.
[0012] Step 2: After cleaning the oxide layer formed on the hole wall during the fabrication of the top deep hole, deposit conductive material on the top silicon surface to fill the top deep hole;
[0013] Step 3: Remove excess conductive material from the top silicon surface to achieve planarization and form anchor points within the top deep holes;
[0014] Step 4: Deeply etch the top silicon layer to form a comb structure, then etch away the buried oxide layer beneath the comb structure to release the comb structure and obtain the wafer-level MEMS device structure.
[0015] Step 5: Etch grooves on the lower surface of the cover plate wafer to obtain the wafer cover plate;
[0016] Step 6: Perform high-vacuum bonding between the wafer-level MEMS device structure and the wafer cover plate. After bonding, the groove and the comb structure form an airtight chamber.
[0017] Step 7: Form isolation islands within the substrate silicon, and form a vertical electrical connection between the isolation islands and the anchor points;
[0018] Step 8: Deposit a passivation layer on the lower surface of the substrate silicon, and make a window at the passivation layer on the lower surface of the isolation island. Then, fabricate substrate electrode leads in the window to complete the fabrication of the wafer-level vacuum packaged MEMS device.
[0019] In one specific embodiment of the fabrication method described above in this invention, in step 1, the top silicon layer and the buried oxide layer are deeply etched by a deep reactive ion etching process to form a deep hole.
[0020] In one specific embodiment of the manufacturing method described above in this invention, in step 2, a conductive material is deposited on the surface of the top silicon layer and the deep holes are filled by a low-pressure chemical vapor deposition process.
[0021] In one specific embodiment of the manufacturing method described above, in step 2, the conductive material includes doped polycrystalline silicon or a metal. The metal used as the conductive material includes aluminum, gold, or copper, and the doping type of the doped polycrystalline silicon can be n-type (e.g., phosphorus) or p-type (e.g., boron).
[0022] In one specific embodiment of the manufacturing method described above in this invention, in step 3, excess conductive material on the top silicon surface is removed by a chemical mechanical polishing process.
[0023] In this invention, the number of anchor points formed in step 3 is the same as the number of top deep holes formed in step 1; and the number of top deep holes and anchor points can be reasonably determined according to the actual needs of the MEMS device. For example, in some embodiments of this invention, the number of top deep holes and anchor points can be 2, 3 or more.
[0024] As a specific embodiment of the fabrication method described above in this invention, in step 4, the top silicon is deeply etched to form a comb structure by a deep reactive ion etching process, and then the buried oxide layer below the comb structure is etched away by a hydrofluoric acid vapor phase etching process to release the comb structure and ensure that the movable part of the wafer-level MEMS device structure is suspended.
[0025] In this invention, the comb structure obtained in step 4 is fixed to the silicon substrate by anchor points, and the two comb structures resonate and move with each other. Furthermore, this invention does not impose specific requirements on the relationship between the position and number of the comb structures and the position and number of the anchor points, nor on the specific number of teeth in the comb structure; these can be reasonably set according to the actual needs of wafer-level vacuum-packaged MEMS devices.
[0026] In one specific embodiment of the manufacturing method described above, in step 5, the depth of the groove is 3-5 μm.
[0027] In one specific embodiment of the manufacturing method described above, in step 5, the cover plate wafer includes a silicon wafer or a borosilicate glass wafer. The silicon wafer described in this invention is a conventional silicon wafer.
[0028] In one specific embodiment of the manufacturing method described above, in step 5, grooves are etched on the lower surface of the cover plate wafer using a dry etching process to obtain the wafer cover plate.
[0029] In one specific embodiment of the manufacturing method described above, in step 6, the high vacuum bonding includes high vacuum silicon-silicon bonding or high vacuum anodic bonding.
[0030] As a specific embodiment of the manufacturing method described above in this invention, step 6 and step 7 further include: thinning the lower surface of the substrate silicon.
[0031] As a specific embodiment of the manufacturing method described above in this invention, step 7 specifically includes:
[0032] Based on the location of the anchor point, the substrate silicon corresponding to the anchor point is deeply etched using a deep reactive ion etching process to form a bottom deep hole. During the fabrication of the bottom deep hole, an oxide layer is formed (grown) on the hole wall. The substrate silicon with the sidewall covered by the oxide layer forms an isolation island, and the isolation island forms a vertical electrical connection with the anchor point.
[0033] This invention uses an oxide layer and deep holes at the bottom to isolate the isolation island, thereby enabling the anchor point to form a vertical electrical connection with the substrate silicon below, i.e. the isolation island and the substrate electrode leads, forming an independent region.
[0034] As a specific embodiment of the manufacturing method described above in this invention, the method for manufacturing the isolated island includes the following specific steps:
[0035] Based on the location of the anchor point, the substrate silicon corresponding to the anchor point is deeply etched using a deep reactive ion etching process to form a bottom deep hole that runs through the width of the substrate silicon. During the fabrication of the bottom deep hole, an oxide layer is formed (grown) on the hole wall. The substrate silicon with the sidewalls (in this case, both sidewalls) covered by the oxide layer forms an isolation island, and the isolation island forms a vertical electrical connection with the anchor point.
[0036] Alternatively, depending on the location of the anchor point, the substrate silicon corresponding to the anchor point is deeply etched along the width and length directions of the substrate silicon using a deep reactive ion etching process to form a bottom deep hole that does not penetrate the substrate silicon in either the length or width direction. During the fabrication of the bottom deep hole, an oxide layer is formed (grown) on the hole wall. The substrate silicon with the sidewalls (in this case, four sidewalls) covered by the oxide layer forms an isolation island, and the isolation island forms a vertical electrical connection with the anchor point.
[0037] In a specific embodiment of the manufacturing method described above in this invention, in step 8, the material of the passivation layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon dioxide.
[0038] In one specific embodiment of the manufacturing method described above, in step 8, substrate electrode leads are fabricated in the window using a sputtering process or a chemical vapor deposition process.
[0039] In one specific embodiment of the fabrication method described above, in step 8, the material of the substrate electrode leads includes aluminum, gold, copper, or polycrystalline silicon. Specifically, when the substrate electrode leads are fabricated using a sputtering process during windowing, the material can be metals such as aluminum, gold, or copper; when the substrate electrode leads are fabricated using a chemical vapor deposition process during windowing, the material can be polycrystalline silicon.
[0040] In this invention, deep reactive ion etching, low-pressure chemical vapor deposition, chemical mechanical polishing, hydrofluoric acid vapor etching, high-vacuum silicon bonding, high-vacuum anodic bonding, dry etching, sputtering, and chemical vapor deposition are all conventional processes used in the field. The operation steps and process parameters involved in the process can be reasonably adjusted according to the actual needs of the field operation.
[0041] On the other hand, the present invention also provides a wafer-level vacuum packaged MEMS device, wherein the wafer-level vacuum packaged MEMS device includes a wafer-level MEMS device structure and a wafer cover plate, and the lower surface of the wafer cover plate is provided with a groove.
[0042] The wafer-level MEMS device structure is made of SOI silicon wafer, which includes a top silicon layer, a buried oxide layer and a substrate silicon layer from top to bottom. The SOI silicon wafer is provided with anchor points that penetrate the top silicon layer and the buried oxide layer, and a comb structure is provided in the top silicon layer.
[0043] An isolation island is provided in the substrate silicon corresponding to the anchor point, and the isolation island forms a vertical electrical connection with the anchor point. The isolation island is a substrate silicon with its sidewalls covered by an oxide layer.
[0044] A passivation layer is provided on the lower surface of the silicon substrate, and a window is opened at the passivation layer on the lower surface of the isolation island, and a substrate electrode lead is provided in the window.
[0045] The wafer cover and the upper part of the wafer-level MEMS device structure are bonded by high vacuum, and the groove and the comb structure form an airtight chamber.
[0046] Compared with the prior art, the beneficial technical effects achieved by the present invention include:
[0047] The wafer-level vacuum-packaged MEMS device fabrication method provided by this invention directly uses SOI silicon wafers as substrates. Anchor points and comb-like structures of the wafer-level MEMS device structure are fabricated on the top silicon layer, and the vacuum cavity is released. Multiple bottom deep holes are etched on the bottom silicon layer to form isolation islands. These isolation islands form a vertical electrical connection with the anchor points of the wafer-level MEMS device structure. The oxide layer surrounding the isolation islands and the bottom deep holes are used to achieve electrical isolation between the isolation islands and their surroundings. By vertically leading out the electrodes of the wafer-level MEMS device structure, this invention can effectively reduce the area occupied by electrode leads and hermetic packaging. Using a high-vacuum bonding method with two wafers, the wafer-level MEMS device structure fabricated from SOI silicon wafers is sealed in a groove on the lower surface of the wafer cover plate to form a hermetic chamber. This method has the advantage of simple process and can further effectively reduce the area occupied by electrode leads and hermetic packaging.
[0048] In summary, the manufacturing method provided by this invention reduces the difficulty of the process and the cost of packaging, enables small-volume packaging, and improves the product yield. Attached Figure Description
[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] Figure 1 This is a schematic diagram of the SOI silicon wafer used in step 1 of the method for fabricating a wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention.
[0051] Figures 2-3 This is a schematic diagram of step 1 of the method for fabricating a wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, which involves fabricating a top deep hole and growing an oxide layer on the hole wall.
[0052] Figure 4This is a schematic diagram illustrating the cleaning of excess oxide layer on the top deep hole wall in step 2 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 1 of the present invention.
[0053] Figure 5 This is a schematic diagram of step 2 of the method for fabricating a wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, in which a conductive material is deposited on the upper surface of the top silicon layer and the top deep hole is filled.
[0054] Figure 6 This is a schematic diagram of step 3 in the fabrication method of the wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, which involves removing excess conductive material from the upper surface of the top silicon layer to achieve planarization and form anchor points.
[0055] Figure 7 This is a schematic diagram of the deep etching of the top silicon layer in step 4 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 1 of the present invention.
[0056] Figures 8-9 This is a schematic diagram illustrating the completion of the comb structure fabrication in step 4 of the wafer-level vacuum-packaged MEMS device fabrication method provided in Embodiment 1 of the present invention.
[0057] Figure 10 This is a schematic diagram of the silicon wafer cover plate obtained in step 5 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 1 of the present invention.
[0058] Figure 11 This is a schematic diagram of the structure obtained after high-vacuum silicon-silicon bonding in step 6 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 1 of the present invention.
[0059] Figure 12 This is a schematic diagram of step 7 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 1 of the present invention, which involves thinning the substrate silicon.
[0060] Figure 13 This is a schematic diagram of step 7 in the fabrication method of the wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, in which an isolated island is formed and vertically electrically connected to the anchor point.
[0061] Figure 14 This is a schematic diagram of step 8 of the method for fabricating a wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, in which a passivation layer is deposited on the lower surface of the substrate silicon.
[0062] Figure 15This is a schematic diagram of step 8 in the fabrication method of the wafer-level vacuum-packaged MEMS device provided in Embodiment 1 of the present invention, which is also a schematic diagram of the structure of the wafer-level vacuum-packaged MEMS device obtained in Embodiment 1.
[0063] Figure 16 This is a schematic diagram illustrating the completion of the comb structure fabrication in step 4 of the wafer-level vacuum-packaged MEMS device fabrication method provided in Embodiment 2 of the present invention.
[0064] Figure 17 This is a schematic diagram of step 8 in the fabrication method of the wafer-level vacuum packaged MEMS device provided in Embodiment 2 of the present invention, which is also a schematic diagram of the structure of the wafer-level vacuum packaged MEMS device obtained in Embodiment 2.
[0065] Figure 18 This is a schematic diagram of the borosilicate glass wafer cover plate used in step 5 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 3 of the present invention.
[0066] Figure 19 This is a schematic diagram of the structure obtained after high vacuum anodic bonding in step 6 of the method for fabricating a wafer-level vacuum packaged MEMS device provided in Embodiment 3 of the present invention, which is also a schematic diagram of the structure of the wafer-level vacuum packaged MEMS device obtained in Embodiment 3.
[0067] Explanation of main icon numbers:
[0068] 1. SOI silicon wafer;
[0069] 101. Top layer silicon;
[0070] 102. Buried oxygen layer;
[0071] 103. Substrate silicon;
[0072] 104. First oxide layer;
[0073] 104 ， Second oxide layer;
[0074] 105. Deep hole at the top;
[0075] 106. Conductive materials;
[0076] 107. Anchor point;
[0077] 108. Comb-like structure;
[0078] 109. Isolated island;
[0079] 110. Passivation layer;
[0080] 111. Substrate electrode leads;
[0081] 112. Deep hole at the bottom;
[0082] 2. Conventional silicon wafers;
[0083] 201. Silicon wafer cover plate;
[0084] 3. Borosilicate glass wafers;
[0085] 301. Borosilicate glass wafer cover. Detailed Implementation
[0086] It should be noted that the term "comprising" and any variations thereof in the specification, claims, and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0087] In this invention, the terms "upper," "lower," "inner," "outer," and "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.
[0088] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.
[0089] Furthermore, the terms "setup" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0090] The "range" disclosed in this invention is given in the form of a lower limit and an upper limit. It can be one or more lower limits and one or more upper limits, respectively. A given range is defined by selecting a lower limit and an upper limit. The selected lower and upper limits define the boundaries of the particular range. All ranges defined in this way are composable, meaning that any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for specific parameters, it is also expected that ranges of 60-110 and 80-120 are also expected. Furthermore, if the listed minimum range values are 1 and 2, and the listed maximum range values are 3, 4, and 5, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5.
[0091] In this invention, unless otherwise specified, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this invention, and "0-5" is simply a shortened representation of these numerical combinations.
[0092] In this invention, unless otherwise specified, all embodiments and preferred embodiments mentioned in this invention can be combined with each other to form new technical solutions.
[0093] In this invention, unless otherwise specified, all technical features and preferred features mentioned in this invention can be combined with each other to form new technical solutions.
[0094] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The embodiments described below are some, but not all, embodiments of this invention, and are only used to illustrate the invention, and should not be considered as limiting the scope of the invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0095] Example 1
[0096] This embodiment provides a method for fabricating a wafer-level vacuum-packaged MEMS device, as shown in the schematic diagram below. Figures 1-15 As shown, from Figures 1-15 As can be seen from the above, the manufacturing method includes the following specific steps:
[0097] Step 1: As Figure 1As shown, an SOI silicon wafer 1 is provided, which includes a top silicon layer 101, a buried oxide layer 102, and a substrate silicon 103. Figures 2-3 As shown, the top silicon 101 and buried oxide layer 102 are deeply etched by the deep reactive ion etching (DRIE) process to form a top deep hole 105. During the fabrication of the top deep hole 105, a first oxide layer 104 will grow on the hole wall of the top deep hole 105.
[0098] Step 2: As Figure 4 As shown, the excess first oxide layer 104 on the wall of the top deep hole 105 is cleaned; as... Figure 5 As shown, a conductive material 106 is deposited on the upper surface of the SOI silicon wafer 1, i.e. the upper surface of the top silicon 101, using a low-pressure chemical vapor deposition (LPCVD) process, and the top deep hole 105 is filled. The conductive material 106 is doped polycrystalline silicon or a metal. The metal can be, for example, aluminum, gold, or copper. The doping type of the doped polycrystalline silicon can be, for example, n-type (such as phosphorus) or p-type (such as boron).
[0099] Step 3: As Figure 6 As shown, excess conductive material 106 on the upper surface of SOI silicon wafer 1, i.e. the upper surface of top silicon 101, is removed by chemical mechanical polishing (CMP) to achieve planarization and to form anchor points 107 of wafer-level MEMS device structure in the top deep hole 105.
[0100] Step 4: As Figure 7 As shown, the top silicon 101 between the two anchor points is deeply etched using the DRIE process to form a comb structure 108; then, the buried oxide layer 102 beneath the comb structure 108 is etched away using a hydrofluoric acid (HF) vapor phase etching process, releasing the comb structure 108 and ensuring that the movable part of the wafer-level MEMS device structure is suspended. A schematic diagram of this step is shown below. Figures 8-9 As shown, Figure 8 and Figure 9 The diagram shows two anchor points 107 and one comb structure 108;
[0101] Step 5: As Figure 10 As shown, a conventional silicon wafer 2 is provided, and a groove corresponding to the wafer-level MEMS device structure is dry etched on the lower surface of the conventional silicon wafer 2 to form a silicon wafer cover plate 201, wherein the groove depth is 3-5μm;
[0102] Step 6: As Figure 11As shown, the silicon wafer cover plate 201 obtained in step 5 is bonded to the wafer-level MEMS device structure obtained in step 4 using high-vacuum silicon-silicon bonding. After bonding, the groove and the comb structure form an airtight chamber.
[0103] In this embodiment, a silicon wafer cover plate 201 is used, which is bonded to the wafer-level MEMS device structure obtained in step 4 by silicon-silicon bonding. Since the anchor point 107 is conductive, the groove edge of the silicon wafer cover plate 201 needs to be aligned with the outer edge of the anchor point 107 or located outside the outer edge of the anchor point 107 to prevent the anchor point 107 from being connected to the silicon wafer cover plate 201.
[0104] Step 7: As Figure 12 As shown, the substrate silicon 103 is thinned; as Figure 13 As shown, multiple bottom deep holes 112 are formed by deep etching on the lower surface of the substrate silicon 103 corresponding to both sides of any anchor point using the DRIE process. During the fabrication of the bottom deep holes 112, a second oxide layer 104 is grown around the bottom deep holes 112. ， The sidewall is covered with a second oxide layer 104 ， The encapsulated silicon substrate 103 forms an isolation island 109, which is vertically electrically connected to the anchor point 107, and the second oxide layer 104 ， The bottom deep hole 112 is used to achieve electrical isolation of the isolated island 109 from its surroundings;
[0105] Step 8: As Figure 14 As shown, a passivation layer 110 is deposited on the lower surface of the substrate silicon 103, wherein the material of the passivation layer includes one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and silicon dioxide; as shown Figure 15 As shown, a window is made below the isolation island 109, that is, at the passivation layer 110 on the lower surface, and a substrate electrode lead 111 is formed in the window by sputtering aluminum or chemical vapor deposition (CVD) polycrystalline silicon to complete the fabrication of the wafer-level vacuum packaged MEMS device.
[0106] Example 2
[0107] This embodiment provides a method for fabricating a wafer-level vacuum-packaged MEMS device, which differs from Embodiment 1 only in the number of anchor points 107 and comb-like structures 108. Figure 16 and Figure 17 As shown, it is provided with 3 anchor points 107 and 2 comb tooth structures 108 respectively, and the remaining steps are the same as in Example 1.
[0108] Example 3
[0109] This embodiment provides a method for fabricating a wafer-level vacuum packaged MEMS device, which differs from Embodiment 1 only in steps 5 and 6, with the remaining steps being the same as in Embodiment 1.
[0110] Step 5 is as follows: Figure 18 As shown, a borosilicate glass wafer 3 is provided, and grooves corresponding to the wafer-level MEMS device structure are etched on the lower surface of the borosilicate glass wafer 3 to form a borosilicate glass wafer cover plate 301, wherein the groove depth is 3-5μm;
[0111] Step 6 is: (e.g.) Figure 19 As shown, the borosilicate glass wafer cover plate 301 obtained in step 5 is bonded to the wafer-level MEMS device structure obtained in step 4 using high vacuum anodic bonding. After bonding, the groove and the comb structure form an airtight chamber.
[0112] In this embodiment, a borosilicate glass wafer cover plate 301 is used. It is anoly bonded to the wafer-level MEMS device structure obtained in step 4. Although the anchor point 107 is conductive, the borosilicate glass wafer cover plate 301 is insulating. Therefore, the groove edge of the borosilicate glass wafer cover plate 301 can be aligned with the outer edge of the anchor point 107, located outside the outer edge of the anchor point 107, or located inside the outer edge of the anchor point 107. Figure 19 The image shown illustrates this situation.
[0113] Example 4
[0114] This embodiment provides a wafer-level vacuum-packaged MEMS device, which is fabricated using the wafer-level vacuum-packaged MEMS device fabrication method provided in Embodiment 1:
[0115] The schematic diagram of the wafer-level vacuum-packaged MEMS device is shown below. Figure 15 As shown, from Figure 15 As can be seen from the above, it includes a wafer-level MEMS device structure and a silicon wafer cover plate 201, wherein the lower surface of the silicon wafer cover plate 201 is provided with a groove.
[0116] The wafer-level MEMS device structure is made of SOI silicon wafer 1, which includes a top silicon layer 101, a buried oxide layer 102, and a substrate silicon layer 103 from top to bottom. The SOI silicon wafer 1 is provided with anchor points 107 that penetrate the top silicon layer 101 and the buried oxide layer 102. A comb structure 108 is provided in the top silicon layer 101 between two anchor points 107. There are two anchor points 107 and one comb structure 108.
[0117] Bottom deep holes 112 are formed in the substrate silicon 103 on both sides of any anchor point 107, and the walls of the bottom deep holes 112 are covered with a second oxide layer 104.， The sidewall is covered with a second oxide layer 104 ， The encapsulated substrate silicon 103 forms an isolation island 109, and the isolation island 109 forms a vertical electrical connection with the anchor point 107;
[0118] A passivation layer 110 is provided on the lower surface of the substrate silicon 103, and a window is opened at the passivation layer 110 on the lower surface of the isolation island 109. A substrate electrode lead 111 is provided in the window, and the substrate electrode lead 111 is made of aluminum.
[0119] The silicon wafer cover plate 201 and the upper part of the wafer-level MEMS device structure are bonded by high-vacuum silicon-silicon bonding, and the groove and the comb structure 108 form an airtight cavity.
[0120] Example 5
[0121] This embodiment provides a wafer-level vacuum-packaged MEMS device, which is fabricated using the wafer-level vacuum-packaged MEMS device fabrication method provided in Embodiment 2. A schematic diagram of the structure is shown below. Figure 17 As shown, from Figure 17 As can be seen from the above, the wafer-level vacuum packaged MEMS device provided in this embodiment includes a wafer-level MEMS device structure and a silicon wafer cover plate 201, wherein the lower surface of the silicon wafer cover plate 201 is provided with a groove.
[0122] The wafer-level MEMS device structure is made of SOI silicon wafer 1, which includes a top silicon layer 101, a buried oxide layer 102 and a substrate silicon layer 103 from top to bottom. The SOI silicon wafer 1 is provided with anchor points 107 that penetrate the top silicon layer 101 and the buried oxide layer 102. There are 3 anchor points 107. A comb structure 108 is provided in the top silicon layer 101 between two adjacent anchor points 107. There are 2 comb structures 108.
[0123] Bottom deep holes 112 are formed in the substrate silicon 103 on both sides of any anchor point 107, and the walls of the bottom deep holes 112 are covered with a second oxide layer 104. ， The sidewall is covered with a second oxide layer 104 ， The encapsulated substrate silicon 103 forms an isolation island 109, and the isolation island 109 forms a vertical electrical connection with the anchor point 107;
[0124] A passivation layer 110 is provided on the lower surface of the substrate silicon 103, and a window is opened at the passivation layer 110 on the lower surface of the isolation island 109. A substrate electrode lead 111 is provided in the window, and the substrate electrode lead 111 is made of aluminum.
[0125] The silicon wafer cover plate 201 and the upper part of the wafer-level MEMS device structure are bonded by high-vacuum silicon-silicon bonding, and the groove and the comb structure 108 form an airtight cavity.
[0126] Example 6
[0127] This embodiment provides a wafer-level vacuum-packaged MEMS device, which is fabricated using the wafer-level vacuum-packaged MEMS device fabrication method provided in Embodiment 3:
[0128] The schematic diagram of the wafer-level vacuum-packaged MEMS device is shown below. Figure 19 As shown, from Figure 19 As can be seen from the above, it includes a wafer-level MEMS device structure and a borosilicate glass wafer cover plate 301, the lower surface of which is provided with a groove;
[0129] The material of the wafer-level MEMS device structure is an SOI silicon wafer 1, which includes a top silicon layer 101, a buried oxide layer 102 and a substrate silicon layer 103 from top to bottom. The SOI silicon wafer 1 is provided with anchor points 107 that penetrate the top silicon layer 101 and the buried oxide layer 102, and a comb structure 108 is provided in the top silicon layer 101 between the two anchor points 107.
[0130] Bottom deep holes 112 are formed in the substrate silicon 103 on both sides of any anchor point 107, and the walls of the bottom deep holes 112 are covered with a second oxide layer 104. ， The sidewall is covered with a second oxide layer 104 ， The encapsulated substrate silicon 103 forms an isolation island 109, and the isolation island 109 forms a vertical electrical connection with the anchor point 107. The anchor point 107 realizes the internal and external electrical connection of the wafer-level vacuum packaged MEMS device through the isolation island 109 and the substrate electrode lead 111.
[0131] A passivation layer 110 is provided on the lower surface of the substrate silicon 103, and a window is opened at the passivation layer 110 on the lower surface of the isolation island 109. A substrate electrode lead 111 is provided in the window, and the substrate electrode lead 111 is made of aluminum.
[0132] The borosilicate glass wafer cover plate 301 and the upper part of the wafer-level MEMS device structure are bonded by high vacuum anodic bonding, and the groove and the comb structure 108 form an airtight chamber.
[0133] The wafer-level vacuum-packaged MEMS device fabrication method provided in this invention directly uses an SOI silicon wafer as the substrate. Anchor points and comb-like structures of the wafer-level MEMS device structure are fabricated on the top silicon layer, and the vacuum cavity is released. Multiple deep holes are etched on the bottom silicon layer to form isolation islands. These isolation islands form a vertical electrical connection with the anchor points of the wafer-level MEMS device structure. The oxide layer surrounding the isolation islands and the deep holes are used to achieve electrical isolation between the isolation islands and their surroundings. By vertically leading out the electrodes of the wafer-level MEMS device structure, this invention can effectively reduce the area occupied by electrode leads and hermetic packaging. Using a high-vacuum bonding method with two wafers, the wafer-level MEMS device structure fabricated from the SOI silicon wafer is sealed in a groove on the lower surface of the wafer cover plate to form a hermetic chamber. This process is simple and can further effectively reduce the area occupied by electrode leads and hermetic packaging.
[0134] In summary, the manufacturing method provided by the embodiments of the present invention reduces the difficulty of the process and the packaging cost, enables small-volume packaging, and improves the product yield.
[0135] The above description is merely a specific embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any substitution of equivalent components or equivalent changes and modifications made within the scope of protection of this patent should still fall within the scope of this patent. Furthermore, the technical features, technical features and technical inventions, and technical inventions in this invention can be freely combined and used.
Claims
1. A method for fabricating a wafer-level vacuum-packaged MEMS device, characterized in that, The manufacturing method includes: Step 1: Using an SOI silicon wafer as a substrate, the SOI silicon wafer includes a top silicon layer, a buried oxide layer, and a substrate silicon layer from top to bottom. Deep etching is performed on the top silicon layer and the buried oxide layer to form a top deep hole. Step 2: After cleaning the oxide layer formed on the hole wall during the fabrication of the top deep hole, deposit conductive material on the top silicon surface to fill the top deep hole; Step 3: Remove excess conductive material from the top silicon surface to achieve planarization and form anchor points within the top deep holes; Step 4: Deeply etch the top silicon layer to form a comb structure, then etch away the buried oxide layer below the comb structure to release the comb structure and obtain the wafer-level MEMS device structure. Step 5: Etch grooves on the lower surface of the cover plate wafer to obtain the wafer cover plate; Step 6: Perform high-vacuum bonding between the wafer-level MEMS device structure and the wafer cover plate. After bonding, the groove and the comb structure form an airtight chamber. Step 7: Form isolation islands within the substrate silicon, and form a vertical electrical connection between the isolation islands and the anchor points; Step 8: Deposit a passivation layer on the lower surface of the substrate silicon, and make a window at the passivation layer on the lower surface of the isolation island. Then, fabricate substrate electrode leads in the window to complete the fabrication of the wafer-level vacuum packaged MEMS device.
2. The manufacturing method according to claim 1, characterized in that, In step 1, deep reactive ion etching is used to deeply etch the top silicon and buried oxide layer to form deep holes.
3. The manufacturing method according to claim 1, characterized in that, In step 2, conductive material is deposited on the top silicon surface and the deep holes are filled by low-pressure chemical vapor deposition.
4. The manufacturing method according to claim 1 or 3, characterized in that, The conductive material includes doped polycrystalline silicon or metal.
5. The manufacturing method according to claim 1, characterized in that, In step 3, excess conductive material on the top silicon surface is removed by chemical mechanical polishing.
6. The manufacturing method according to claim 1, characterized in that, In step 4, the top silicon is deeply etched to form a comb structure using a deep reactive ion etching process, and then the buried oxide layer under the comb structure is etched away using a hydrofluoric acid vapor phase etching process to release the comb structure.
7. The manufacturing method according to claim 1, characterized in that, In step 5, the depth of the groove is 3-5 μm.
8. The manufacturing method according to claim 1 or 7, characterized in that, In step 5, the cover plate wafer includes a silicon wafer or a borosilicate glass wafer.
9. The manufacturing method according to claim 1, characterized in that, In step 6, the high-vacuum bonding includes high-vacuum silicon-silicon bonding or high-vacuum anodic bonding.
10. The manufacturing method according to claim 1, characterized in that, Between steps 6 and 7, the lower surface of the substrate silicon is thinned.
11. The manufacturing method according to claim 1 or 10, characterized in that, Step 7 specifically includes: Based on the location of the anchor point, the substrate silicon corresponding to the anchor point is deeply etched to form a bottom deep hole. At the same time, an oxide layer is formed on the wall of the bottom deep hole. The substrate silicon with the sidewall covered by the oxide layer forms an isolation island, and the isolation island forms a vertical electrical connection with the anchor point.
12. The manufacturing method according to claim 1, characterized in that, In step 8, substrate electrode leads are fabricated in the window using sputtering or chemical vapor deposition processes.
13. The manufacturing method according to claim 1 or 12, characterized in that, In step 8, the substrate electrode leads are made of aluminum, gold, copper, or polycrystalline silicon.
14. A wafer-level vacuum-packaged MEMS device, characterized in that, The wafer-level vacuum-packaged MEMS device includes a wafer-level MEMS device structure and a wafer cover plate, wherein a groove is provided on the lower surface of the wafer cover plate. The wafer-level MEMS device structure is made of SOI silicon wafer, which includes a top silicon layer, a buried oxide layer and a substrate silicon layer from top to bottom. The SOI silicon wafer is provided with anchor points that penetrate the top silicon layer and the buried oxide layer, and a comb structure is provided in the top silicon layer. An isolation island is provided in the substrate silicon corresponding to the anchor point, and the isolation island forms a vertical electrical connection with the anchor point. The isolation island is a substrate silicon with its sidewalls covered by an oxide layer. A passivation layer is provided on the lower surface of the silicon substrate, and a window is opened at the passivation layer on the lower surface of the isolation island, and a substrate electrode lead is provided in the window. The wafer cover and the upper part of the wafer-level MEMS device structure are bonded by high vacuum, and the groove and the comb structure form an airtight chamber.