Motion control data high speed co-processing system and method

Abstract

The application provides a motion control data high-speed cooperative processing system and method, wherein the motion control data high-speed cooperative processing system comprises a master control card, a motion control card, a fiber interface card, a sensor acquisition card and a case, the case is provided with a backboard, the master control card, the motion control card and the fiber interface card are inserted on the backboard and are interconnected through the backboard bus; the sensor acquisition card, the fiber interface card and the motion control card are all provided with FPGA modules, and a front-end calculation module is arranged in the FPGA module of the sensor acquisition card, the fiber interface card or the motion control card, and the front-end calculation module is used for front-end calculation and obtaining front-end calculation data. The front-end calculation module is placed in the FPGA module, the calculation time is shortened, the servo cycle is shortened, and the motion control data processing speed is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-speed collaborative processing system and method for motion control data. Background Technology

[0002] Lithography machines are key equipment in IC manufacturing. With the development and advancement of lithography machines and their processes, the requirements for parallel computing, complex motion control algorithms, and real-time control in the lithography machine stage control system are becoming increasingly stringent. However, for motion control data processing of the lithography machine stage, only a DSP (Digital Signal Processor) is typically used as the motion control calculation processor. This results in a heavy workload, long processing time, low motion control data processing speed, and impacts servo cycle time and control accuracy.

[0003] For example, existing technologies propose a high-speed, large-volume information processing system that combines a multi-core DSP with an FPGA (Field-Programmable Gate Array). The multi-core DSP serves as the core data processing module, while the FPGA acts as the encoding, decoding, display, and control module, implementing a combined IMU (Inertial Measurement Unit), GPS (Global Positioning System), and starlight navigation algorithm. However, for high-end lithography equipment, a data processing capacity of 12,500 M / min using only a DSP is insufficient to meet the servo cycle requirements.

[0004] For example, existing technologies have proposed an embedded navigation information processor based on DSP and FPGA. This processor combines DSP and FPGA to achieve navigation data acquisition, processing, output, and other control. However, this scheme only has one half-duplex EMIF interface between the DSP and FPGA, and simultaneously connects FLASH (flash memory), SDRAM (Synchronous Dynamic RAM), and the FPGA. This limits the data exchange rate between the DSP and FPGA, and all navigation data processing is handled by the DSP, with the FPGA only responsible for the data channel, thus failing to fully utilize its computational power.

[0005] Therefore, there is an urgent need for a high-speed collaborative processing system and method for motion control data in lithography equipment to improve the processing speed of motion control data, reduce the computational load of DSP, and shorten the servo cycle. Summary of the Invention

[0006] The purpose of this invention is to provide a high-speed collaborative processing system and method for motion control data, so as to reduce the computational load of DSP modules, shorten computation time, shorten servo cycles, and thus improve the processing speed of motion control data.

[0007] To achieve the above and other related objectives, this invention provides a high-speed collaborative processing system for motion control data, comprising: a main control card, a motion control card, a fiber optic interface card, a sensor acquisition card, and a chassis, wherein...

[0008] The chassis is provided with a backplane, and the main control card, motion control card and fiber optic interface card are installed on the backplane and interconnected through the backplane bus;

[0009] The main control card is responsible for the control and scheduling of the entire system;

[0010] The sensor acquisition card converts sensor data into optical fiber signals and transmits the optical fiber signals to the optical fiber interface card through a communication optical fiber.

[0011] The fiber optic interface card forwards the fiber optic signals from the sensor acquisition card to the motion control card via internal synchronization.

[0012] The motion control card processes and calculates the fiber optic signals forwarded by the fiber optic interface card to obtain servo control data.

[0013] The sensor acquisition card, fiber optic interface card, and motion control card are all equipped with FPGA modules, and a front-end computing module is set in the FPGA module of the sensor acquisition card, fiber optic interface card, or motion control card. The front-end computing module is used for front-end computing and to acquire front-end computing data.

[0014] Optionally, in the high-speed collaborative processing system for motion control data, the system further includes a data acquisition card, which is used to acquire servo control data from the previous servo cycle, convert it into an optical fiber signal, and transmit the optical fiber signal to the optical fiber interface card through a communication optical fiber.

[0015] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the sensor acquisition card includes an ADC analog-to-digital converter module, a first FPGA module, and an optical fiber communication interface module, wherein...

[0016] The ADC analog-to-digital converter module converts sensor data into digital signals;

[0017] The first FPGA module is connected to the ADC module and the optical fiber communication interface module respectively, and it is used as a data channel to transmit the digital signal to the optical fiber communication interface.

[0018] The fiber optic communication interface converts the digital signal into a fiber optic signal and transmits the fiber optic signal to the fiber optic interface card.

[0019] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the fiber optic interface card includes a fiber optic communication module and a second FPGA module, wherein...

[0020] The optical fiber communication module receives the optical fiber signal transmitted by the sensor acquisition card or the data acquisition card;

[0021] The second FPGA module is connected to the optical fiber communication module and is used as a data channel.

[0022] Optionally, in the high-speed collaborative processing system for motion control data, the fiber optic interface card further includes an internal synchronization bus module, which is mounted on the backplane. The internal synchronization bus module receives data signals from other chassis and realizes synchronous control of the servo cycles of each chassis.

[0023] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the motion control card includes a clock module, a third FPGA module, a DSP module, and a program embedding module, wherein...

[0024] The third FPGA module is connected to the backplane bus through the VME interface module. The third FPGA module processes the optical fiber signals forwarded by the optical fiber interface card and transmits the processed data to the DSP module.

[0025] The DSP module is connected to the third FPGA module. The DSP module obtains the processed data from the third FPGA module through the PCIe interface module, and performs filtering and control algorithm calculations on the processed data transmitted by the third FPGA module according to the system configuration to obtain servo control data. The DSP module also transmits the obtained servo control data to the third FPGA module through the EMIF interface module.

[0026] The clock module is connected to the third FPGA module and provides a clock signal to the third FPGA module;

[0027] The program embedding module is connected to the third FPGA module. It is composed of a FLASH chip and is used to store the running programs of the third FPGA module and the DSP module. It will be automatically loaded after power-on.

[0028] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the third FPGA module includes: a data input module and a data buffer module, wherein,

[0029] The data input module receives the optical fiber signal forwarded by the optical fiber interface card, and converts, synthesizes, and parses the optical fiber signal;

[0030] The data cache module consists of the block random access memory inside the third FPGA module, which maps the register space of the PCIe interface module, allowing the DSP module to read data through the PCIe interface module.

[0031] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the data input module includes a QSFP optical module, an FPGA serial-to-parallel conversion IP core, and a protocol parsing submodule, wherein...

[0032] The QSFP optical module is used to convert the optical fiber signal forwarded by the optical fiber interface card into a high-speed differential serial signal for processing by the FPGA serial-to-parallel conversion IP core.

[0033] The FPGA serial-to-parallel conversion IP core is used to sample, align, and decode the high-speed differential serial signal, and combine it into parallel data;

[0034] The protocol parsing submodule parses the frame type and specific data of the parallel data according to the communication protocol frame format.

[0035] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the front-end computing module includes a parameter cache register, a data cache register, a linear correction submodule, and a pulsation matrix submodule, wherein...

[0036] The parameter buffer register is used to store the initial input data acquired by the data acquisition card or sensor acquisition card, and the sensor data or the servo control data of the previous servo cycle is used as the initial input data;

[0037] The linear correction submodule performs linear correction on the initial input data;

[0038] The pulsation matrix submodule preprocesses the corrected initial input data to obtain front-end calculation data;

[0039] The data cache register is used to cache the front-end computation data.

[0040] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the pulse matrix submodule comprises several PE multiply-accumulate calculation units, and each PE multiply-accumulate calculation unit includes a floating-point multiplier, a floating-point adder, and a delay register.

[0041] The floating-point multiplier is used for floating-point multiplication operations;

[0042] The floating-point adder is used for floating-point addition operations;

[0043] The delay register is used for timing matching.

[0044] Optionally, in the high-speed collaborative processing system for motion control data, when the front-end computing module is located in the FPGA module of the motion control board, the front-end computing module is connected to the data input module and the data cache module respectively. The front-end computing module performs calculations based on the data transmitted by the data input module to obtain front-end computing data, and transmits the front-end computing data to the data cache module. The DSP module reads the front-end computing data through the PCIe interface module, and performs filtering and control algorithm calculations on the front-end computing data to obtain servo control data.

[0045] Optionally, in the aforementioned high-speed collaborative processing system for motion control data, the main control card is a PowerPC board running the VxWorks operating system.

[0046] To achieve the above and other related objectives, the present invention also provides a high-speed collaborative processing method for motion control data, comprising the following steps:

[0047] Initial input data is acquired using a data acquisition card or sensor acquisition card and then converted into fiber optic signals.

[0048] The fiber optic signal is received through the fiber optic interface card, and the fiber optic signal is forwarded to the motion control card through internal synchronization.

[0049] The data transmitted by the fiber optic interface card is processed and calculated to obtain servo control data.

[0050] Before acquiring servo control data, a front-end calculation step is also included to acquire front-end calculation data, and the front-end calculation step is implemented in the FPGA module of the sensor acquisition card, fiber optic interface card or motion control card.

[0051] Optionally, in the high-speed collaborative processing method for motion control data, the front-end calculation step includes:

[0052] The initial input data is linearly corrected using a linear correction submodule.

[0053] The pulsation matrix submodule is used to preprocess the corrected initial input data to obtain the front-end calculation data.

[0054] Optionally, in the high-speed collaborative processing method for motion control data, the initial input data is in the format of an unsigned integer matrix X, and the step of performing linear correction on the initial input data through a linear correction submodule includes:

[0055] x ij Convert to floating-point number x ij ", where x ij Let X be the data in the i-th row and j-th column of matrix X, where i, j = 1, 2, 3;

[0056] System configuration parameter k, calculate floating-point multiplication k×x ij ”;

[0057] System configuration parameter m, calculate floating-point addition kx ij ”+m.

[0058] Optionally, in the high-speed collaborative processing method for motion control data, the step of preprocessing the corrected initial input data through the pulse matrix submodule includes: configuring system parameters A, calculating matrix multiplication Z = Y × A, where Z is the front-end calculation result, and Y = kx ij ”+m.

[0059] Optionally, in the high-speed collaborative processing method for motion control data, the initial input data is in the format of an unsigned integer matrix X, and the step of performing linear correction on the initial input data through a linear correction submodule includes:

[0060] Estimate the quantization error of the integer matrix X to determine the number of bits for the fixed-point number;

[0061] System configuration parameter k', calculate fixed-point multiplication k'×x ij ', where x ij ' is the fixed-point number corresponding to the data in the i-th row and j-th column of matrix X;

[0062] System configuration parameter m', calculates fixed-point addition k'x ij '+m'.

[0063] Optionally, in the high-speed collaborative processing method for motion control data, the step of preprocessing the corrected initial input data through the pulse matrix submodule includes:

[0064] The system is configured with parameter A' to calculate matrix multiplication Z' = Y' × A', where Z' is the result of the front-end calculation and Y' = k' × A'. ij '+m';

[0065] Convert the calculation result Z' into a floating-point number.

[0066] Optionally, in the high-speed collaborative processing method for motion control data, the front-end calculation step includes:

[0067] The system is configured with parameters A, k, and m. The calculation is Z = X × P1 + P2, where X is an unsigned integer matrix of initial input data; P1 = kA; P2 = M × A, where M is a matrix with each element being m; and Z is the front-end calculation result.

[0068] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0069] The high-speed collaborative processing system for motion control data proposed in this invention adopts a collaborative computing approach between FPGA and DSP modules. The FPGA module is responsible for front-end data processing and matrix operations, while the DSP module is responsible for the core motion control algorithm. This reduces the computational load of the DSP module, shortens the computation time, shortens the servo cycle, and improves the computation speed of motion control data, thus meeting the performance requirements of lithography equipment. Attached Figure Description

[0070] Figure 1 This is a schematic diagram of the structure of a high-speed collaborative processing system for motion control data according to an embodiment of the present invention;

[0071] Figure 2 This is a schematic diagram of the structure of a motion control card according to an embodiment of the present invention;

[0072] Figure 3 This is a schematic diagram of a pulsation matrix structure according to an embodiment of the present invention;

[0073] Figure 4 This is a schematic diagram of the PE multiplication and accumulation calculation unit structure according to an embodiment of the present invention;

[0074] Figure 5 This is a data flow diagram of a motion control system according to an embodiment of the present invention. Detailed Implementation

[0075] The high-speed collaborative processing system and method for motion control data proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0076] See Figure 1 This invention provides a high-speed collaborative processing system for motion control data, comprising: a main control card, a motion control card, an optical fiber interface card, a sensor acquisition card, and a chassis (not shown in the figure).

[0077] The chassis is equipped with a backplane, on which the main control card, motion control card, and fiber optic interface card are inserted. The backplane can be a multi-slot backplane; for example, the chassis uses a 21-slot backplane and employs standard 6U boards.

[0078] The backplane is also equipped with a backplane bus, through which the main control card, motion control card, and fiber optic interface card are interconnected. The backplane bus is preferably a VME bus.

[0079] The main control card is a PowerPC (Performance Optimization With Enhanced Enhanced RISC-Performance Computing) board running the VxWorks operating system, responsible for the control and scheduling of the entire system. The main control card connects to the host computer via a TCP / IP network and is used to configure parameters and send commands to the motion control card, fiber optic interface card, data acquisition card, and sensor acquisition card. The main control card communicates with the device boards via a backplane bus, such as the VME bus.

[0080] The sensor acquisition card converts the sensor data into fiber optic signals and transmits these signals to the fiber optic interface card via a communication fiber optic cable. The sensor data is the new input data.

[0081] The sensor acquisition card includes an ADC (Analog-to-Digital Converter) module, a first FPGA module, and an optical fiber communication interface module. The ADC module converts the sensor data into digital signals. The first FPGA module is connected to both the ADC module and the optical fiber communication interface module, serving as a data channel to transmit the digital signals to the optical fiber communication interface. The first FPGA module uses an FPGA chip, such as the EP2C70F896C6. The optical fiber communication interface has an optical module that converts the digital signals into optical fiber signals and transmits these signals to the optical fiber interface card.

[0082] The high-speed collaborative processing system for motion control data may further include a data acquisition card, which is used to acquire servo control data from the previous servo cycle, convert it into an optical fiber signal, and transmit the optical fiber signal to the optical fiber interface card via a communication optical fiber. The servo control data from the previous servo cycle acquired by the data acquisition card or the sensor data acquired by the sensor acquisition card is used as the initial input data.

[0083] When the high-speed collaborative processing system for motion control data includes a data acquisition card, the fiber optic interface card forwards the fiber optic signals from the sensor acquisition card or the data acquisition card to the motion control card via internal synchronization. The number of fiber optic interface cards is preferably 1 to 6. Each fiber optic interface card includes a fiber optic communication module and a second FPGA module. The fiber optic communication module receives the fiber optic signals transmitted by the sensor acquisition card or the data acquisition card. The second FPGA module is connected to the fiber optic communication module and serves as a data channel, sending the data transmitted by the fiber optic communication module to the motion control card. The second FPGA module uses an FPGA chip, such as the EP2C70F896C6 FPGA chip.

[0084] The fiber optic interface card is also equipped with a VME bus control module, which is located on the backplane. Through the VME bus control module, the fiber optic interface card can communicate with other device boards in the chassis. For example, the parameter configuration of the fiber optic interface card issued by the main control card of the chassis can be transmitted to the fiber optic interface card through the VME bus.

[0085] The fiber optic interface card also includes an internal synchronization bus module, which is located on the backplane. This internal synchronization bus module receives data signals from other chassis, such as data signals transmitted from other chassis via an external synchronization bus. The internal synchronization bus module synchronizes the data signals from other chassis within its own chassis to achieve synchronized control of the servo cycles of each chassis.

[0086] The motion control card, as the core computing board, processes and calculates the fiber optic signals forwarded by the fiber optic interface card to obtain servo control data. The preferred number of motion control boards is 1 to 6. (See also...) Figure 2 The motion control card includes a clock module, a third FPGA module, a DSP module, and a program embedding module. The third FPGA module is connected to the backplane bus via a VME interface module.

[0087] The third FPGA module processes the fiber optic signals forwarded by the fiber optic interface card and transmits the processed data to the DSP module. The third FPGA module uses an FPGA chip, such as the XC7K325TFFG900-2. The DSP module uses a DSP chip, such as the TMS320C6678.

[0088] The third FPGA module includes a data input module and a data buffer module. The data input module receives the fiber optic signals forwarded by the fiber optic interface card (i.e., fiber optic signals transmitted from external systems) and converts, synthesizes, and parses these signals. The data input module includes a QSFP optical module, an FPGA serial-to-parallel conversion IP core, and a protocol parsing submodule. The number of optical modules is at least one, preferably two QSFP optical modules. The QSFP optical module converts the fiber optic signals forwarded by the fiber optic interface card into high-speed differential serial signals for processing by the FPGA serial-to-parallel conversion IP core. For example, it converts eight fiber optic signals into eight high-speed differential serial signals. The FPGA serial-to-parallel conversion IP core samples, aligns, and decodes the high-speed differential serial signals, combining them into parallel data. The protocol parsing submodule parses the frame type and specific data of the parallel data according to the communication protocol frame format and sends the parsed data to the data buffer module.

[0089] The data cache module consists of the block random access memory (BRAM) inside the third FPGA module, which maps the register space of the PCIe interface module, allowing the DSP module to read data through the PCIe interface module.

[0090] The DSP module is connected to the third FPGA module. The DSP module acquires the processed data from the third FPGA module via a PCIe interface module. Based on the system configuration, the DSP module performs filtering and control algorithm calculations on the processed data transmitted from the third FPGA module to obtain servo control data. The calculation results are then output to the third FPGA module via an EMIF interface module. The filtering and control algorithm calculations performed by the DSP module on the processed data from the third FPGA module are primarily implemented through its core computing module.

[0091] The third FPGA module and DSP module are also equipped with a PCIe interface module. The PCIe interface module is based on the PCIe communication protocol and is used to transmit the data processed by the third FPGA module to the memory of the DSP module.

[0092] The third FPGA module and DSP module are also equipped with an EMIF interface module. The EMIF interface module is based on the EMIF standard interface and is used by the DSP module to output the calculation results of the core calculation module to the third FPGA module.

[0093] The third FPGA module also includes a VME bus control module, which is based on the VME64 bus standard and instructs the host computer to read the calculation results by triggering a VME interrupt.

[0094] The clock module is connected to the FPGA module and provides a clock signal to the FPGA module. When the various boards on the bus transmit information through the bus, they will use a common clock signal for synchronization.

[0095] The program embedding module is connected to the FPGA module. It is composed of a FLASH chip and is used to store the running programs of the FPGA module and the DSP module. It will be automatically loaded after power-on.

[0096] To improve the speed of motion control data processing, the front-end computation steps, traditionally implemented in the DSP module, are implemented in the FPGA logic. Since the sensor acquisition card, fiber optic interface card, and motion control card all have FPGA modules, the front-end computation module can be located in the FPGA module of the sensor acquisition card, or in the FPGA module of the fiber optic interface card or motion control card, depending on the resource availability of each board's FPGA module. For example, Figure 2 The front-end computing module is located within the FPGA module of the motion control card. This front-end computing module is used for front-end calculations and to acquire front-end calculation data.

[0097] When the front-end computing module is located in the FPGA module of the sensor acquisition card, i.e., the first FPGA module, the first FPGA module, in addition to serving as a data channel, can also perform front-end computing steps to obtain front-end computing data. The high-speed collaborative processing method for motion control data is as follows: the digital signal converted by the ADC analog-to-digital converter module of the sensor acquisition card is transmitted to the first FPGA module, where front-end computing steps are performed to obtain front-end computing data; the front-end computing data is sent to the optical fiber communication interface module, which converts the front-end computing data into an optical fiber signal and transmits it to the optical fiber interface card; the optical fiber interface card forwards the data to the data input module of the motion control card via internal synchronization; the data input module converts, synthesizes, and parses the optical fiber signal containing the front-end computing data, and sends the parsed data to the data cache module, i.e., the front-end computing data is stored in the data cache module; the front-end computing data is then transmitted to the DSP module via the PCIe interface module, where the DSP module performs filtering and control algorithm calculations on the front-end computing data to obtain servo control data.

[0098] When the front-end computing module is located in the FPGA module (i.e., the second FPGA module) of the fiber optic interface card, the second FPGA module, in addition to serving as a data channel, can also perform front-end computing steps to obtain front-end computing data. The high-speed collaborative processing method for motion control data is as follows: the initial input data acquired by the sensor acquisition card or data acquisition card is converted into fiber optic signals and transmitted to the fiber optic communication module of the fiber optic interface card; the fiber optic communication module has an optical module that converts the fiber optic signal with the initial input data into a digital signal and transmits it to the second FPGA module, where front-end computing steps are performed to obtain front-end computing data; the front-end computing data is converted into fiber optic signals through the optical module and forwarded to the data input module of the motion control card via internal synchronization; the data input module converts, synthesizes, and parses the fiber optic signal with the front-end computing data, and sends the parsed data to the data cache module, i.e., the front-end computing data is stored in the data cache module; the front-end computing data is then transmitted to the DSP module through the PCIe interface module, where the DSP module performs filtering and control algorithm calculations on the front-end computing data to obtain servo control data.

[0099] When the front-end computing module is located in the FPGA module (i.e., the third FPGA module) of the motion control card, the high-speed collaborative processing method for motion control data is as follows: the initial input data acquired by the sensor acquisition card or data acquisition card is converted into an optical fiber signal and transmitted to the optical fiber interface card; the optical fiber interface card forwards the optical fiber signal to the data input module of the motion control card through internal synchronization; the data input module converts, synthesizes, and parses the optical fiber signal with the initial input data, and sends the parsed data to the front-end computing module; the front-end computing module performs front-end computing steps to obtain front-end computing data, and transmits the front-end computing data to the data cache module, i.e., the front-end computing data is stored in the data cache module; the front-end computing data is then transmitted to the DSP module through the PCIe interface module; the DSP module performs filtering and control algorithm calculations on the front-end computing data to obtain servo control data.

[0100] The front-end computing module includes a parameter cache register, a data cache register, a linear correction submodule, and a pulsation matrix submodule. The parameter cache register stores the initial input data acquired by the data acquisition card or sensor acquisition card. The linear correction submodule performs linear correction on the initial input data. Since the initial input data may contain errors and deviations, linear correction uniformly corrects the initial input data to avoid affecting subsequent calculation results. The pulsation matrix submodule preprocesses the corrected initial input data to obtain front-end computing data. The data cache register caches the front-end computing data. For example, when the front-end computing module is located in the FPGA module of the motion control card, the front-end computing data buffered in the data cache register is transferred to the data cache module. The pulsation matrix submodule implements the preprocessing part of the corrected initial input data; this part can be computed in parallel to reduce the computational load of the DSP module and shorten the overall servo cycle of the control system.

[0101] See Figure 3 The pulsation matrix submodule consists of several PE multiplication and accumulation calculation units, for example... Figure 3 The pulse matrix submodule described herein consists of 9 PE multiplication and accumulation calculation units, namely PE 11 ~PE 33 , and a 11 ~a 33 b 11 ~b 33 This is the data for the input PE multiplication and accumulation calculation unit.

[0102] See Figure 4 Each PE multiply-accumulate calculation unit includes a floating-point multiplier 10, a floating-point adder 20, and a delay register 30. The floating-point multiplier 10 is used for floating-point multiplication operations; the floating-point adder 20 is used for floating-point addition operations; and the delay register 30 is used for timing matching and alignment. For example, when inputting data a (a_in) and b (b_in), data a can be directly stored in the delay register 30 and output as data a, i.e., a_out; alternatively, it can be multiplied with data b, then added and stored in the delay register 30, and finally output as the calculated data, i.e., c_out. Data b, besides being multiplied with data a, can also be directly stored in the delay register 30 and output as data b, i.e., b_out. The front-end calculation module can complete the front-end calculation steps using a floating-point operator (float_operator) resource.

[0103] The PE multiply-accumulate calculation unit can also have another structure, namely, it includes a fixed-point multiplier, a fixed-point adder, and a delay register. The fixed-point multiplier is used for fixed-point multiplication operations; the fixed-point adder is used for fixed-point addition operations; and the delay register is used for timing matching and alignment. In this case, the front-end calculation module uses DSP48 resources instead of floating-point arithmetic unit resources to complete the front-end calculation steps.

[0104] The front-end computing module can also have another structure, which includes: a parameter cache register, a data cache register, a parameter calculation module, and a systolic matrix submodule. The structures of the parameter cache register, data cache register, and systolic matrix submodule are the same as in the above embodiment. The parameter calculation module calculates configuration parameters for the systolic matrix submodule to perform subsequent calculations to obtain front-end computing data.

[0105] This invention sets the front-end computing module in the FPGA module. Depending on the FPGA resources of each board, it can be set in the FPGA module of the sensor data acquisition card, or in the FPGA module of the motion control card or fiber optic interface card. By adopting a collaborative computing approach between the FPGA module and the DSP module, the FPGA module is responsible for front-end data processing and matrix operations, while the DSP module is responsible for the core motion control algorithm. This effectively improves the computing speed of the motion control module, shortens the servo cycle of the control system, and meets the performance requirements of lithography equipment.

[0106] In addition, the present invention also provides a processing method based on the aforementioned high-speed collaborative processing system for motion control data, comprising the following steps:

[0107] Initial input data is acquired using a data acquisition card or sensor acquisition card and then converted into fiber optic signals.

[0108] The fiber optic signal is received through the fiber optic interface card, and the fiber optic signal is forwarded to the motion control card through internal synchronization.

[0109] The data transmitted by the fiber optic interface card is processed and calculated to obtain servo control data.

[0110] Before acquiring servo control data, a front-end calculation step is also included to acquire front-end calculation data, and the front-end calculation step is implemented in the FPGA module of the sensor acquisition card, fiber optic interface card or motion control card.

[0111] The front-end calculation steps include:

[0112] The initial input data is linearly corrected using a linear correction submodule.

[0113] The pulsation matrix submodule is used to preprocess the corrected initial input data to obtain the front-end calculation results.

[0114] The initial input data is in the format of an unsigned integer matrix X, for example, X is x 11 x 12 x 13 x 21 x 22 x 23 x 31 x 32 x 33 The initial input data is formed into a 3x3 matrix, and the steps of performing linear correction on the initial input data through the linear correction submodule include:

[0115] x ij Convert to floating-point number x ij ", where x ij Let i be the data in the i-th row and j-th column of matrix X, where i and j are preferably 1, 2, 3;

[0116] System configuration parameter k, calculate floating-point multiplication k×x ij "As stated;

[0117] System configuration parameter m, calculate floating-point addition kx ij ”+m.

[0118] That is, the step of performing linear correction on the initial input data through the linear correction submodule requires three sub-steps: fixed-point to floating-point conversion, floating-point multiplication, and floating-point addition.

[0119] The specific steps for preprocessing the corrected initial input data using the pulsation matrix submodule include: configuring system parameters A, calculating matrix multiplication Z = Y × A, where Z is the front-end calculation result, i.e., the front-end calculation data, and Y = kx ij +m. Y is a 3x3 matrix, and parameter A is also a 3x3 matrix. The pulsating matrix module is used to calculate the multiplication of two 3x3 matrices, and the resulting front-end calculation result Z is a 3x3 floating-point matrix.

[0120] Existing technology, through DSP module simulation, shows that the DSP module requires 1800ns to complete the front-end calculation steps. In this embodiment, an FPGA module is used for calculation. Under a 125MHz clock domain, a floating-point arithmetic unit IP with a delay of 3 cycles is used to build the front-end calculation module. The cumulative front-end calculation steps require 9 + 6 x 8 clock cycles. Including additional control delays, the final calculation time is 472ns. Therefore, the high-speed collaborative processing method for motion control data in this embodiment can shorten the calculation time and the servo cycle.

[0121] In another embodiment, the initial input data is in the format of an unsigned integer matrix X, and the step of performing linear correction on the initial input data through the linear correction submodule includes:

[0122] Estimate the quantization error of the integer matrix X to determine the number of bits for the fixed-point number;

[0123] System configuration parameter k', calculate fixed-point multiplication k'×x ij ', where x ij ' is the fixed-point number corresponding to the data in the i-th row and j-th column of matrix X;

[0124] System configuration parameter m', calculates fixed-point addition k'x ij '+m'.

[0125] The quantization error of the integer matrix X is estimated using software simulation to determine the number of bits in the fixed-point number. The software used is, for example, Matlab.

[0126] The specific steps for preprocessing the corrected initial input data using the pulsation matrix submodule include:

[0127] The system is configured with parameter A' to calculate matrix multiplication Z' = Y' × A', where Z' is the result of the front-end calculation and Y' = k' × A'. ij '+m';

[0128] The calculation result Z' is converted into a floating-point number. Here, Y' is a 3x3 matrix, the parameter A' is also a 3x3 matrix, and the final calculation result Z' is a 3x3 fixed-point matrix.

[0129] The previous embodiment employed a floating-point calculation scheme. The unsigned integer real-time data input to the system underwent a fixed-to-floating-point conversion from the outset. All calculations within the FPAG module used a floating-point arithmetic unit, with each floating-point operation requiring at least three clock cycles. In this embodiment, a fixed-point calculation scheme is used. If, based on the algorithm's precision requirements, local fixed-point processing is evaluated, multiplication and addition operations are performed using fixed-point format, and the final result is converted to floating-point, the DSP48 resource can replace the floating-point arithmetic unit, reducing the calculation time to one-third of the previous time.

[0130] In yet another embodiment, the front-end computing step includes:

[0131] The system is configured with parameters A, k, and m. The calculation is Z = X × P1 + P2, where X is an unsigned integer matrix of initial input data; P1 = kA; P2 = M × A, where M is a matrix with each element being m; and Z is the front-end calculation result.

[0132] In the previous implementation of the floating-point calculation scheme, the front-end calculation steps were divided into two steps, represented by matrices: the first step was Y = kX + M, where M is a 3x3 matrix with each element being a parameter m; the second step was Z = Y × A. The first step required three sub-steps: fixed-point to floating-point conversion, floating-point multiplication, and floating-point addition; the second step used a systolic matrix for calculation.

[0133] Combining the two calculation steps yields Z = (kX + M) × A = X × (kA) + (M × A). Since k, m, and A are system configuration parameters, if the system configures these parameters in advance (i.e., using a parameter calculation module to calculate and obtain the configuration parameters; the acquisition of configuration parameters is existing technology and will not be elaborated further), and utilizes some FPGA register cache resources, the two calculation steps can be combined into one step: Z = X × P1 + P2, where P1 = kA and P2 = M × A. Since M is a special 3x3 matrix with each element being m, M × A can actually be reduced to summing the columns of matrix A and multiplying by m to obtain a 1x3 row vector. Each row of the final parameter matrix is ​​this row vector. Because the calculation is not complex and does not depend on real-time data, it can be pre-calculated and cached in registers. During system operation, only fixed-point to floating-point conversion, matrix multiplication, and matrix addition need to be implemented. Compared to previous implementations that used floating-point calculations, this method uses additional register resources to reduce one floating-point multiplication operation during runtime, further improving calculation speed. In this embodiment, all calculations within the FPAG module are performed using a floating-point arithmetic unit.

[0134] Of course, the solution described in this implementation is also applicable to fixed-point number calculations; simply replace floating-point operations with fixed-point operations.

[0135] When the front-end computing module is located in the FPGA module of the motion control board, the uplink and downlink data flow diagram of the high-speed collaborative processing system for motion control data is as follows: Figure 5 As shown.

[0136] The downlink parameter configuration process is as follows: The parameter configuration information in the main control card is transmitted to the DSP module of the motion control board, and the DSP module is set according to the DSP-related parameters in the parameter configuration information; then, the parameter configuration information is transmitted to the FPGA module of the motion control board, i.e., the third FPGA module, and the third FPGA module is set according to the third FPGA module-related parameters in the parameter configuration information; next, the parameter configuration information is transmitted to the fiber optic interface card, and the fiber optic interface card is set according to the relevant parameters in the parameter configuration information, for example, the second FPGA module is set according to the second FPGA module-related parameters in the parameter configuration information; finally, the parameter configuration information is converted into optical signals by the fiber optic interface card and transmitted to the sensor acquisition card, so that the sensor acquisition card is set according to the relevant parameters in the parameter configuration information.

[0137] The process of uplink input data stream includes: sensor data from the sensor acquisition card is converted into optical fiber signals and transmitted to the optical fiber interface card; the optical fiber signals are sent to the FPGA module of the motion control card by the optical fiber interface card through internal conversion; the FPGA module processes the data and sends the processed data to the DSP module of the motion control card; the DSP module obtains servo control data through calculation, and finally the data is fed back to the main control card.

[0138] This invention proposes a high-speed collaborative processing method for motion control data. By employing the logic resources of an FPGA and a DSP for collaborative computing, the FPGA is responsible for front-end data processing and matrix operations, while the DSP is responsible for the core motion control algorithm. This effectively improves the computing speed of the motion control module, reduces the computational burden of the DSP module, and shortens the servo cycle of the control system, thus meeting the performance requirements of lithography equipment.

[0139] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0140] Furthermore, it should be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive or”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way, unless the context clearly indicates otherwise.

Claims

1. A high-speed collaborative processing system for motion control data, characterized in that, include: The main control card, motion control card, fiber optic interface card, sensor acquisition card, and chassis are included. The chassis is provided with a backplane, and the main control card, motion control card and fiber optic interface card are installed on the backplane and interconnected through the backplane bus; the motion control card includes a DSP module; The main control card is responsible for the control and scheduling of the entire system; The sensor acquisition card converts sensor data into optical fiber signals and transmits the optical fiber signals to the optical fiber interface card through a communication optical fiber. The fiber optic interface card forwards the fiber optic signals from the sensor acquisition card to the motion control card via internal synchronization. The sensor acquisition card, fiber optic interface card, and motion control card are all equipped with FPGA modules, and a front-end computing module is set in the FPGA module of the sensor acquisition card, fiber optic interface card, or motion control card. The front-end computing module is used for front-end computing and to acquire front-end computing data. The FPGA module of the motion control card processes the optical fiber signal forwarded by the optical fiber interface card to obtain the front-end calculation data. The DSP module performs filtering and control algorithm calculations on the front-end calculation data according to the system configuration to obtain servo control data.

2. The high-speed collaborative processing system for motion control data as described in claim 1, characterized in that, The system also includes a data acquisition card, which is used to acquire servo control data from the previous servo cycle, convert it into an optical fiber signal, and transmit the optical fiber signal to the optical fiber interface card through a communication optical fiber.

3. The high-speed collaborative processing system for motion control data as described in claim 1, characterized in that, The sensor acquisition card includes an ADC analog-to-digital converter module, a first FPGA module, and an optical fiber communication interface module. The ADC analog-to-digital converter module converts sensor data into digital signals; The first FPGA module is connected to the ADC analog-to-digital conversion module and the optical fiber communication interface module respectively, and it is used as a data channel to transmit the digital signal to the optical fiber communication interface. The fiber optic communication interface converts the digital signal into a fiber optic signal and transmits the fiber optic signal to the fiber optic interface card.

4. The high-speed collaborative processing system for motion control data as described in claim 2, characterized in that, The fiber optic interface card includes a fiber optic communication module and a second FPGA module, wherein... The optical fiber communication module receives the optical fiber signal transmitted by the sensor acquisition card or the data acquisition card; The second FPGA module is connected to the optical fiber communication module and is used as a data channel.

5. The high-speed collaborative processing system for motion control data as described in claim 4, characterized in that, The fiber optic interface card also includes an internal synchronization bus module, which is mounted on the backplane. The internal synchronization bus module receives data signals from other chassis and realizes synchronous control of the servo cycle of each chassis.

6. The high-speed collaborative processing system for motion control data as described in claim 2, characterized in that, The motion control card includes a clock module, a third FPGA module, the DSP module, and a program embedding module, wherein... The third FPGA module is connected to the backplane bus through the VME interface module. The third FPGA module processes the optical fiber signals forwarded by the optical fiber interface card and transmits the processed data to the DSP module. The DSP module is connected to the third FPGA module. The DSP module obtains the data processed by the third FPGA module through the PCIe interface module, and performs filtering and control algorithm calculations on the processed data transmitted by the third FPGA module according to the system configuration to obtain the servo control data. The DSP module also transmits the obtained servo control data to the third FPGA module through the EMIF interface module. The clock module is connected to the third FPGA module and provides a clock signal to the third FPGA module; The program embedding module is connected to the third FPGA module. It is composed of a FLASH chip and is used to store the running programs of the third FPGA module and the DSP module. It will be automatically loaded after power-on.

7. The high-speed collaborative processing system for motion control data as described in claim 6, characterized in that, The third FPGA module includes: a data input module and a data buffer module, wherein, The data input module receives the optical fiber signal forwarded by the optical fiber interface card, and converts, synthesizes, and parses the optical fiber signal; The data cache module consists of the block random access memory inside the third FPGA module, which maps the register space of the PCIe interface module, allowing the DSP module to read data through the PCIe interface module.

8. The high-speed collaborative processing system for motion control data as described in claim 7, characterized in that, The data input module includes a QSFP optical module, an FPGA serial-to-parallel conversion IP core, and a protocol parsing submodule, wherein... The QSFP optical module is used to convert the optical fiber signal forwarded by the optical fiber interface card into a high-speed differential serial signal for processing by the FPGA serial-to-parallel conversion IP core. The FPGA serial-to-parallel conversion IP core is used to sample, align, and decode the high-speed differential serial signal, and combine it into parallel data; The protocol parsing submodule parses the frame type and specific data of the parallel data according to the communication protocol frame format.

9. The high-speed collaborative processing system for motion control data as described in claim 2, characterized in that, The front-end computing module includes a parameter cache register, a data cache register, a linear correction submodule, and a pulsation matrix submodule, wherein... The parameter buffer register is used to store the initial input data acquired by the data acquisition card or sensor acquisition card, and the sensor data or the servo control data of the previous servo cycle is used as the initial input data; The linear correction submodule performs linear correction on the initial input data; The pulsation matrix submodule preprocesses the corrected initial input data to obtain front-end calculation data; The data cache register is used to cache the front-end computation data.

10. The high-speed collaborative processing system for motion control data as described in claim 9, characterized in that, The pulsation matrix submodule consists of several PE multiply-accumulate calculation units, and each PE multiply-accumulate calculation unit includes a floating-point multiplier, a floating-point adder, and a delay register. The floating-point multiplier is used for floating-point multiplication operations; The floating-point adder is used for floating-point addition operations; The delay register is used for timing matching.

11. The high-speed collaborative processing system for motion control data as described in claim 2, characterized in that, When the front-end computing module is set in the FPGA module of the motion control card, the front-end computing module is connected to the data input module and the data cache module respectively. The front-end computing module performs calculations based on the data transmitted by the data input module to obtain front-end computing data, and transmits the front-end computing data to the data cache module. The DSP module reads the front-end computing data through the PCIe interface module, and performs filtering and control algorithm calculations on the front-end computing data to obtain servo control data.

12. The high-speed collaborative processing system for motion control data as described in claim 1, characterized in that, The main control card uses a PowerPC board and runs the Vxworks operating system.

13. A high-speed collaborative processing method for motion control data, characterized in that, Includes the following steps: Initial input data is acquired using a data acquisition card or sensor acquisition card and then converted into fiber optic signals. The fiber optic signal is received through the fiber optic interface card and then forwarded to the motion control card via internal synchronization. The data transmitted by the fiber optic interface card is processed and calculated to obtain servo control data. Before acquiring servo control data, a front-end calculation step is also included to acquire front-end calculation data, and the front-end calculation step is implemented in the FPGA module of the sensor acquisition card, fiber optic interface card or motion control card. The servo control data is obtained in the following manner: The optical fiber signal forwarded by the optical fiber interface card is processed to obtain the front-end calculation data. The DSP module of the motion control card performs filtering and control algorithm calculations on the front-end calculation data according to the system configuration to obtain the servo control data.

14. The high-speed collaborative processing method for motion control data as described in claim 13, characterized in that, The front-end computing steps include: The initial input data is linearly corrected using a linear correction submodule. The pulsation matrix submodule is used to preprocess the corrected initial input data to obtain the front-end calculation data.

15. The high-speed collaborative processing method for motion control data as described in claim 14, characterized in that, The initial input data is in the format of an unsigned integer matrix X. The steps of performing linear correction on the initial input data through the linear correction submodule include: Will Convert to floating-point number ,in The first in matrix X Line number The data in the column, and , =1,2,3; System configuration parameter k, calculates floating-point multiplication. ; System configuration parameter m, calculates floating-point addition. .

16. The high-speed collaborative processing method for motion control data as described in claim 15, characterized in that, The preprocessing steps for the corrected initial input data using the pulsation matrix submodule include: configuring system parameters A, calculating matrix multiplication Z = Y × A, where Z is the front-end calculation result, and Y = ... .

17. The high-speed collaborative processing method for motion control data as described in claim 14, characterized in that, The initial input data is in the format of an unsigned integer matrix X. The steps of performing linear correction on the initial input data through the linear correction submodule include: Estimate the quantization error of the integer matrix X to determine the number of bits for the fixed-point number; System configuration parameters Calculate fixed-point multiplication ,in The first in matrix X Line number The number of fixed points corresponding to the data in the column; System configuration parameters Calculate fixed-point addition .

18. The high-speed collaborative processing method for motion control data as described in claim 17, characterized in that, The steps for preprocessing the corrected initial input data using the pulsation matrix submodule include: System configuration parameters Calculate matrix multiplication ,in For the front-end calculation results, ; The calculation results Convert to floating-point number.

19. The high-speed collaborative processing method for motion control data as described in claim 13, characterized in that, The front-end computing steps include: System configuration parameters A, k, and m, calculation ,in An unsigned integer matrix representing the initial input data; ; M is a matrix with each element being m; Z is the result of the front-end calculation.

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