Selective management of erase operations in memory devices enabled with suspend command

Abstract

The present disclosure relates to selective management of erase operations in memory devices enabled with stall commands. A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including initiating a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of the memory array, tracking a number of stall commands received from a processing device during a time period of a memory line of the memory array ramping toward an erase voltage of the erase pulse, in response to receiving each stall command, stalling the true-erase sub-operation to enable performance of a non-erase memory operation, and in response to the number of stall commands satisfying a threshold criterion, alerting the processing device to terminate sending stall commands until after the true-erase sub-operation is completed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to selective management of erase operations in a memory device that enables a suspend command. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] One aspect of the present disclosure relates to a memory device comprising: a memory array comprising memory cells; and control logic coupled in operation with the memory array, the control logic performing operations comprising: initiating a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of the memory array; tracking a number of suspend commands received from a processing device during a time period in which a memory line of the memory array is ramping up towards an erase voltage of the erase pulse; in response to receiving each suspend command, suspending the true-erase sub-operation to enable performance of a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after the true-erase sub-operation is completed.

[0004] Another aspect of the present disclosure relates to a memory device comprising: a memory array comprising memory cells; and control logic coupled in operation with the memory array, the control logic performing operations comprising: initiating a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of the memory array, wherein memory cells of the one or more sub-blocks begin erasing in response to a memory line of the one or more sub-blocks reaching an erase voltage of the erase pulse; tracking a number of suspend commands received from a processing device during the true-erase sub-operation, including suspend commands received while the memory cells are being erased; in response to receiving each suspend command, suspending the true-erase sub-operation to enable performance of a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands such that the memory cells can be completely erased before other suspend commands are received.

[0005] Yet another aspect of the disclosure relates to a method comprising: initiating, by control logic of a memory device, a true erase sub-operation by applying an erase pulse to one or more sub-blocks of a memory array; tracking, by the control logic, a number of pause commands received from a processing device during a time period in which a memory line of the memory array is ramped toward an erase voltage of the erase pulse; in response to receiving each pause command, pausing the true erase sub-operation to enable performance of a non-erase memory operation; and in response to the number of pause commands satisfying a threshold criterion, alerting the processing device to terminate sending pause commands until after the true erase sub-operation is completed. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings and some embodiments of the disclosure.

[0007] Figure 1A An example computing system including a memory sub-system is shown in accordance with some embodiments.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system in accordance with embodiments.

[0009] Figures 2A-2C is a simplified voltage waveform diagram of an erase pulse in accordance with embodiments. Figure 1B is a schematic diagram of a portion of a memory cell array of the type of memory that can be referenced

[0010] Figure 3 is a simplified voltage waveform diagram of an erase pulse in accordance with embodiments. Figure 1B is a simplified voltage waveform diagram of an erase pulse in accordance with embodiments.

[0011] Figure 4 is a simplified voltage waveform diagram of an erase pulse in accordance with embodiments.

[0012] Figure 5A is a modified flow diagram of an erase operation of a specified group of memory cells of a memory array (e.g., of a block of memory cells) in accordance with some embodiments.

[0013] Figure 5B is a voltage waveform diagram of multiple erase pulses applied to a group of memory cells due to multiple pause commands in accordance with some embodiments.

[0014] Figure 6 is a flow diagram of a method of selectively shortening a duration of a true erase sub-operation of an erase operation based on a number of pause commands received in accordance with at least one embodiment.

[0015] Figure 7is a flowchart of a method of selectively shortening a duration of a true-erase sub-operation of an erase operation based on a number of suspend commands received according to at least one embodiment.

[0016] Figure 8 is a flowchart of a method of selectively shortening a duration of a true-erase sub-operation of an erase operation based on a number of suspend commands received according to at least one embodiment.

[0017] Figure 9 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0018] Embodiments of the disclosure relate to selective management of erase operations in a suspend command-enabled memory device. The memory device can be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in connection with Figure 1A In certain memory devices, such as NAND (or flash) memory devices, memory cells are first erased and then the memory cells are programmed, which is commonly referred to as a program / erase cycle.

[0019] In these memory devices, each erase operation can include a number of sub-operations, such as pre-program, true-erase, true-erase verify, soft-program, soft-program verify, and final erase verify. Each of these sub-operations takes a relatively short amount of time, such as 40-60 microseconds (ps), except that the true-erase sub-operation can take 1 millisecond (ms) or more. The true-erase sub-operation involves applying an actual erase pulse to the memory cells being erased. The true-erase sub-operation takes significantly longer than the other memory operations and longer than the other sub-operations of the erase operation. The duration of the true-erase sub-operation is lengthy because of the significant bias voltage (Vera) of the erase pulse applied to the string of memory cells being erased. After the true-erase sub-operation is complete, it takes a considerable amount of time to ramp up to this bias voltage, and it takes a significant amount of time for the string of memory cells to recover (e.g., discharge).

[0020] For example, in a NAND memory device, read operations are faster than erase operations, and read operations can be prioritized over erase operations. For this reason, when a host system (or a coupled memory subsystem controller, e.g., a processing device) sends a suspend command to temporarily suspend an erase operation to facilitate performing a read or other non-erase memory operation, the erase operation is often repeatedly interrupted. The erase suspend command can be a “forward progress” type, in which the erase operation is not immediately suspended to facilitate completing a current sub-operation before actually suspending the erase operation. Enabling forward progress can be understood as efficient and safe in enabling the memory structure of the memory device to naturally complete a voltage ramp and / or recovery.

[0021] Accordingly, if a suspend command interrupts an erase operation during a true erase sub-operation when using a “forward” suspend command process, a non-erase memory operation (e.g., a read operation) with higher priority still needs to wait a long time, waiting for the true erase sub-operation to complete, before the suspend command can be executed and the memory operation completed. The wait time can exceed 20 times the time to wait for other erase sub-operations. This significant delay can negatively impact quality of service (QoS) performance of the memory device each time a suspend command is received during a true erase sub-operation. For example, the latency repeatedly caused by waiting for a true erase sub-operation to complete when interrupted by a suspend command can significantly degrade memory performance.

[0022] Aspects of the present disclosure address the above and other deficiencies by enabling true erase sub-operations to be suspended prior to completion, enabling non-erase memory operations to be completed in a prioritized manner. However, interrupting a true erase sub-operation can also cause significant stress on the memory structure of the sub-block being erased, particularly on certain memory lines, caused by the repeated ramping of voltage and discharge of the ramped voltage. These memory lines can include, for example, a common source voltage (SRC) line or bit line in two-dimensional (2D) NAND, or a channel region, pillar, or bit line in three-dimensional (3D) NAND. For simplicity, references herein to “memory lines” should be understood to refer to either of an SRC line or bit line in 2D NAND, or to either of a channel, pillar, or bit line in 3D NAND, as the present disclosure is relevant to both 2D and 3D NAND. Further, an erase potential in a memory cell can be caused by a ramped voltage on any of these memory lines.

[0023] According to various embodiments, the potential risk of voltage stress on such memory lines is addressed by the memory device tracking the number of suspend commands received from the processing device (e.g., host system or memory subsystem controller) during a true erase sub-operation. In at least a first embodiment, suspend commands are tracked by the memory device during a period in which the memory line is ramped up to an erase voltage (Vera) of an erase pulse, e.g., by the memory line of one or more sub-blocks (or strings) of memory cells being erased. In at least a second embodiment, suspend commands are tracked by the memory device during the entire true erase sub-operation, including the ramp-up period and one or more erase periods, during which the memory cells lose charge through the memory line as the memory line has reached the erase voltage.

[0024] Furthermore, in these embodiments, in response to the number of suspend commands satisfying a threshold criterion, the memory device alerts the processing device to terminate sending suspend commands until after the true erase sub-operation is completed. In various embodiments, the threshold criterion is set to a particular number of suspend commands above which the memory device determines that the stress on the memory line is excessive, e.g., if exceeded, there is a risk of damaging the memory structure. In the first embodiment, the memory device can additionally reduce the erase voltage necessary for the ramp-up by applying a negative offset corresponding to the number of tracked suspend commands and the duration of time the memory line has been ramped up when the threshold criterion is detected. This reduction in the ramp-up is possible due to the previous ramp-up and corresponding stress of the memory line during the partial erase operation preceding each suspend command, which has already moved many of the memory cells toward the erase potential. In this way, the ramp-up period can be selectively shortened before the erase period of the true erase sub-operation is completed.

[0025] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, a significant improvement in QoS related to memory performance, e.g., reduced latency due to immediate processing of erase suspend commands received during a true erase sub-operation of an erase operation. Furthermore, because the number of suspend commands that can be processed during any given true erase sub-operation is limited, the memory structure associated with the memory cells being erased is protected from excessive stress applied due to discharging / ramping up the high voltage bias when suspending / resuming the true erase sub-operation. Other advantages will be apparent to those of skill in the art of memory operations, including erase operations, associated with the memory device discussed below.

[0026] Figure 1AAn example computing system 100 including a memory sub-system 110 is shown in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such media or memory devices. The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module.

[0027] The memory devices 130 can be non-volatile memory devices. One example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die can include one or more planes. A plane can be grouped into a logical unit (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store binary information of one or more bits and have various logical states related to the number of bits stored. The logical states can be represented as binary values, such as “0” and “1,” or a combination of such values.

[0028] The memory devices 130 can be composed of bits arranged in a two- or three-dimensional grid, also referred to as a memory array. The memory cells are formed onto a silicon die into an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address of each memory cell. The intersection of a bit line and a word line constitutes an address of a memory cell.

[0029] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMCs) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0031] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1A One example of a host system 120 coupled to one memory sub-system 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intermediate components), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

[0032] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0033] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM Express (NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory devices 130) of the memory sub-system 110 when the memory sub-system 110 is coupled with the host system 120 by the physical host interface (e.g., a PCIe bus). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. As an example, Figure 1AThe memory sub-system 110 is shown. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0035] Some examples of non-volatile memory devices (e.g., the memory device 130) include negative-and (NAND) type flash memories and in-place write memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Non-volatile memory cross-point arrays can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-situ write operations, where a non-volatile memory cell can be programmed if it has previously been erased. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit of data per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0037] Although non-volatile memory components are described, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory sub-system controller 115 (or, for simplicity, controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory sub-system controller 115 can be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0040] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the example memory sub-system 110 in Figure 1 is shown to include the memory sub-system controller 115, in another embodiment of the present disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0041] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to effectuate the desired accesses to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access memory devices 130 and convert responses associated with memory devices 130 into information for host system 120.

[0042] Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from memory sub-system controller 115 and decode the addresses to access memory devices 130.

[0043] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory device that includes raw memory devices 130 with control logic on-die (e.g., local media controller 135) and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] In some embodiments, the control logic of the local media controller 135 (e.g., which includes control logic) can implement an erase operation manager 138. The erase operation manager 138 can manage the processing of pause commands that allow for interrupting true erase sub-operations, as described in greater detail below. In some embodiments, the erase operation manager 138 is integrated, in whole or in part, within the memory sub-system controller 115 and / or the host system 120. In various embodiments, the local media controller 135 further includes or is coupled to one or more counters 142 that can be used to track the number of pause commands received from the memory sub-system controller 115 and / or the host system 120 (e.g., from a processing device). In various embodiments, the local media controller 135 further includes or is coupled to one or more timers 144 that can be used to track the duration of each true erase sub-operation prior to pausing in response to a pause command.

[0045] Figure 1B is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory sub-system controller 115 of a memory sub-system (e.g., Figure 1A of the memory sub-system 110) in accordance with an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, etc. The memory sub-system controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device.

[0046] The memory device 130 includes an array of memory cells 104 logically arranged in rows and columns. The memory cells of a logical row are typically connected to the same access line (e.g., word line), while the memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array of memory cells 104 (not shown in Figure 1B are capable of being programmed to one of at least two target data states.

[0047] Row decode circuitry 108 and column decode circuitry 111 are provided to decode address signals. Address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes input / output (I / O) control circuitry 112 for managing the input of commands, addresses and data to the memory device 130 and the output of data and status information from the memory device 130. An address register 114 is in communication with the I / O control circuitry 112, row decode circuitry 108, and column decode circuitry 111 to latch address signals prior to decoding. A command register 124 is in communication with the I / O control circuitry 112 and the local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 internal to the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) to the memory cell array 104. In at least some embodiments, the local media controller 135 includes an erase operation manager 138. The local media controller 135 is in communication with the row decode circuitry 108 and the column decode circuitry 111 to control the row decode circuitry 108 and the column decode circuitry 111 in response to addresses.

[0049] The local media controller 135 is also in communication with a cache register 118 and a data register 121. The cache register 118 latches incoming or outgoing data as instructed by the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a program operation (e.g., a write operation), data can be transferred from the cache register 118 to the data register 121 for transfer to the memory cell array 104; then new data can be latched in the cache register 118 from the I / O control circuitry 112. During a read operation, data can be transferred from the cache register 118 to the I / O control circuitry 112 for output to the memory sub-system controller 115; then new data can be transferred to the cache register 118 from the data register 121. The cache register 118 and / or the data register 121 can form a page buffer of the memory device 130 (e.g., can form at least a portion thereof). The page buffer can further include sensing devices, such as sense amplifiers, for sensing data states of memory cells of the memory cell array 104, e.g., by sensing a state of a data line connected to the memory cells. A status register 122 can be in communication with the I / O control circuitry 112 and the local memory controller 135 to latch status information for output to the memory sub-system controller 115.

[0050] The memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 over a control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be received over the control link 132 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 over a multiplexed input / output (I / O) bus 134 and outputs data to the memory sub-system controller 115 over the I / O bus 134.

[0051] For example, a command can be received at the I / O control circuitry 112 over input / output (I / O) pins [7:0] of the I / O bus 134 and then written into the command register 124. An address can be received at the I / O control circuitry 112 over input / output (I / O) pins [7:0] of the I / O bus 134 and then written into the address register 114. Data can be received at the I / O control circuitry 112 over input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device and then written into the cache register 118. Subsequently, the data can be written into the data register 121 to program the memory cell array 104.

[0052] In an embodiment, the cache register 118 can be omitted and data can be written directly into the data register 121. Data can also be output over input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference can be made to I / O pins, they can include any electrically conductive node that enables electrical connection to the memory device 130 by an external device (e.g., the memory sub-system controller 115), such as a commonly used electrically conductive pad or electrically conductive bump.

[0053] Those skilled in the art will appreciate that additional circuitry and signals can be provided, and Figure 1B The memory device 130 has been simplified for this disclosure. It is recognized that various block components described Figure 1B may not necessarily be separate in different components or component parts of an integrated circuit device. For example, a single component or component part of an integrated circuit device can be adapted to perform the functions of more than one block component described Figure 1B Alternatively, one or more components or component parts of an integrated circuit device can be combined to perform the functions ofFigure 1B Additionally, while specific I / O pins are described to receive and output various signals according to common practice, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) can be used in various embodiments.

[0054] Figures 2A-2C are available for reference Figure 1B A schematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) of the type of memory (e.g., used as part of the memory cell array 104) according to embodiments. The memory array 200A includes access lines (e.g., word lines 2020-202 N ) and data lines (e.g., bit lines 2040-204 M ). The word lines 202 can be connected in a many-to-one relationship to global access lines (e.g., global word lines), which are not shown in FIG. 2. For some embodiments, the memory array 200A can be formed over a semiconductor, which can be conductively doped, for example, to have a certain conductivity type, such as p-type conductivity, for example, to form a p-well, or n-type conductivity, for example, to form an n-well. Figure 2A

[0055] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (e.g., non-volatile memory cells) connected in series, such as one of NAND strings 2060-206 M Each NAND string 206 can be connected (e.g., selectively connected) to a common source (SRC) 216, and can include memory cells 2080-208 N The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field effect transistor), such as one of select gates 2100-210 M (e.g., which can be a source select transistor, commonly referred to as a select gate source), and a select gate 212 (e.g., a field effect transistor), such as one of select gates 2120-212 M (e.g., which can be a drain select transistor, commonly referred to as a select gate drain). The select gates 2100-210 M may be commonly connected to a select line 214, such as a source select line (SGS), and the select gates 2120-212 M ​They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can use a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 may represent several select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0056] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0057] In some embodiments, the drain select line (SGD) and source select line (SGS) are separated and biased to different sources or a common source. Furthermore, the SGD and SGS lines can be one of several layers of a memory subblock, each layer containing the various connections as explained above. Additionally, the common source 216 (SRC) can be a plate, which can be fully or partially segmented, or fully connected.

[0058] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the selected gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0059] Figure 2A The memory array 200A in the memory may be a quasi-two-dimensional memory array and may have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the bit line 204, and the plane containing the bit line 204 can be substantially parallel to the plane containing the common source 216.

[0060] A typical construction of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, etc.) that can determine a data state of the memory cell (e.g., by a change in threshold voltage), and a control gate 236, as shown in Figure 2A Data storage structure 234 can include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. Memory cells 208 have their control gates 236 connected to (and in some cases, formed by) word lines 202.

[0061] A column of memory cells 208 can be selectively connected to one NAND string 206 or a number of NAND strings 206 of a given bit line 204. A row of memory cells 208 can be commonly connected to memory cells 208 of a given word line 202. A row of memory cells 208 can, but need not, include all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically includes every other memory cell 208 commonly connected to a given word line 202. For example, memory cells 208 commonly connected to word line 202 N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), while memory cells 208 commonly connected to word line 202 N and selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cells 208 (e.g., odd memory cells).

[0062] Although bit lines 2043-2045 are not explicitly depicted in Figure 2A , it can be seen from the figure that bit lines 204 of memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204 MThe other groups of memory cells 208 that are collectively connected to a given word line 202 can also define a physical page of memory cells 208. For a particular memory device, all memory cells that are collectively connected to a given word line can be considered a physical page of memory cells. Portions of a physical page of memory cells (which in some embodiments can still be an entire row) that are read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as all memory cells connected to word lines 2020-202 N of a memory array 200B. Unless explicitly distinguished, a reference to a page of memory cells refers to a memory cell in a logical page of memory cells herein. Although examples are discussed in connection with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND array, NOR array, etc.). Figure 2A

[0063] Figure 2B is another schematic diagram of a portion of a memory cell array 200B that can be used in reference to the type of memory described in Figure 1B (e.g., used as part of a memory cell array 104). Figure 2B Similar numbered elements in Figure 2A correspond to the description provided in relation to Figure 2B Additional details are provided that provide one example of a three-dimensional NAND memory array structure. A three-dimensional NAND memory array 200B can incorporate vertical structures that can include semiconductor pillars, where a portion of the pillars can act as channel regions for memory cells of a NAND string 206. The NAND strings 206 can each be selectively connected to a bit line 2040-204 M through a select transistor 210 (e.g., which can be a source select transistor, often referred to as a select gate source) to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. Subsets of NAND strings 206 can be connected to their respective bit lines 204 by biasing select lines 2150-215 K to selectively activate a particular select transistor 212 that is each between a NAND string 206 and a bit line 204. The select transistors 210 can be activated by biasing a select line 214. Each word line 202 can be connected to multiple rows of memory cells of the memory array 200B. Rows of memory cells that are collectively connected to each other by a particular word line 202 can be collectively referred to as a tier.​

[0064] Figure 2C is available for reference Figure 1B Another diagram of a portion of a memory cell array 200C of the type of memory (e.g., used as part of the memory cell array 104). Figure 2C correspond to the description provided with respect to Figure 2A The memory cell array 200C can include strings of memory cells (e.g., NAND strings) 206 connected in series, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as depicted in Figure 2A For example, a portion of the memory cell array 200A can be a portion of the memory cell array 200C.

[0065] Figure 2C depicts grouping of the NAND strings 206 into memory cell blocks 250 (e.g., memory cell blocks 2500-250 L ). The memory cell blocks 250 can be groupings of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as erase blocks. Each memory cell block 250 can represent those NAND strings 206 that are collectively associated with a single select line 215 (e.g., select line 2150). The sources 216 of the memory cell block 2500 can be the same sources as the sources 216 of the memory cell block 250 L . For example, each memory cell block 2500-250 L may be selectively connected to the sources 216 collectively. The access lines 202 and the select lines 214 and 215 of one memory cell block 250 can each not be directly connected to the access lines 202 and the select lines 214 and 215 of any other memory cell block in the memory cell blocks 2500-250 L .

[0066] The bit lines 2040-204 M may be connected (e.g., selectively connected) to a buffer portion 240, which can be part of a page buffer of the memory device 130. The buffer portion 240 can correspond to a memory plane (e.g., a group of memory cell blocks 2500-250 L ). The buffer portion 240 can include sensing circuitry (which can include a sense amplifier) for sensing data values indicated on the respective bit lines 204.

[0067] Figure 3 is available for reference Figure 1BA schematic block diagram of a portion of a memory cell array 300 of the type described. The memory cell array 300 is depicted having four memory planes 350 (e.g., memory planes 3500-3503), each memory plane communicating with a corresponding buffer portion 240, which together form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may communicate with the page buffer 352. Each memory plane 350 is depicted containing L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-2503). L ).

[0068] Continue to refer to Figure 1B , 2A -2C, During a true erase sub-operation, the local media controller 135 (e.g., erase operation manager 138) can utilize the erase pulse (see...) Figure 4 ) makes the common source voltage line (e.g., SRC 216) Figure 2A Ramp up to the erase voltage (Vera), while selecting gate 2100 to 210. M (SGS transistor) is turned on. As discussed, the ramp-up to this high bias erase voltage and subsequent recovery from this voltage ramp require a significant amount of time. Meanwhile, the erase operation manager 138 can select gates 2120 to 212. M ( Figure 2A Disconnects, causing select gates 2120 to 212 to be turned off. M The drain can float, thus allowing the bit line to move from 2040 to 204. M It also floats. Furthermore, the erase operation manager 138 can erase word lines 202 ( Figure 2A Coupled to ground, such as zero volts, or keep word line 202 at a low voltage, such as... Figure 4 As shown. This set of voltage levels at memory array 200A can create voltage levels between memory cells 2080 and 208... N The erase potential, for example, forces electrons through the body of each memory cell to leave the floating bit line 2040 to 204. M In addition.

[0069] In other embodiments, the operation can be reversed, such that the select gates 2100 to 210 are selected. M Disconnecting the gate causes SRC line 216 to float, while the voltage on the bit line ramps up to Vera, simultaneously selecting gates 2120 to 212. MTurning on. As previously mentioned, in 3D NAND, the voltage of one of the channel region, the pillar, or the bit line can also be ramped up such that the attached memory cells are erased. Thus, for simplicity, references herein to a "memory line" should be understood to refer to either of the SRC lines or bit lines in 2D NAND or either of the channel, pillar, or bit line in 3D NAND. In some embodiments, one or more sub-blocks of a physical block of memory cells are erased during the same true erase sub-operation. A memory cell block can generally be understood to include four or more sub-blocks, with each sub-block including a separate string of memory cells.

[0070] Figure 4 is a simplified voltage waveform diagram of an erase pulse 400 according to embodiments. The erase pulse 400 includes two ramp-up periods, a pulse ramp-up period 404 and an overall memory line ramp-up period 408. The pulse ramp-up period 404 is the period of time during which the erase pulse 400 ramps up from a low voltage (e.g., ground or another low voltage) to an erase voltage (Vera) that will provide a high enough voltage bias to the string of memory cells such that the memory cells are erased (as just discussed above). However, the memory line (e.g., one or more of the SRC lines 216 or the bit lines 2040-204 M after the erase pulse 400 reaches the flat top region 414, the memory line is still ramping up during an erase wait period 412 of the flat top region 414, at the end of which the memory line reaches the erase voltage. In some embodiments, at least part of the erase wait period 412 involves the memory line stabilizing at the erase voltage (Vera) so that the memory cells can reach the erase potential required for erasure.

[0071] Thus, the memory line ramp-up period 408 is the collection of the pulse ramp-up period 404 of the erase pulse 400 and the erase wait period 412 of the flat top region 414. Once the memory line ramps up to the erase voltage (Vera), the memory cells attached to the memory line are effectively erased during an erase period 416 of the flat top region 414 of the erase pulse. After the memory cells are erased, the erase pulse 400 transitions to a recovery period 420 during which the memory line and word lines are discharged. A Vpassw waveform can be applied to turn on / off one or more sub-blocks or groups of memory cells being erased.

[0072] As discussed, the selected word lines (e.g., at least some of the word lines 2020-202 N to a low voltage, as Figure 4The word line (WL) waveform 424 is shown. During a true erase sub-operation, some of these word lines can be moved to different biases depending on their position relative to select gates 2100 to 210 along the bit lines or posts (e.g., memory lines). M (SGS transistor) and select gate 2120 to 212 M The location of the (SGD transistors) is important because the memory cells closest to these select gates may need to be biased differently to ensure a complete, non-over-erasing process. In other words, further biasing of some selected word lines may not be necessary, while further biasing of other word lines may be necessary to bring the word lines closer to ground potential. Therefore, WL waveform 424 can represent the voltage bias applied to most, but not necessarily all, of the word lines of one or more sub-blocks being erased.

[0073] Figure 5A This is a modified flowchart of an erase operation 500 of a specified group of memory cells in a memory array (e.g., a block of memory cells) according to some embodiments. Although this disclosure focuses on true erase sub-operations, Figure 5A The context of the overall erase operation and the other sub-operations involved in each erase operation is provided. Each erase operation may include a pre-programming (PPGM) sub-operation 502, which includes, for example, a voltage ramp of a memory cell array containing groups of memory cells being erased, but this is optional. The pre-programming sub-operation 502 may be executed such that at least some groups of memory cells reach a specific uniform voltage, so that the groups of memory cells can then be uniformly erased and verified in subsequent sub-operations. Following the pre-programming sub-operation is a pre-programming (PPGM) recovery sub-operation 506, during which the memory lines and selected word lines (WL) are discharged. According to various embodiments, following the pre-programming sub-operation and recovery is a true erase sub-operation 510, followed by an erase pulse recovery sub-operation 512, both of which are referenced to Figure 4 explain.

[0074] like Figure 5A As shown, the pre-programmed sub-operation 502 and the true erase sub-operation 510 can each be interrupted at various points (e.g., multiple times) during the execution of each sub-operation due to the receipt of a pause command. Solid arrows indicate pause checkpoints, thus showing the moments when the local media controller 135 checks and processes the pause command. Discontinuous arrows indicate recovery points or moments when the erase operation can be resumed after being interrupted by a pause command.

[0075] For example, interrupting programming of memory cells during a pre-programmed sub-operation is generally easier to perform throughout the programming period (as compared to the true erase sub-operation 510) because it is less likely to be disrupted, e.g., it is possible to program subsets of memory cells during different time periods. In addition, the voltage ramp involved in the programming is at a lower voltage, thus, less time is involved in the ramp-up / ramp-down and less stress is applied to the memory structure due to the ramp-up and ramp-down.

[0076] However, interrupting the true erase sub-operation 510 multiple times due to suspend commands is more complex because generally a larger group of memory cells (e.g., a physical block of memory) is erased at a time and a higher voltage bias is involved in the erase pulse applied to the memory line of the NAND memory cells. As discussed, this higher voltage bias applied to the memory line of the memory structure applies stress that can more quickly damage or wear out the memory structure with frequent program / erase cycles. Figure 5B and Figures 6-8 A memory management method that can facilitate frequent interruption of the true erase sub-operation is described in detail to improve the QoS performance of the memory device 130 by avoiding long waits for the true erase sub-operation to complete.

[0077] After the erase pulse resumption 512, the memory operation 500 continues with a series of true erase verify (TEV) sub-operations. A first set of TEV sub-operations 516 is used to verify the erase level of even sub-blocks of one or more memory blocks, including a TEV resume sub-operation. A second set of TEV sub-operations 520 is used to verify the erase level of odd sub-blocks of one or more blocks, including a TEV resume sub-operation. As shown, a suspend command can be processed and the memory operation 500 resumes between each TEV sub-operation.

[0078] Figure 5B is a graph of voltage waveforms of multiple erase pulses applied to a group of memory cells due to multiple suspend commands according to some embodiments. As shown, each erase pulse has been shortened at a flat top region 414 Figure 4 ) indicating that the true erase sub-operation 502 is ending prematurely each time in response to processing a suspend command. Thus, the memory device 130 can track the number of suspend commands received during any given true erase sub-operation. The memory device 130 can further track the entire ramp-up time of each memory line within a cycle of a true erase sub-operation, including after each resume command.

[0079] In some embodiments, the number of suspend commands received reaches a threshold criterion value while the memory line is still ramping up, this embodiment is referred to as a Figure 6 and Figure 8discussed in detail. In other embodiments, the number of received suspend commands is tracked throughout the course of the true-erase sub-operation, and this number reaches a threshold criteria value while the memory cells attached to the memory line are being erased, this embodiment is referred to as Figure 7 discussed in detail.

[0080] Figure 6 is a flow diagram of a method 600 of selectively shortening the duration of a true-erase sub-operation of an erase operation based on a number of received suspend commands, according to at least one embodiment. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the local media controller 135 including the erase operation manager 138. Figures 1A-1B is performed by the local media controller 135 including the erase operation manager 138. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, the processes shown can be performed in a different order, and some processes can be performed concurrently. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0081] At operation 605, a timer is started. More specifically, the processing logic starts a timer 144 that will be used to track the duration of the ramp-up period of the true-erase sub-operation. The timer can be a clock or a counter or other type of timer.

[0082] At operation 610, the memory line is ramped up. More specifically, the processing logic causes the memory line of one or more memory cell sub-blocks to be ramped up toward an erase voltage (Vera) of an erase pulse (see Figure 4 ).

[0083] At operation 615, a suspend command is detected. More specifically, the processing logic determines whether a suspend command is received from a processing device during the time period in which the voltage of the memory line is being ramped up. Depending on the configuration of the memory sub-system 110 in different embodiments, this processing device can be the host system 120 or one of the memory sub-system controllers 115.

[0084] At operation 620, a counter is incremented. More specifically, in response to receiving a suspend command, the processing logic causes a counter 142 to be incremented to track the total number of suspend commands received during the true-erase sub-operation. Each suspend command causes the true-erase sub-operation to be suspended so that a non-erase memory operation (e.g., a read operation or a program operation) can be performed.

[0085] At operation 625, the timer is stopped. More specifically, in response to receiving the suspend command, the processing logic also stops the timer and optionally records the duration tracked by the timer.

[0086] At operation 630, a threshold is checked against the number of suspend commands received. More specifically, the processing logic determines whether the number of suspend commands received satisfies a threshold criterion. In some embodiments, the threshold criterion can include satisfying a particular number of suspend commands being below (or a safe distance from) a number of suspend commands that would cause damage due to voltage stress caused to the memory structure of the one or more sub-blocks.

[0087] At operation 635, an erase recovery is performed. More specifically, in response to not detecting that the threshold criterion is satisfied, the processing logic performs an erase recovery sub-operation in which the memory line and selected word lines are discharged.

[0088] At operation 640, a true erase sub-operation is resumed. More specifically, after performing a non-erase memory operation in which a suspend command was received, the processing logic resumes a true erase sub-operation. In some embodiments, the true erase sub-operation resumes being performed automatically, as in some applications directly after non-erase memory operation processing. In other embodiments, the true erase sub-operation resumes is performed in response to receiving a resume command from the processing device.

[0089] At operation 605, the timer is restarted. More specifically, the processing logic restarts the timer so as to be able to continue tracking the ramp-up period of the erase pulse at the memory line. The duration tracked by the timer can cumulatively grow across true erase sub-operation resumptions, and thus the total voltage ramp-up time can cumulatively grow.

[0090] In various embodiments, continuing to refer to Figure 6 Method 600 continues looping operations 605 through 640 until, at operation 630, the processing logic determines that the number of suspend commands satisfies the threshold criterion.

[0091] At operation 645, the processing device is warned. More specifically, in response to the number of suspend commands satisfying the threshold criterion (at operation 630), the processing logic warns the processing device to terminate sending suspend commands until after the true erase sub-operation is completed. In some embodiments, warning the processing device includes setting a flag for the processing device to detect, such as setting in a reserved metadata region of the memory cell array 104. In other embodiments, warning the processing device includes sending to the processing device the total cumulative number of suspend commands received and / or the total cumulative amount of time tracked by the timer 144.

[0092] At operation 650, an offset is determined. More specifically, processing logic determines a voltage offset to be applied to the memory line that corresponds to the number of tracked pause commands and the duration of the ramp-up period of the true-erase sub-operation. The combination of pause commands and duration can be used to estimate the amount of voltage ramp-up that has been applied by the true-erase sub-operation during different ramp-up periods, including resuming the true-erase sub-operation after each pause command. In some embodiments, in addition or alternatively, determining the voltage offset takes into account the type of multi-level memory cells being erased. For example, a higher or lower erase voltage can be required to erase single-level memory cells, multi-level memory cells, triple-level memory cells, or quad-level memory cells. For example, based on different program / erase cycles or performance targets, single-level, multi-level, and triple-level memory cells can have different Vera than quad-level memory cells.

[0093] At operation 655, the erase voltage is changed. More specifically, processing logic changes the erase voltage (Vera) by the voltage offset, for example so that the time for the memory line to ramp up to the erase potential is also changed. Although this can typically be a decrease in Vera, it is contemplated that Vera can be increased by the voltage offset in some embodiments.

[0094] At operation 660, the method 600 waits for the memory line to ramp up. More specifically, processing logic ramps up the bit lines of the one or more sub-blocks to the changed erase voltage. This decrease in ramp-up is possible due to the previous ramp-up of the memory line and corresponding stress during the partial erase operations before each pause command, which has already moved many of the memory cells toward the erase potential. In this way, the ramp-up period can be selectively shortened before the erase period of the true-erase sub-operation is complete.

[0095] At operation 670, the memory cells are erased. More specifically, processing logic waits for the erase potential to ramp up to the changed erase voltage so that the memory cells attached to the memory line are erased. At operation 680, processing logic performs another erase resume.

[0096] At operation 690, the warning to the processing device is cleared. More specifically, processing logic clears the warning of the terminate pause command that was previously provided (or sent) to the processing device. In this way, the method 600 is complete and can transition to a true-erase verify (TEV) sub-operation (see Figure 5A ).

[0097] In some embodiments, if the processing logic does not detect any more pause commands before the threshold number of pause commands is detected at operation 615 and at operation 630, then at operation 665 the processing logic determines whether the memory line has reached an erase voltage (Vera). If the answer is no at operation 665, then the processing logic loops back to operation 610 and continues to ramp the memory line up. If the answer is yes at operation 665, then the erase potential has been reached, and the method 600 can continue to operation 670 during which the memory cells are erased.

[0098] Figure 7 A flow diagram of a method 700 to selectively shorten a duration of a true-erase sub-operation of an erase operation based on a number of received pause commands according to at least another embodiment. The method 700 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by a local media controller 135 including an erase operation manager 138 of Figures 1A-1B The local media controller 135 including the erase operation manager 138 is executed. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, the processes shown can be performed in a different order, and some processes can be performed concurrently. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0099] At operation 705, a timer is started. More specifically, the processing logic starts a timer 144 that will be used to track a duration of a ramp-up period of a true-erase sub-operation. The timer can be a clock or a counter or other type of timer.

[0100] At operation 710, the memory line is ramped up. More specifically, the processing logic ramps up the memory line of one or more memory cell sub-blocks toward an erase voltage (Vera) of an erase pulse (see Figure 4 ).

[0101] At operation 720, the memory cells begin to erase. More specifically, in response to the memory line reaching the erase voltage (Vera), the processing logic allows the memory cells to begin to erase. This will still happen naturally when the memory line reaches Vera.

[0102] At operation 715, a pause command is detected. More specifically, the processing logic determines whether a pause command is received from the processing device while the voltage of the memory line is being ramped up (operation 710) or the memory cells are being erased (operation 712).

[0103] At operation 720, the counter is incremented. More specifically, in response to receiving a pause command, the processing logic increments the counter 142 to track the total number of pause commands received during the true erase sub-operation. Each pause command causes the true erase sub-operation to pause so that a non-erase memory operation (e.g., a read operation or a program operation) can be performed.

[0104] At operation 725, the timer is stopped. More specifically, in response to receiving a pause command, the processing logic also stops the timer and optionally records the duration tracked by the timer.

[0105] At operation 730, a threshold is checked against the number of pause commands received. More specifically, the processing logic determines whether the number of pause commands received satisfies a threshold criterion. In some embodiments, the threshold criterion can include satisfying a determination that a particular number of pause commands is below (or a safe distance from) a number of pause commands that would cause damage due to voltage stress caused to the memory structure of the one or more sub-blocks.

[0106] At operation 735, an erase recovery is performed. More specifically, in response to not detecting that the threshold criterion is satisfied, the processing logic performs an erase recovery sub-operation in which the memory line and selected word lines are discharged.

[0107] At operation 740, the true erase sub-operation is resumed. More specifically, after performing the non-erase memory operation in which a pause command was received, the processing logic resumes the true erase sub-operation. In some embodiments, the true erase sub-operation resume is performed automatically, as in some applications directly after non-erase memory operation processing. In other embodiments, the true erase sub-operation resume is performed in response to receiving a resume command from the processing device.

[0108] At operation 705, the timer is restarted. More specifically, the processing logic restarts the timer so that it can continue to track the ramp-up period of the erase pulse at the memory line. The duration tracked by the timer can accumulate growth across true erase sub-operation resumptions, and thus the total voltage ramp time can accumulate growth.

[0109] In various embodiments, continuing to refer to Figure 7 The method 700 continues to loop operations 705 through 740 until, at operation 730, the processing logic determines that the number of pause commands satisfies the threshold criterion.

[0110] At operation 750, the processing device is warned. More specifically, in response to the number of suspend commands satisfying the threshold criteria (at operation 730), the processing logic warns the processing device to terminate sending suspend commands so that the memory cells can be fully erased before other suspend commands are received. In some embodiments, warning the processing device includes setting a flag for the processing device to detect, such as setting in a reserved region of the memory cell array 104. In other embodiments, warning the processing device includes sending the processing device the total cumulative number of suspend commands received and / or the total cumulative amount of time tracked by the timer 144.

[0111] At operation 770, the memory cells are fully erased. More specifically, the processing logic waits for the memory cells attached to the memory lines of the one or more sub-blocks to be fully erased. Recall that these memory cells started erasing at operation 712. At operation 780, the processing logic performs another erase recovery.

[0112] At operation 790, the warning to the processing device is cleared. More specifically, the processing logic clears the warning of the termination suspend commands previously provided (or sent) to the processing device. In this way, the method 700 is complete and can transition to a true-erase verification (TEV) sub-operation (see Figure 5A ).

[0113] Figure 8 is a flow diagram of a method 800 to selectively shorten the duration of a true-erase sub-operation of an erase operation based on a number of suspend commands received, according to at least one embodiment. The method 800 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 800 is performed by the local media controller 135 of the memory system 100 including the erase operation manager 138. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed concurrently. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figures 1A-1B

[0114] At operation 810, a true-erase sub-operation is initiated. More specifically, the processing device initiates a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of a memory array.

[0115] ​At operation 820, the received suspend commands are tracked. More specifically, the processing logic tracks a number of suspend commands received from the processing device (e.g., the host system 120 or the memory sub-system controller 115) during the time period of the memory line of the memory array ramping towards the erase voltage of the erase pulse.

[0116] At operation 830, a threshold is checked against the number of received suspend commands. More specifically, the processing logic determines whether the number of received suspend commands satisfies a threshold criterion. In some embodiments, the threshold criterion can include satisfying that a particular number of suspend commands is below (or a safe distance from) a number of suspend commands that would cause a damage due to voltage stress applied to the memory structure of the one or more sub-blocks.

[0117] At operation 840, each suspend command is processed. More specifically, in response to receiving a suspend command and not satisfying the threshold criterion at operation 830, the processing logic suspends the true erase sub-operation and enables execution of a non-erase memory operation.

[0118] At operation 850, the processing device is warned. More specifically, in response to the number of suspend commands satisfying the threshold criterion (at operation 830), the processing logic warns the processing device to terminate sending suspend commands until after the true erase sub-operation is completed, e.g., until after the memory cells are erased. In some embodiments, warning the processing device includes setting a flag for the processing device to detect, e.g., setting in a reserved area of the memory cell array 104. In other embodiments, warning the processing device includes sending to the processing device a total cumulative number of received suspend commands and / or a total cumulative amount of time tracked by the timer 144.

[0119] Figure 9 An example machine is shown including the computer system 900 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 900 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1), or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to the memory sub-system controller 115 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1A Figure 1A Figure 1A In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. ​​

[0120] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0121] Example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0122] Processing device 902 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 902 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 can further include a network interface device 908 to communicate over the network 920.

[0123] The data storage system 918 can include a machine-readable storage medium 924 (also known as a computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The data storage system 918 can further include a local media controller 135, including an erase operation manager 138, which have been discussed previously. The instructions 926 can also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, data storage system 918, and / or main memory 904 can correspond to memory subsystem 110 of Figure 1A

[0124] ​In one embodiment, the instructions 926 include instructions to implement functionality corresponding to a memory sub-system controller 115 of a controller (e.g., Figure 1A The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0125] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. Herein and generally, an algorithm is conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0126] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0127] The disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0128] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear from the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0129] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., non-transitory computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0130] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising memory cells; and control logic coupled in operation with the memory array, the control logic performing operations comprising: initiating a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of the memory array; tracking a number of pause commands received from a processing device during a time period in which a memory line of the memory array is ramped toward an erase voltage of the erase pulse; suspending the true-erase sub-operation in response to each pause command to enable performance of a non-erase memory operation; stopping a timer in response to each pause command, the timer tracking a duration of the time period; and alerting the processing device to terminate sending pause commands until after the true-erase sub-operation is completed in response to the number of pause commands satisfying a threshold criterion, wherein alerting the processing device comprises sending to the processing device a total accumulated number of pause commands received from the processing device and a total accumulated amount of time tracked by the timer.

2. The memory device of claim 1, further comprising a counter coupled with the control logic, the counter to track the number of pause commands received from the processing device.

3. The memory device of claim 1, wherein the operations further comprise, after each pause command is received: performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receiving a recovery command; and ramping the memory line back up to resume the true-erase sub-operation.

4. The memory device of claim 1, wherein the operations further comprise, in response to the number of pause commands satisfying the threshold criterion: determining a voltage offset to the erase voltage to be applied to the erase pulse, the voltage offset corresponding to the number of pause commands tracked and the duration; changing the erase voltage by the voltage offset; and ramping the memory line of the one or more sub-blocks to the changed erase voltage.

5. The memory device of claim 4, wherein determining the voltage offset is further dependent on a type of multi-level memory cells of the memory array.

6. The memory device of claim 1, wherein alerting the processing device comprises setting a flag for the processing device to detect.

7. A memory device comprising: a memory array comprising memory cells; and control logic coupled in operation with the memory array, the control logic performing operations comprising: initiating a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of the memory array, wherein memory cells of the one or more sub-blocks begin erasing in response to a memory line of the one or more sub-blocks reaching an erase voltage of the erase pulse; tracking a number of pause commands received from a processing device during the true-erase sub-operation, including pause commands received while the memory cells are being erased; suspending the true-erase sub-operation in response to each pause command to enable performance of a non-erase memory operation; stopping a timer in response to each pause command, the timer tracking a duration of the true-erase sub-operation; and alerting the processing device to terminate sending pause commands such that the memory cell can be fully erased prior to receiving other pause commands in response to the number of pause commands satisfying a threshold criterion, wherein alerting the processing device includes sending to the processing device a total accumulated number of pause commands received from the processing device and a total accumulated amount of time tracked by the timer.

8. The memory device of claim 7, wherein alerting the processing device includes one of: setting a flag for detection by the processing device; or sending the number of pause commands to the processing device.

9. The memory device of claim 8, wherein the operations further include clearing the flag in response to the memory cell being fully erased.

10. The memory device of claim 7, wherein the operations further include detecting that the number of pause commands satisfies the threshold criterion after the memory cell begins erasing.

11. The memory device of claim 7, wherein the operations further include, after receiving each pause command: performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receiving a recovery command; and ramping the memory line back up to resume the true-erase sub-operation.

12. The memory device of claim 7, further comprising a counter coupled with the control logic, the counter to track the number of pause commands received from the processing device.

13. A method comprising: initiating, by control logic of a memory device, a true-erase sub-operation by applying an erase pulse to one or more sub-blocks of a memory array; tracking, by the control logic, a number of pause commands received from a processing device during a time period in which a memory line of the memory array is ramping toward an erase voltage of the erase pulse; suspending the true-erase sub-operation in response to each pause command to enable performance of a non-erase memory operation; stopping a timer in response to each pause command, the timer tracking a duration of the time period; and alerting the processing device to terminate sending pause commands until after the true-erase sub-operation is complete in response to the number of pause commands satisfying a threshold criterion, wherein alerting the processing device includes sending to the processing device a total accumulated number of pause commands received from the processing device and a total accumulated amount of time tracked by the timer.

14. The method of claim 13, wherein alerting the processing device includes setting a flag for detection by the processing device.

15. The method of claim 13, further comprising, after receiving each pause command: performing an erase recovery of the one or more sub-blocks; restarting the timer in response to receiving a recovery command; and ramping the memory line back up to resume the true-erase sub-operation. ramping up the memory line to recover the true erase sub-operation.

16. The method of claim 13, further comprising, in response to the number of pause commands satisfying the threshold criteria: determining a voltage offset to the erase voltage to be applied to the erase pulse, the voltage offset corresponding to the number and the duration of tracked pause commands; changing the erase voltage by the voltage offset; and ramping up the memory line of the one or more sub-blocks to the changed erase voltage.

17. The method of claim 16, wherein determining the voltage offset is further dependent on a type of multi-level memory cells of the memory array.

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