Flip voltage follower with common gate stage feedback

Abstract

The present application discloses a flip voltage follower with common gate stage feedback, including: a first to an eleventh transistor, and an adjustment resistor. The sources of the first to the third transistors are connected to a power supply terminal, the drain of the first transistor and the gates of the first to the third transistors are connected to a first bias current source; the drains of the second and fourth transistors, the source of the sixth transistor and one end of the adjustment resistor are connected together, the source of the fourth transistor is connected to the drain of the eighth transistor, the gates of the sixth and eighth transistors and the drain and gate of the tenth transistor are connected together; the drains of the third and fifth transistors, the source of the seventh transistor and the other end of the adjustment resistor are connected together, the source of the fifth transistor is connected to the drain of the ninth transistor, the drain of the seventh transistor, the gate of the ninth transistor and the drain and gate of the eleventh transistor are connected together; the gates of the sixth and seventh transistors are connected to a bias voltage. The present application provides more design freedom and robustness for the design of the DC bias point of the circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a toggle voltage follower with common gate stage feedback. Background Art

[0002] The basic structure of a toggle voltage follower is as Figure 1 shown. Transistors M1, M2 and current source Ib form a feedback loop. If it is assumed that the feedback loop is cut off, when the voltage of input node Vi rises, the voltage of output node Vo also rises to keep the IDS of transistor M1 unchanged, which is the basic operation of a simple source follower. Now assume that the feedback loop is open. In addition to the direct signal path from Vi to Vo, there is an additional signal path from Vi to voltage node y and then to Vo. With the help of the feedback loop, the effective transconductance (Gm) and bandwidth of the toggled voltage follower are much larger than those of a simple source follower. There are some problems with the basic toggle voltage follower in mass production and practical applications as follows.

[0003] 1. Voltage node y is directly connected to the gate of M2. To keep M1 and M2 in the saturation region, VGS2 > Vdsat1 + Vdsat2 should be maintained. This means that VGS2 of M2 is large, which means that the W / L ratio of M2 is small and the current density is large. From the perspective of electromigration and aging effects of modern semiconductor technology, this is not beneficial.

[0004] 2. VGS2 is approximately equal to Vdsat2 + Vth2. To keep VGS2 > Vdsat1 + Vdsat2, Vth2 > Vdsat1 needs to be maintained in different PVT environments. In practical applications, Vth2 may fluctuate greatly in different PVT environments, and it is difficult to keep Vth2 > Vdsat1 in all cases. Summary of the Invention

[0005] The purpose of this application is to provide a toggle voltage follower with common gate stage feedback, which provides more design freedom and robustness for the design of the DC bias point of the circuit.

[0006] This application discloses a toggle voltage follower with common gate stage feedback, including the first to eleventh transistors and an adjustment resistor, wherein:

[0007] The sources of the first to third transistors are connected to the power supply terminal, the drain of the first transistor and the gates of the first to third transistors are connected together and connected to the first bias current source;

[0008] The drain of the second transistor, the drain of the fourth transistor, the source of the sixth transistor, and one end of the regulating resistor are connected. The source of the fourth transistor is connected to the drain of the eighth transistor. The drain of the sixth transistor, the gate of the eighth transistor, and the drain and gate of the tenth transistor are connected.

[0009] The drain of the third transistor, the drain of the fifth transistor, the source of the seventh transistor, and the other end of the regulating resistor are connected. The source of the fifth transistor is connected to the drain of the ninth transistor. The drain of the seventh transistor, the gate of the ninth transistor, and the drain and gate of the eleventh transistor are connected. The sources of the eighth to eleventh transistors are connected to the ground terminal.

[0010] Among them, the gates of the sixth transistor and the seventh transistor are connected to a bias voltage. Among them, the gates of the fourth transistor and the fifth transistor respectively receive differential input signals, and the sources of the fourth transistor and the fifth transistor respectively output differential output signals.

[0011] In a preferred example, it further includes: a bias voltage generation circuit, including: the twelfth to fifteenth transistors, a first resistor, and a second bias current source; among them, the gate and drain of the twelfth transistor, and the gate of the thirteenth transistor are connected to the second bias current source. The drain of the thirteenth transistor, the drain and gate of the fourteenth transistor are connected and output the bias voltage. The source of the fourteenth transistor, one end of the first resistor, and the drain and gate of the fifteenth transistor are connected. The other end of the first resistor is connected to the power supply terminal, and the source of the fifteenth transistor is connected to the power supply terminal.

[0012] In a preferred example, the first bias current source and the second bias current source have a suitable current ratio relationship, and the twelfth and thirteenth transistors have a suitable size ratio relationship, so that the current density of the fourteenth transistor is equal to the source-drain current density of the sixth and seventh transistors.

[0013] In a preferred example, the currents of the first bias current source and the second bias current source are 1:1, and the sizes of the twelfth and thirteenth transistors are 1:1.

[0014] In a preferred example, the twelfth transistor and the thirteenth transistor are NMOS transistors or PMOS transistors, and the fourteenth transistor and the fifteenth transistor are PMOS transistors or NMOS transistors.

[0015] In a preferred example, it further includes: a first capacitor, one end of the first capacitor is connected to the source of the fourth transistor and the drain of the eighth transistor, and the other end is connected to the ground terminal.

[0016] In a preferred embodiment, it further includes: a second capacitor, one end of the second capacitor is connected to the source of the fifth transistor and the drain of the ninth transistor, and the other end is connected to the ground terminal.

[0017] In a preferred embodiment, the first to fourth, sixth transistors and the seventh transistor are PMOS transistors or NMOS transistors, and the fourth transistor, the fifth transistor, and the eighth to eleventh transistors are NMOS transistors or PMOS transistors.

[0018] Compared with the basic flip voltage follower, the improved technical effects of the present invention include but are not limited to:

[0019] 1. Enhancing the robustness of the circuit DC operating point design, making it relatively insensitive to process corners and temperature fluctuations;

[0020] 2. Enhancing the freedom of the feedback loop design, enabling the circuit to achieve optimal circuit stability, linearity, bandwidth, and power consumption by adjusting the resistance or current mirror ratio under different bias current sources and power supply voltages;

[0021] 3. The feedback loop of the present invention does not use an AC coupling capacitor structure but adopts a DC coupling means. This avoids introducing a large AC coupling capacitor and saves layout area in actual integrated circuit applications.

[0022] A large number of technical features are recorded in the description of this application, distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are to be listed, the description will be too long. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A + B + C are disclosed, and in another example, features A + B + D + E are disclosed, and features C and D are equivalent technical means that play the same role and only one of them can be used technically and they cannot be used simultaneously, and feature E can be combined with feature C technically. Then, the solution of A + B + C + D should not be regarded as having been recorded because it is technically infeasible, while the solution of A + B + C + E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic structural diagram of a flip voltage follower in the prior art.

[0024] Figure 2It is a schematic structural diagram of a flip voltage follower according to an embodiment of the present application.

[0025] Figure 3 It is a schematic structural diagram of a bias circuit according to an embodiment of the present application.

[0026] Figure 4 It shows the voltages of the drain with and without a clamping device input under the conditions of fast NMOS, fast PMOS, low supply voltage, and different temperatures. Detailed implementation manners

[0027] In the following description, many technical details are presented for the reader to better understand the present application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0028] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0029] The present application discloses a flip voltage follower with a common gate stage feedback. Figure 2 It shows a schematic diagram of a flip voltage follower in an embodiment. The flip voltage follower includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and an adjustment resistor Rt. In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor, and the seventh transistor are PMOS transistors. The fourth transistor, the fifth transistor, and the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors. In another embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor, and the seventh transistor are NMOS transistors. The fourth transistor, the fifth transistor, and the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are PMOS transistors.

[0030] Among them, the sources of the first transistor M1, the second transistor M2, and the third transistor M3 are connected to the power supply terminal Vaa, and the drain of the first transistor M1 and the gates of the first transistor M1, the second transistor M2, and the third transistor M3 are connected and connected to the first bias current source Ibias.

[0031] Further, the drain of the second transistor M2, the drain of the fourth transistor M4, the source of the sixth transistor M6, and one end of the adjustment resistor Rt are connected to a first node S1. The source of the fourth transistor M4 is connected to the drain of the eighth transistor M8. The drain of the sixth transistor M6, the gate of the eighth transistor M8, and the drain and gate of the tenth transistor M10 are connected. Similarly, the drain of the third transistor M3, the drain of the fifth transistor M5, the source of the seventh transistor M7, and the other end of the adjustment resistor Rt are connected to a second node S2. The source of the fifth transistor M5 is connected to the drain of the ninth transistor M9. The drain of the seventh transistor M7, the gate of the ninth transistor M9, and the drain and gate of the eleventh transistor M11 are connected. The sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are connected to the ground terminal. Among them, the gates of the sixth transistor M6 and the seventh transistor M7 are connected to the bias voltage VG. This application enables both the transistor M4 and the transistor M2 to be in the saturation operating region.

[0032] The gates of the fourth transistor M4 and the fifth transistor M5 respectively receive differential input signals, and the sources of the fourth transistor M5 and the fifth transistor M5 respectively output differential output signals. Specifically, the gate of the fourth transistor M4 receives the positive input signal INP, the source of the fourth transistor M4 outputs the positive differential output signal OUTP, the gate of the fifth transistor M5 receives the negative input signal INN, and the source of the fifth transistor M5 outputs the negative differential output signal OUTN.

[0033] In one embodiment, the flip voltage follower further includes: a first capacitor C1, one end of the first capacitor C1 is connected to the source of the fourth transistor M4 and the drain of the eighth transistor M8, and the other end is connected to the ground terminal.

[0034] In a preferred example, the flip voltage follower further includes: a second capacitor C2, one end of the second capacitor C2 is connected to the source of the fifth transistor M5 and the drain of the ninth transistor M9, and the other end is connected to the ground terminal.

[0035] In one embodiment, the flip voltage follower further includes a bias voltage generation circuit. Figure 3The figure shows a schematic diagram of a bias voltage generation circuit in an embodiment. The bias voltage generation circuit includes: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first resistor R1, and a second bias current source Ibias2. In one embodiment, the twelfth transistor M12 and the thirteenth transistor M13 are NMOS transistors, and the fourteenth transistor M14 and the fifteenth transistor M14 are PMOS transistors. In another embodiment, the twelfth transistor M12 and the thirteenth transistor M13 are PMOS transistors, and the fourteenth transistor M14 and the fifteenth transistor M14 are NMOS transistors.

[0036] The gate voltages of transistors M6 and M7 are derived from the bias voltage generation circuit in the preferred example. This bias voltage generation circuit has a process corner and temperature compensation function, making the gate voltage of transistor M6 insensitive to different process corners and operating temperatures, enhancing the robustness of the main circuit.

[0037] Among them, the gate and drain of the twelfth transistor M12, and the gate of the thirteenth transistor M13 are connected to the second bias current source Ibias2. The drain of the thirteenth transistor M13, the drain and gate of the fourteenth transistor M14 are connected and output the bias voltage VG. The source of the fourteenth transistor M14, one end of the first resistor R1, and the drain and gate of the fifteenth transistor M15 are connected. The other end of the first resistor R1 is connected to the power supply terminal Vaa, and the source of the fifteenth transistor M15 is connected to the power supply terminal Vaa.

[0038] In one embodiment, the first bias current source Ibias and the second bias current source Ibias2 have a suitable current ratio relationship, and the twelfth transistor M12 and the thirteenth transistor M13 have a suitable size ratio relationship, such that the current density of the fourteenth transistor M14 is equal to the source-drain current density of the sixth transistor M6 and the seventh transistor M7. For example, the currents of the first bias current source and the second bias current source are 1:1, and the sizes of the twelfth and thirteenth transistors are 1:1, making the source-drain current densities (IDS / W) of the sixth transistor M6, the seventh transistor M7, and the fourteenth transistor M14 equal.

[0039] The feedback loop in the main circuit consists of a regulating resistor Rt, transistors M6, M10, and M8. Among them, transistors M10 and M8 form a current mirror. The loop gain of the feedback loop can be adjusted by adjusting the resistance value of Rt or the mirror ratio of the current mirror formed by M10 / M8 (the W / L ratio of M10 / M8). In general design, the loop gain is adjusted to a relatively large value while ensuring stability, so that the main circuit has the characteristics of high bandwidth, high linearity, and controllable stability.

[0040] To better understand the technical solution of this application, a specific example is given below for illustration. The details listed in this example are mainly for easy understanding and do not limit the protection scope of this application.

[0041] The circuit proposed in this application is a fully differential circuit, as Figure 2 shown. A pair of differential input signals are input to the gate nodes of transistors M4 and M5. The source nodes of transistors M4 and M5 output a pair of differential output signals.

[0042] Compared with the basic flip voltage follower, the flip voltage follower proposed in this application has three additional devices on one side of the differential circuit. These additional devices are transistors M6, M10, and Rt (or M7, M11, and Rt). Transistor M6 is connected as a common gate stage, and the electrically connected transistor M10 serves as its load. Transistors M10 and M8 form a current mirror. The regulating resistor Rt is a variable resistor used to control the loop gain of the feedback loop.

[0043] The two additional transistors in the feedback loop (for example, transistors M6 and M10) provide more freedom for the design of the DC bias point of the circuit. By adjusting the gate voltage (VG) of transistor M6, the drain voltage of transistor M4 can be adjusted accordingly. Adjusting the gate voltage VG has little effect on the VGS of transistor M8.

[0044] In summary, the proposed flip voltage follower breaks the coupling between VGS_M8 and VDS_M8 + VDS_M4 (in the basic flip voltage follower, VGS_M8 = VDS_M8 + VDS_M4).

[0045] In addition, the proposed circuit provides a method for generating the bias voltage VG (the gate bias voltage of transistors M6 and M7). As Figure 3 shown, assuming that the current mirror ratio of transistors M12 and M13 is 1:1, then

[0046] VG = Vaa - R1 * Ibias2 - |VGS_M14|.

[0047] Among them, the current source Ibias2 is proportional to Ibias, and the transistor M14 is a scaled copy of the transistors M6 and M7. In the first-order approximation, VGS_M14 = VGS_M6 = VGS_M7.

[0048] Adjusting Ibias2 * R1 determines the source voltages of the transistors M14, M6, and M7. If Ibias2 * R1 is too small, the source voltages of the transistors M6 and M7 are too high, making the VDS of the transistors M2 and M3 too small and pushing them into the linear region. If Ibias2 * R1 is too large, the source voltages of the transistors M6 and M7 are too low, making the VDS of the transistors M4 and M5 too small and pushing them into the linear region. Therefore, it is crucial to properly design Ibias2 * R1 so that the transistors M2, M3, M4, and M5 all have sufficient voltage headroom simultaneously.

[0049] In the FF_HT_LV (Fast NMOS / Fast PMOS, high temperature, low supply voltage) scenario, Ibias2 * R1 may become larger than its nominal value, making VG lower to squeeze the voltage headroom of the transistors M4 and M5.

[0050] To improve the voltage headroom of the transistors M4 and M5 in the FF_HT_LV (Fast NMOS / Fast PMOS, high temperature, low supply voltage) scenario, this application adds a clamping device (M15) in parallel with R1. In the FF_HT (Fast NMOS / Fast PMOS, high temperature) scenario, the threshold voltage Vth of the clamping device M15 becomes lower, and its IDS becomes larger in this case, pulling up the bias voltage VG to compensate for the effect of R1. In summary, the resistor R1 has a positive temperature coefficient, while the Vth of the transistor M15 has a negative first-order temperature coefficient, and they can compensate each other to obtain a relatively stable bias voltage. Figure 4 Shows the voltage Vd (i.e., the voltages of nodes S1 and S2) of the input pair with and without the clamping device in the FF_LV (Fast NMOS / Fast PMOS, low supply voltage) scenario at different temperatures. It can be seen from the figure that after using the clamping device, the transistor voltages remain stable when the temperature changes.

[0051] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the existence of additional identical elements in the process, method, article or device comprising said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: the act is performed only according to that element, and the act is performed according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds, and more than 2, more than 2 times, more than 2 kinds.

[0052] This specification includes combinations of various embodiments described herein. Separate references to embodiments (such as "one embodiment" or "some embodiments" or "preferred embodiments") are not necessarily to the same embodiment; however, unless indicated to be mutually exclusive or clearly understood by those skilled in the art to be mutually exclusive, these embodiments are not mutually exclusive. It should be noted that the word "or" is used in a non-exclusive sense in this specification unless the context clearly indicates otherwise or requires otherwise.

[0053] All documents mentioned in this specification are considered to be integrally included in the disclosure of this application so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.

Claims

1. A flip voltage follower with common gate stage feedback, characterized in that, it includes the first to the eleventh transistors and an adjustment resistor, where: The sources of the first to the third transistors are connected to the power supply terminal, the drain of the first transistor and the gates of the first to the third transistors are connected and connected to a first bias current source; The drain of the second transistor, the drain of the fourth transistor, the source of the sixth transistor and one end of the adjustment resistor are connected, the source of the fourth transistor is connected to the drain of the eighth transistor, and the drain of the sixth transistor, the gate of the eighth transistor and the drain and gate of the tenth transistor are connected; The drain of the third transistor, the drain of the fifth transistor, the source of the seventh transistor and the other end of the adjustment resistor are connected, the source of the fifth transistor is connected to the drain of the ninth transistor, and the drain of the seventh transistor, the gate of the ninth transistor and the drain and gate of the eleventh transistor are connected, and the sources of the eighth to the eleventh transistors are connected to the ground terminal; Wherein, the gates of the sixth transistor and the seventh transistor are connected to a bias voltage. Among them, the gates of the fourth transistor and the fifth transistor respectively receive differential input signals, and the sources of the fourth transistor and the fifth transistor respectively output differential output signals.

2. The flip voltage follower according to claim 1, characterized in that, it further includes: A bias voltage generation circuit, including: the twelfth to the fifteenth transistors, a first resistor and a second bias current source; wherein, the gate and drain of the twelfth transistor and the gate of the thirteenth transistor are connected to the second bias current source, the drain of the thirteenth transistor, the drain and gate of the fourteenth transistor are connected and output the bias voltage, the source of the fourteenth transistor, one end of the first resistor and the drain and gate of the fifteenth transistor are connected, the other end of the first resistor is connected to the power supply terminal, and the source of the fifteenth transistor is connected to the power supply terminal.

3. The flip voltage follower according to claim 2, characterized in that, The first bias current source and the second bias current source have a suitable current ratio relationship, and the twelfth and thirteenth transistors have a suitable size ratio relationship, so that the current density of the fourteenth transistor is equal to the source-drain current density of the sixth and seventh transistors.

4. The flip voltage follower according to claim 3, characterized in that, The currents of the first bias current source and the second bias current source are 1:1, and the sizes of the twelfth and thirteenth transistors are 1:

1.

5. The flip voltage follower according to claim 2, characterized in that, The twelfth transistor and the thirteenth transistor are NMOS transistors or PMOS transistors, and the fourteenth transistor and the fifteenth transistor are PMOS transistors or NMOS transistors.

6. The flip voltage follower according to claim 1, characterized in that, The first to the fourth, sixth transistors and the seventh transistor are PMOS transistors or NMOS transistors, and the fourth transistor, the fifth transistor, and the eighth to the eleventh transistors are NMOS transistors or PMOS transistors.

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