A bias circuit with high and low voltage connection and protection functions

Abstract

The present invention discloses a bias circuit with high-voltage and low-voltage connection and protection functions, which includes a high-voltage bias module, a high-low voltage connection module, and a low-voltage bias module, realizing multiple bias levels in the high-voltage region and the low-voltage region while taking into account circuit protection; the bias circuit of the present invention can provide the connection between the high-voltage region and the low-voltage region and provide a protection function to ensure the normal operation of the chip in a high-voltage environment; moreover, the MOS transistor used for protection in the present invention is also used to define the branch current, and the branch current in the low-voltage region and the high-voltage region is defined simultaneously, saving chip area and manufacturing cost; and the structure and concept of the present invention also have certain reference significance for the high-low voltage connection of discrete devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuits, and particularly relates to a bias circuit with high-low voltage connection and protection functions. Background Art

[0002] In industrial applications, the input power supply of integrated circuits is often higher than the breakdown voltage of conventional devices, and there may be multiple power rails. If high-voltage-resistant devices are used under all power rails to ensure chip safety, it will occupy a large chip area, and the chip performance may be poor. Therefore, it should be attempted to separate the high-voltage area from the low-voltage area and complete the connection between the high-voltage and low-voltage parts. Since there are both high-voltage areas and low-voltage areas in the chip, attention should be paid to the circuit protection function.

[0003] Most of the existing technologies achieve high-low voltage separation by inserting high-voltage-resistant devices in the branches to achieve high breakdown voltage of the traditional structure. In order to achieve multiple bias levels in the high-voltage area and the low-voltage area and take into account circuit protection at the same time, it is often necessary to increase the chip area and improve the circuit power consumption, resulting in cost waste. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a bias circuit with high-low voltage connection and protection functions, which can reduce the chip area, save chip cost, and have a protection function.

[0005] The present invention adopts the following technical solutions:

[0006] A bias circuit with high-low voltage connection and protection functions,

[0007] including a high-voltage bias module, a high-low voltage connection module, and a low-voltage bias module; the high-voltage bias module is respectively connected to a high-voltage power rail VH and a low-voltage power rail VL; the low-voltage bias module is connected to the low-voltage power rail VL; one end of the high-low voltage connection module is connected to the connection node between the high-voltage bias module and the low-voltage bias module, and the other end of the high-low voltage connection module is connected to the low-voltage bias module. The control signal of the bias circuit is connected to the bias circuit through the high-low voltage connection module; the high-voltage power rail VH and the low-voltage power rail VL provide preset various bias voltages to the outside through the bias circuit. The high-voltage bias module is used to provide a preset high-voltage bias voltage to the outside, and the low-voltage bias module is used to provide preset various low-voltage bias voltages to the outside.

[0008] Preferably, the high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1. The source of the high-voltage bias transistor MP1 is connected to the high-voltage power supply rail VH. The gate and the drain of the high-voltage bias transistor MP1 are connected and connected to the drain of the main current-defining transistor DN1. The gate of the main current-defining transistor DN1 is connected to the low-voltage power supply rail VL. The source of the main current-defining transistor DN1 is connected to one end of the high-low voltage connection module and the low-voltage bias module. The gate of the high-voltage bias transistor MP1 provides a preset high-voltage bias voltage VBH externally.

[0009] Preferably, the high-low voltage connection module includes a connection transistor DN3, a connection transistor DN4, and a current-defining resistor R0. The gates of the connection transistor DN3 and the connection transistor DN4 are connected to the control signal of the bias circuit. The sources of the connection transistor DN3 and the connection transistor DN4 are connected, and this connection point is grounded through the current-defining resistor R0. The drain of the connection transistor DN3 is connected to the connection node between the high-voltage bias module and the low-voltage bias module. The drain of the connection transistor DN4 is connected to the low-voltage bias module.

[0010] Preferably, the low-voltage bias module includes a first current mirror unit and a second current mirror unit. One end of the first current mirror unit is connected to the low-voltage power supply rail VL. The other end of the first current mirror unit is grounded through the second current mirror unit. And the first current mirror unit is connected to the second current mirror unit through the high-low voltage connection module.

[0011] Preferably, the first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3. The second current mirror unit includes a low-voltage bias transistor DN2 and a low-voltage bias transistor DN5. The sources of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are connected to the low-voltage power supply rail VL. The drain and the gate of the low-voltage bias transistor MP2 are connected, and this connection point is respectively connected to the other end of the high-low voltage connection module and the gate of the low-voltage bias transistor MP3. The drain of the low-voltage bias transistor MP3 is connected to the drain of the low-voltage bias transistor DN5. The sources of the low-voltage bias transistor DN2 and the low-voltage bias transistor DN5 are grounded. The drain of the low-voltage bias transistor DN2 is connected to one end of the high-low voltage connection module. The gates of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 provide a preset low-voltage bias voltage VBP externally. The gates of the low-voltage bias transistor DN5 and the low-voltage bias transistor DN2 provide a preset low-voltage bias voltage VBN externally.

[0012] Preferably, the first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3, and the second current mirror unit includes a low-voltage bias transistor DN2, a low-voltage bias transistor MN1, a low-voltage bias transistor MN2, a low-voltage bias transistor DN5, and a resistor R1. The sources of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are connected to the low-voltage power supply rail VL. The drain and the gate of the low-voltage bias transistor MP2 are connected, and this connection point is respectively connected to the other end of the high-low voltage connection module and the gate of the low-voltage bias transistor MP3. The drain of the low-voltage bias transistor MP3 is connected to the drain of the low-voltage bias transistor DN5 through the resistor R1. The source of the low-voltage bias transistor DN5 is connected to the drain of the low-voltage bias transistor MN2. The sources of the low-voltage bias transistor MN2 and the low-voltage bias transistor MN1 are grounded. The drain of the low-voltage bias transistor MN1 is connected to the source of the low-voltage bias transistor DN2. The drain of the low-voltage bias transistor DN2 is connected to one end of the high-low voltage connection module. The gates of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 provide a preset low-voltage bias voltage VBP externally. The gates of the low-voltage bias transistor DN5, the drain of the low-voltage bias transistor MP3, and the gate of the low-voltage bias transistor DN2 provide a preset cascode bias voltage VN externally. The drains of the low-voltage bias transistor DN5, the gate of the low-voltage bias transistor MN1, and the gate of the low-voltage bias transistor MN2 provide a preset low-voltage bias voltage VBN externally.

[0013] Preferably, the sources of the current definition main transistor DN1, the connection transistor DN3, the connection transistor DN4, and the gate voltage of the low-voltage bias transistor MP2 are equal.

[0014] Preferably, the width-to-length ratios of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are equal; the width-to-length ratios of the low-voltage bias transistor DN2 and the low-voltage bias transistor DN5 are equal; the width-to-length ratios of the low-voltage bias transistor MN1 and the low-voltage bias transistor MN2 are equal.

[0015] Preferably, based on the operating voltage of the high-voltage power supply rail VH, a preset number of PMOS transistors with source-drain connected in series are connected in series between the high-voltage power supply rail VH and the high-voltage bias voltage.

[0016] Preferably, the current definition main transistor DN1, the low-voltage bias transistor DN2, the connection transistor DN3, the connection transistor DN4, and the low-voltage bias transistor DN5 adopt N-type high-voltage-resistant LDMOS transistors, the high-voltage bias transistor MP1, the low-voltage bias transistor MP2, and the low-voltage bias transistor MP3 adopt PMOS transistors, and the low-voltage bias transistor MN1 and the low-voltage bias transistor MN2 adopt NMOS transistors.

[0017] The beneficial effects of the present invention are as follows: The present invention provides a bias circuit with high-voltage and low-voltage connection and protection functions. The bias circuit of the present invention can provide the connection between the high-voltage area and the low-voltage area and provide protection functions to ensure the normal operation of the chip in a high-voltage environment. Moreover, the MOS transistor used for protection in the present invention is also used to define the branch current, and the branch current definitions of the low-voltage area and the high-voltage area are completed simultaneously, saving chip area and manufacturing cost. And the structure and concept of the present invention also have certain reference significance for the high-voltage and low-voltage connection of discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a structural block diagram of the bias circuit with high-voltage and low-voltage connection and protection functions according to an embodiment of the present invention;

[0019] Figure 2 is the bias circuit diagram of the high-voltage and low-voltage connection and protection functions in Embodiment 1 of the present invention;

[0020] Figure 3 is the bias circuit diagram of the high-voltage and low-voltage connection and protection functions in Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present invention will be further described below with reference to the accompanying drawings. The following embodiments can enable those skilled in the art to understand the present invention more comprehensively, but do not limit the present invention in any way.

[0022] Embodiment 1

[0023] A bias circuit with high-voltage and low-voltage connection and protection functions, as Figure 1 shown, includes a high-voltage bias module, a high-low voltage connection module, and a low-voltage bias module; the high-voltage bias module is respectively connected to the high-voltage power supply rail VH and the low-voltage power supply rail VL; the low-voltage bias module is connected to the low-voltage power supply rail VL; one end of the high-low voltage connection module is connected to the connection node between the high-voltage bias module and the low-voltage bias module, and the other end of the high-low voltage connection module is connected to the low-voltage bias module. The control signal of the bias circuit is connected to the bias circuit through the high-low voltage connection module, and the control signal VCtrl can be controlled by the target integrated circuit switch or system enable signal accessed by the bias circuit; the high-voltage power supply rail VH and the low-voltage power supply rail VL provide preset various bias voltages to the outside through the bias circuit, that is, provide a preset high-voltage bias voltage and preset various low-voltage bias voltages to the target integrated circuit accessed by the bias circuit. The high-voltage bias module is used to provide a preset high-voltage bias voltage to the outside, and the low-voltage bias module is used to provide preset various low-voltage bias voltages to the outside.

[0024] As Figure 2As shown, the high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1; the high-low voltage connection module includes a connection transistor DN3, a connection transistor DN4, and a current-defining resistor R0; the low-voltage bias module includes a first current mirror unit and a second current mirror unit. The first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3, and the second current mirror unit includes a low-voltage bias transistor DN2 and a low-voltage bias transistor DN5.

[0025] The main current-defining transistor DN1, the low-voltage bias transistor DN2, the connection transistor DN3, the connection transistor DN4, and the low-voltage bias transistor DN5 are made of N-type high-voltage-resistant LDMOS transistors. The high-voltage bias transistor MP1, the low-voltage bias transistor MP2, and the low-voltage bias transistor MP3 are made of PMOS transistors, and ordinary PMOS transistors can be used. And the main current-defining transistor DN1, the low-voltage bias transistor DN2, the connection transistor DN3, the connection transistor DN4, and the low-voltage bias transistor DN5 can be replaced with high-voltage-resistant MOS transistors in various different processes. The current-defining resistor R0 is an ordinary resistor.

[0026] The high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1. The source of the high-voltage bias transistor MP1 is connected to the high-voltage power supply rail VH. The gate of the high-voltage bias transistor MP1 is connected to its drain and then connected to the drain of the main current-defining transistor DN1. The gate of the main current-defining transistor DN1 is connected to the low-voltage power supply rail VL. The source of the main current-defining transistor DN1 is connected to one end of the high-low voltage connection module and the low-voltage bias module, that is, the source of the main current-defining transistor DN1 is respectively connected to the drain of the low-voltage bias transistor DN2 in the low-voltage bias module and the drain of the connection transistor DN3 in the high-low voltage connection module. The gate of the high-voltage bias transistor MP1 provides a preset high-voltage bias voltage VBH externally.

[0027] The high-low voltage connection module includes a connection transistor DN3, a connection transistor DN4, and a current-defining resistor R0. The gates of the connection transistor DN3 and the connection transistor DN4 are connected to the control signal of the bias circuit. The sources of the connection transistor DN3 and the connection transistor DN4 are connected, and this connection point is grounded through the current-defining resistor R0. The drain of the connection transistor DN3 is connected to the connection node between the high-voltage bias module and the low-voltage bias module, that is, the drain of the connection transistor DN3 is respectively connected to the source of the main current-defining transistor DN1 in the high-voltage bias module and the drain of the low-voltage bias transistor DN2 in the low-voltage bias module, and the source of the main current-defining transistor DN1 in the high-voltage bias module and the drain of the low-voltage bias transistor DN2 in the low-voltage bias module are connected; the drain of the connection transistor DN4 is connected to the low-voltage bias module, that is, the drain of the connection transistor DN4 is connected to the drain of the low-voltage bias transistor MP2 in the low-voltage bias module.

[0028] The low-voltage biasing module includes a first current mirror unit and a second current mirror unit. One end of the first current mirror unit is connected to the low-voltage power supply rail VL, and the other end of the first current mirror unit is grounded through the second current mirror unit. A high-low voltage connection module is connected between the first current mirror unit and the second current mirror unit.

[0029] Specifically, the first current mirror unit includes a low-voltage biasing transistor MP2 and a low-voltage biasing transistor MP3, and the second current mirror unit includes a low-voltage biasing transistor DN2 and a low-voltage biasing transistor DN5. The sources of the low-voltage biasing transistor MP2 and the low-voltage biasing transistor MP3 are connected to the low-voltage power supply rail VL. The drain and gate of the low-voltage biasing transistor MP2 are connected, and this connection point is respectively connected to the other end of the high-low voltage connection module and the gate of the low-voltage biasing transistor MP3, that is, the connection point where the drain and gate of the low-voltage biasing transistor MP2 are connected is respectively connected to the drain of the connection transistor DN4 in the high-low voltage connection module and the gate of the low-voltage biasing transistor MP3. The drain of the low-voltage biasing transistor MP3 is connected to the drain of the low-voltage biasing transistor DN5. The sources of the low-voltage biasing transistor DN2 and the low-voltage biasing transistor DN5 are grounded. The drain of the low-voltage biasing transistor DN2 is connected to one end of the high-low voltage connection module, that is, the drain of the low-voltage biasing transistor DN2 is connected to the drain of the connection transistor DN3 in the high-low voltage connection module. The gates of the low-voltage biasing transistor MP2 and the low-voltage biasing transistor MP3 provide a preset low-voltage biasing voltage VBP externally, and the gates of the low-voltage biasing transistor DN5 and the low-voltage biasing transistor DN2 provide a preset low-voltage biasing voltage VBN externally.

[0030] The connection transistor DN3 and the connection transistor DN4 are switching transistors, so that the source of the current definition main transistor DN1, the sources of the connection transistor DN3, the connection transistor DN4, and the gate voltage of the low-voltage biasing transistor MP2 are approximately equal. The width-to-length ratios of the low-voltage biasing transistor MP2 and the low-voltage biasing transistor MP3 are equal; and the width-to-length ratios of the low-voltage biasing transistor DN2 and the low-voltage biasing transistor DN5 are equal.

[0031] Based on the operating voltage of the high-voltage power supply rail VH, that is, according to the operating range of the input voltage, a preset number of PMOS transistors with their sources and drains connected in series are connected between the high-voltage power supply rail VH and the high-voltage biasing voltage to protect the high-voltage biasing transistor MP1.

[0032] Based on the above circuit, the working principle of the biasing circuit in this solution is as follows:

[0033] When VCtrl rises, the connection transistor DN3 and the connection transistor DN4 play the role of approximate enable transistors, the circuit starts. At the same time, the connection transistor DN3 and the connection transistor DN4 prevent the potential at the upper end of the resistor R0 from being too high, and prevent the possible high voltage at the source of the current definition main transistor DN1, playing a protective role and completing the connection between the high-voltage area and the low-voltage area.

[0034] Since the low-voltage bias transistors MP2 and MP3 form a current mirror, and the low-voltage bias transistors DN2 and DN5 form a current mirror. Therefore, the current flowing through the low-voltage bias transistor MP2 is equal to the current flowing through the low-voltage bias transistor DN2. At this time, the current flowing through the current definition main transistor DN1 is equal to the current flowing through the current definition resistor R0. The current in the branch where the current definition main transistor DN1 is located is defined by the current definition main transistor DN1 and the current definition resistor R0, and there is:

[0035]

[0036]

[0037] In the formula, is the current flowing through the current definition main transistor DN1, is the carrier mobility of the current definition main transistor DN1, is the gate oxide capacitance of the current definition main transistor DN1, is the gate width of the current definition main transistor DN1, is the gate length of the current definition main transistor DN1, is the threshold voltage of the current definition main transistor DN1; represents the intrinsic conductivity factor of the MOS transistor DN1; represents the voltage value of the low-voltage power supply rail.

[0038] At this time, the current definition main transistor DN1 not only plays the role of current definition but also undertakes the function of high-low voltage isolation. The current is also the high-voltage region bias current, and a preset high-voltage bias voltage VBH is output via the high-voltage bias transistor MP1.

[0039] At this time, the source voltage of the current definition main transistor DN1 is determined, that is, the gate voltage of the low-voltage bias transistor MP2 is determined, and a preset low-voltage bias voltage VBP is output, and is converted into low-voltage region bias voltages VBP and VBN through the low-voltage bias transistors MP3 and DN5.

[0040] After VCtrl is powered on, the circuit starts. According to the magnitude of the low-voltage voltage source, the aspect ratio of the N-type LDMOS transistor DN1 and the magnitude of the resistor R0 can be designed based on the above formula to complete the definition of the high-voltage region bias current. This current can be transmitted through the current mirror starting point formed by the PMOS transistor MP1 to other circuit modules operating in the high-voltage region for use. MP1, as a diode-connected MOS transistor, can be used as a new current mirror starting point. By adjusting the aspect ratio of the PMOS transistor MP2, the magnitude of the low-voltage region bias current can be determined and transmitted through the current mirror formed by the low-voltage bias transistor DN5 to other modules operating in the low-voltage region for use.

[0041] Embodiment 2

[0042] A bias circuit with high and low voltage connection and protection functions, as Figure 1 shown, including a high-voltage bias module, a high-low voltage connection module and a low-voltage bias module; the high-voltage bias module is respectively connected to the high-voltage power supply rail VH and the low-voltage power supply rail VL; the low-voltage bias module is connected to the low-voltage power supply rail VL; one end of the high-low voltage connection module is connected to the connection node between the high-voltage bias module and the low-voltage bias module, and the other end of the high-low voltage connection module is connected to the low-voltage bias module. The control signal of the bias circuit is connected to the bias circuit through the high-low voltage connection module, and the control signal VCtrl can be controlled by the target integrated circuit switch or system enable signal accessed by the bias circuit; the high-voltage power supply rail VH and the low-voltage power supply rail VL provide various preset bias voltages externally through the bias circuit, that is, provide a preset high-voltage bias voltage and various preset low-voltage bias voltages for the target integrated circuit accessed by the bias circuit. The high-voltage bias module is used to provide a preset high-voltage bias voltage externally, and the low-voltage bias module is used to provide various preset low-voltage bias voltages externally.

[0043] As Figure 2 shown, the high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1; the high-low voltage connection module includes connection transistors DN3, DN4 and a current-defining resistor R0; the low-voltage bias module includes a first current mirror unit and a second current mirror unit. The first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3, and the second current mirror unit includes a low-voltage bias transistor DN2, a low-voltage bias transistor MN1, a low-voltage bias transistor MN2 and a low-voltage bias transistor DN5, and a resistor R1.

[0044] The main current-defining transistor DN1, the low-voltage bias transistor DN2, the connection transistors DN3, DN4, and the low-voltage bias transistor DN5 adopt N-type high-voltage-resistant LDMOS transistors. The high-voltage bias transistor MP1, the low-voltage bias transistors MP2, and MP3 adopt PMOS transistors, and ordinary PMOS transistors can be used. And the main current-defining transistor DN1, the low-voltage bias transistor DN2, the connection transistors DN3, DN4, and the low-voltage bias transistor DN5 can be replaced by high-voltage-resistant MOS transistors in various different processes. The low-voltage bias transistors MN1 and MN2 adopt NMOS transistors. The current-defining resistor R0 and the resistor R1 are ordinary resistors.

[0045] The high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1. The source of the high-voltage bias transistor MP1 is connected to the high-voltage power supply rail VH. The gate and drain of the high-voltage bias transistor MP1 are connected and connected to the drain of the main current-defining transistor DN1. The gate of the main current-defining transistor DN1 is connected to the low-voltage power supply rail VL. The source of the main current-defining transistor DN1 is connected to one end of the high-low voltage connection module and the low-voltage bias module, that is, the source of the main current-defining transistor DN1 is respectively connected to the drain of the low-voltage bias transistor DN2 in the low-voltage bias module and the drain of the connection transistor DN3 in the high-low voltage connection module. The gate of the high-voltage bias transistor MP1 provides a preset high-voltage bias voltage VBH externally.

[0046] The high-low voltage connection module includes a connection transistor DN3, a connection transistor DN4, and a current-defining resistor R0. The gates of the connection transistor DN3 and the connection transistor DN4 are connected to the control signal of the bias circuit. The sources of the connection transistor DN3 and the connection transistor DN4 are connected, and this connection point is grounded through the current-defining resistor R0. The drain of the connection transistor DN3 is connected to the connection node between the high-voltage bias module and the low-voltage bias module, that is, the drain of the connection transistor DN3 is respectively connected to the source of the main current-defining transistor DN1 in the high-voltage bias module and the drain of the low-voltage bias transistor DN2 in the low-voltage bias module, and the source of the main current-defining transistor DN1 in the high-voltage bias module and the drain of the low-voltage bias transistor DN2 in the low-voltage bias module are connected; the drain of the connection transistor DN4 is connected to the low-voltage bias module, that is, the drain of the connection transistor DN4 is connected to the drain of the low-voltage bias transistor MP2 in the low-voltage bias module.

[0047] The low-voltage bias module includes a first current mirror unit and a second current mirror unit. One end of the first current mirror unit is connected to the low-voltage power supply rail VL. The other end of the first current mirror unit is grounded through the second current mirror unit, and the first current mirror unit and the second current mirror unit are connected through the high-low voltage connection module.

[0048] Specifically, the first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3, and the second current mirror unit includes a low-voltage bias transistor DN2, a low-voltage bias transistor MN1, a low-voltage bias transistor MN2, a low-voltage bias transistor DN5, and a resistor R1. The sources of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are connected to the low-voltage power supply rail VL. The drain and gate of the low-voltage bias transistor MP2 are connected, and this connection point is respectively connected to the other end of the high-low voltage connection module and the gate of the low-voltage bias transistor MP3, that is, the connection point where the drain and gate of the low-voltage bias transistor MP2 are connected is respectively connected to the drain of the connection transistor DN4 in the high-low voltage connection module and the gate of the low-voltage bias transistor MP3; the drain of the low-voltage bias transistor MP3 is connected to the drain of the low-voltage bias transistor DN5 through the resistor R1, the source of the low-voltage bias transistor DN5 is connected to the drain of the low-voltage bias transistor MN2, the sources of the low-voltage bias transistor MN2 and the low-voltage bias transistor MN1 are grounded, the drain of the low-voltage bias transistor MN1 is connected to the source of the low-voltage bias transistor DN2, and the drain of the low-voltage bias transistor DN2 is connected to one end of the high-low voltage connection module, that is, the drain of the low-voltage bias transistor DN2 is connected to the drain of the connection transistor DN3 in the high-low voltage connection module; the gates of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 provide a preset low-voltage bias voltage VBP externally, the gates of the low-voltage bias transistor DN5, the drain of the low-voltage bias transistor MP3, and the gate of the low-voltage bias transistor DN2 provide a preset cascode bias voltage VN externally, and the drains of the low-voltage bias transistor DN5, the gates of the low-voltage bias transistor MN1, and the gates of the low-voltage bias transistor MN2 provide a preset low-voltage bias voltage VBN externally.

[0049] The connection transistors DN3 and DN4 are switching transistors, so that the source of the current definition main transistor DN1, the sources of the connection transistors DN3 and DN4, and the gate voltage of the low-voltage bias transistor MP2 are approximately equal. The width-to-length ratios of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are equal; and the width-to-length ratios of the low-voltage bias transistor DN2 and the low-voltage bias transistor DN5 are equal, and the width-to-length ratios of the low-voltage bias transistor MN1 and the low-voltage bias transistor MN2 are equal.

[0050] Based on the working voltage of the high-voltage power supply rail VH, that is, according to the working range of the input voltage, a preset number of PMOS transistors with their sources and drains connected in series are connected in series between the high-voltage power supply rail VH and the high-voltage bias voltage to protect the high-voltage bias transistor MP1.

[0051] Based on the above circuit, the working principle of the bias circuit in this solution is as follows:

[0052] When VCtrl rises, the connection transistors DN3 and DN4 act as approximate enable transistors, the circuit starts, and at the same time, the connection transistors DN3 and DN4 prevent the potential at the upper end of the resistor R0 from being too high and prevent the possible high voltage at the source of the current definition main transistor DN1, playing a protective role and completing the connection between the high-voltage area and the low-voltage area.

[0053] Since the low-voltage bias transistors MP2 and MP3 form a current mirror, and the low-voltage bias transistors DN2, MN1, MN2 and the low-voltage bias transistors DN5 and resistor R1 form a current mirror. Therefore, the current flowing through the low-voltage bias transistor MP2 is equal to the current flowing through the low-voltage bias transistor DN2. At this time, the current flowing through the current definition main transistor DN1 is equal to the current flowing through the current definition resistor R0. The current in the branch where the current definition main transistor DN1 is located is defined by the current definition main transistor DN1 and the current definition resistor R0, and there is:

[0054]

[0055]

[0056] In the formula, is the current flowing through the current definition main transistor DN1, is the carrier mobility of the current definition main transistor DN1, is the gate oxide capacitance of the current definition main transistor DN1, is the gate width of the current definition main transistor DN1, is the gate length of the current definition main transistor DN1, is the threshold voltage of the current definition main transistor DN1; represents the intrinsic conductivity factor of the MOS transistor DN1; represents the voltage value of the low-voltage power supply rail.

[0057] At this time, the current definition main transistor DN1 not only plays the role of current definition but also undertakes the function of high-low voltage isolation. The current is also the high-voltage region bias current, and the preset high-voltage bias voltage VBH is output via the high-voltage bias transistor MP1.

[0058] At this time, the source voltage of the current definition main transistor DN1 is determined, that is, the gate voltage of the low-voltage bias transistor MP2 is determined, and the preset low-voltage bias voltage VBP is output, and is converted into the low-voltage region bias voltages VBP, VBN, and VN through the low-voltage bias transistors MP3 and DN5.

[0059] After VCtrl is powered on, the circuit starts. According to the magnitude of the low-voltage voltage source, the aspect ratio of the N-type LDMOS transistor DN1 and the magnitude of the resistor R0 can be designed based on the above formula to complete the definition of the high-voltage region bias current. This current can be transmitted through the current mirror formed by the PMOS transistor MP1 to other circuit modules operating in the high-voltage region for use. By adjusting the aspect ratio of the second PMOS transistor MP2, the magnitude of the low-voltage region bias current can be determined and transmitted through the current mirror formed by the low-voltage bias transistor MN2 to other modules operating in the low-voltage region for use.

[0060] By multiplexing the functions of high-voltage-resistant MOS transistors, the present invention takes into account chip protection while saving chip area, and simultaneously generates currents in the low-voltage region and the high-voltage region, achieving the purpose of simplifying circuit design and reducing chip costs.

[0061] The present invention designs a bias circuit with high- and low-voltage connection and protection functions. The bias circuit of the present invention can provide the connection between the high-voltage region and the low-voltage region and provide protection functions to ensure the normal operation of the chip in a high-voltage environment; moreover, the MOS transistor used for protection in the present invention is also used to define the branch current, and the branch currents in the low-voltage region and the high-voltage region are defined simultaneously, saving chip area and manufacturing costs; and the structure and concept of the present invention also have certain reference significance for the high- and low-voltage connection of discrete devices.

[0062] The above are only the preferred embodiments of the present invention, but do not limit the patent scope of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or perform equivalent replacements for some of the technical features. Any equivalent structure directly or indirectly using the content of the specification and drawings of the present invention in other related technical fields is equally within the scope of the patent protection of the present invention.

Claims

1. A bias circuit with high and low voltage connection and protection functions, characterized in that: It includes a high-voltage bias module, a high-low voltage connection module, and a low-voltage bias module; the high-voltage power rail VH and the low-voltage power rail VL provide various preset bias voltages to the outside through this bias circuit. The high-voltage bias module is used to provide a preset high-voltage bias voltage to the outside, and the low-voltage bias module is used to provide various preset low-voltage bias voltages to the outside; The high-voltage bias module includes a high-voltage bias transistor MP1 and a main current-defining transistor DN1. The source of the high-voltage bias transistor MP1 is connected to the high-voltage power rail VH. The gate and drain of the high-voltage bias transistor MP1 are connected and connected to the drain of the main current-defining transistor DN1. The gate of the main current-defining transistor DN1 is connected to the low-voltage power rail VL. The source of the main current-defining transistor DN1 is connected to one end of the high-low voltage connection module and the low-voltage bias module. The gate of the high-voltage bias transistor MP1 provides a preset high-voltage bias voltage VBH to the outside; The high-low voltage connection module includes a connection transistor DN3, a connection transistor DN4, and a current-defining resistor R0. The gates of the connection transistor DN3 and the connection transistor DN4 are connected to the control signal of the bias circuit. The sources of the connection transistor DN3 and the connection transistor DN4 are connected, and the connected position is grounded through the current-defining resistor R0. The drain of the connection transistor DN3 is connected to the connection node between the high-voltage bias module and the low-voltage bias module. The drain of the connection transistor DN4 is connected to the low-voltage bias module; The low-voltage bias module includes a first current mirror unit and a second current mirror unit. One end of the first current mirror unit is connected to the low-voltage power rail VL. The other end of the first current mirror unit is grounded through the second current mirror unit, and the first current mirror unit and the second current mirror unit are connected through the high-low voltage connection module; The first current mirror unit includes a low-voltage bias transistor MP2 and a low-voltage bias transistor MP3. The second current mirror unit includes a low-voltage bias transistor DN2, a low-voltage bias transistor MN1, a low-voltage bias transistor MN2, a low-voltage bias transistor DN5, and a resistor R1. The sources of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 are connected to the low-voltage power rail VL. The drain and gate of the low-voltage bias transistor MP2 are connected, and this connection point is respectively connected to the other end of the high-low voltage connection module and the gate of the low-voltage bias transistor MP3. The drain of the low-voltage bias transistor MP3 is connected to the drain of the low-voltage bias transistor DN5 through the resistor R1. The source of the low-voltage bias transistor DN5 is connected to the drain of the low-voltage bias transistor MN2. The sources of the low-voltage bias transistor MN2 and the low-voltage bias transistor MN1 are grounded. The drain of the low-voltage bias transistor MN1 is connected to the source of the low-voltage bias transistor DN2. The drain of the low-voltage bias transistor DN2 is connected to one end of the high-low voltage connection module. The gates of the low-voltage bias transistor MP2 and the low-voltage bias transistor MP3 provide a preset low-voltage bias voltage VBP to the outside. The gates of the low-voltage bias transistor DN5, the drain of the low-voltage bias transistor MP3, and the gate of the low-voltage bias transistor DN2 provide a preset cascode bias voltage VN to the outside. The drains of the low-voltage bias transistor DN5, the gate of the low-voltage bias transistor MN1, and the gate of the low-voltage bias transistor MN2 provide a preset low-voltage bias voltage VBN to the outside.

2. The offset circuit with high and low voltage connection and protection functions according to claim 1, characterized in that: The source of the main current-defining transistor DN1, the source of the connection transistor DN3, the source of the connection transistor DN4, and the gate voltage of the low-voltage bias transistor MP2 are equal.

3. The offset circuit with high and low voltage connection and protection functions according to claim 1, characterized in that: The width-to-length ratios of the low-voltage bias transistors MP2 and MP3 are equal; the width-to-length ratios of the low-voltage bias transistors DN2 and DN5 are equal; the width-to-length ratios of the low-voltage bias transistors MN1 and MN2 are equal.

4. The offset circuit with high and low voltage connection and protection functions according to claim 1, characterized in that: Based on the operating voltage of the high-voltage power supply rail VH, a preset number of PMOS transistors with source-drain connected in series are connected between the high-voltage power supply rail VH and the high-voltage bias voltage.

5. The offset circuit with high and low voltage connection and protection functions according to claim 1, characterized in that: The current definition main transistor DN1, the low-voltage bias transistor DN2, the connection transistor DN3, the connection transistor DN4, and the low-voltage bias transistor DN5 adopt N-type high-voltage-resistant LDMOS transistors, the high-voltage bias transistor MP1, the low-voltage bias transistors MP2 and MP3 adopt PMOS transistors, and the low-voltage bias transistors MN1 and MN2 adopt NMOS transistors.

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