Online configuration methods, systems, devices, and media for clock debouncing in switches
By configuring the clock debouncing firmware online using the BMC chip in the switch, the problems of clock signal jitter and insufficient chip supply were solved, enabling the switch to operate normally and maintain stable production, thus avoiding additional material costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2022-11-08
- Publication Date
- 2026-05-26
AI Technical Summary
In high-density port switches, the clock signal generated by the clock generator introduces jitter through a long path, affecting the working state of the PHY chip. Furthermore, the supply of clock debouncing chips is insufficient, making it impossible to meet the personalized configuration needs of different customers, which restricts the production of switch products.
During the initial power-on and restart processes of the switch, the BMC chip reads the clock debouncing model and reconfigures the firmware as needed. The timing is controlled by the switch's internal BMC system, and a custom chip of the same series is selected for online configuration, thus avoiding increased material costs.
This technology ensures the normal operation of the switch even when the clock debouncing chip supply voltage is insufficient, avoiding additional material costs and ensuring the stable production and function of the switch products.
Smart Images
Figure CN115756562B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically to a method, system, device, and medium for online configuration of a clock debouncing device in a switch. Background Technology
[0002] In high-density port switches, the number of MAC chip SERDES is usually limited, making it impossible to generate so many ports. PHY / GearBox chips are typically used for port expansion. Both the MAC chip and the PHY chip require the same reference clock frequency, and in some demanding scenarios, their clocks must originate from the same source. Current switch designs often connect one MAC chip to multiple PHY chips, with a clock generator producing a clock extender for the PHY chips. These clock lines are often quite long, potentially passing through connectors. The signal reaching the clock extender inevitably introduces jitter, which can affect the PHY chip's operating state and cause packet loss.
[0003] Clock debouncing devices are commonly used in the industry to debouncing the clock generated by clock generators. Clock generator chips often extend a single clock input to multiple outputs, and debouncing is applied to each output clock. These clock debouncing chips are typically custom-designed and require corresponding firmware. The firmware is configured by the chip manufacturer according to specific needs and is burned into the chip via OTP at the factory, ensuring it is never lost. These chips often have numerous firmware configurations. In recent years, due to insufficient chip production capacity, chip manufacturers prioritize supplying customers with large order volumes, often leaving smaller orders unmet. Furthermore, the firmware configurations for different customers are often different and cannot be used directly. Summary of the Invention
[0004] To address the above problems, the present invention aims to provide an online configuration method, system, device, and medium for a clock debouncing device in a switch, which enables the firmware of the clock debouncing device chip to be reconfigured as needed during the initial power-on and restart processes of the switch via a BMC chip.
[0005] To achieve the above objectives, this invention provides the following technical solution: an online configuration method for a clock debouncing device in a switch, comprising:
[0006] When the switch is powered on for the first time, the BMC sends a power-on signal to the CPU.
[0007] Read the model number of the clock debouncing device using the BMC;
[0008] Determine whether the debouncer needs to be reconfigured based on the clock debouncer model;
[0009] If so, the clock debouncing device is reconfigured via the BMC, and the PHY chip is de-reset via the CPU.
[0010] If not, the PHY chip is directly reset via the CPU;
[0011] When the switch is running, the BMC detects the preset signal status of the CPU and determines whether a hot restart or cold restart operation has occurred.
[0012] When a cold restart occurs, reconfigure the clock debouncing device.
[0013] Furthermore, the step of reading the model number of the clock debouncing device via the BMC includes:
[0014] BMC reads the clock debouncing configuration firmware via the I2C interface;
[0015] Identify the clock debouncing model from the configuration firmware.
[0016] Furthermore, the step of determining whether the debouncing device needs to be reconfigured based on the clock debouncing device model includes:
[0017] If the clock debouncing device is a custom clock debouncing device for the switch, then there is no need to reconfigure the debouncing device;
[0018] If the clock debouncing device is a clock debouncing device from the same series as the switch, then the debouncing device needs to be reconfigured.
[0019] Furthermore, the reconfiguration of the clock debouncing device via BMC includes:
[0020] The BMC controls the writing of the required configuration firmware into the clock debouncing unit via the I2C interface.
[0021] Furthermore, the configuration duration of the BMC reconfiguration clock debouncing device is less than or equal to 5 seconds.
[0022] Furthermore, the step of detecting the CPU's preset signal state via BMC and determining whether a hot reboot or cold reboot operation has occurred includes:
[0023] The BMC will detect the status of the CPU's PLT_RST and S4 signals;
[0024] When the PLT_RST signal has a falling edge and the S4 signal has a rising edge, the switch performs a cold restart; when the PLT_RST signal has a falling edge and the S4 signal remains unchanged, the switch performs a warm restart.
[0025] Furthermore, the reconfiguration of the clock debouncing device when a cold restart operation occurs includes:
[0026] Read the model number of the clock debouncing device using the BMC;
[0027] Determine whether the clock debouncing device is a clock debouncing device of the same series as the switch;
[0028] If so, reconfigure the clock debouncing via BMC;
[0029] If not, then the process ends directly.
[0030] Accordingly, the present invention also discloses an online configuration system for a clock debouncing device in a switch, comprising: a power-on unit, used to send a power-on signal from the BMC to the CPU when the switch is first powered on;
[0031] The reading unit is used to read the model number of the clock debouncing device via the BMC.
[0032] The judgment unit determines whether the clock debouncer needs to be reconfigured based on the clock debouncer model.
[0033] The configuration unit is used to reconfigure the clock debouncing unit via the BMC and to de-reset the PHY chip via the CPU.
[0034] The signal recognition unit is used to detect the preset signal status of the CPU through the BMC when the switch is running, and to determine whether a hot restart or cold restart operation has occurred.
[0035] Accordingly, this invention discloses an online configuration device for a clock debouncing device in a switch, comprising:
[0036] The memory is used to store the online configuration program for the clock debouncing device in the switch;
[0037] The processor is configured to implement the steps of the online configuration method for the clock debouncing device in the switch as described above when executing the online configuration program for the clock debouncing device in the switch.
[0038] Accordingly, the present invention discloses a readable storage medium storing an online configuration program for a clock debouncing device in a switch. When the online configuration program for a clock debouncing device in a switch is executed by a processor, it implements the steps of the online configuration method for a clock debouncing device in a switch as described in any of the above claims.
[0039] Compared with existing technologies, the advantages of this invention are as follows: This invention discloses an online configuration method, system, device, and medium for clock debouncing in a switch. When the custom chip supply voltage to the clock debouncing in the switch is insufficient, other custom chips from the same series can be selected. The firmware of the clock debouncing chip is reconfigured via the BMC chip during the initial power-on and restart processes of the switch, without increasing any material costs, thus ensuring the production of switch products. This invention utilizes the switch's internal BMC system, controlling the power-on sequence of the switching system through the BMC, shortening the online programming time for configuring the clock debouncing, and ensuring the normal operation of the switch.
[0040] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0042] Figure 1 This is a flowchart illustrating a specific embodiment of the present invention.
[0043] Figure 2 This is a flowchart illustrating the reconfiguration of the clock debouncing firmware during the switch restart process in a specific embodiment of the present invention.
[0044] Figure 3 This is a system structure diagram of a specific embodiment of the present invention.
[0045] In the diagram, 1 is the power-on unit; 2 is the reading unit; 3 is the judgment unit; 4 is the configuration unit; and 5 is the signal recognition unit. Detailed Implementation
[0046] The core of this invention is to provide an online configuration method for clock debouncing devices in switches. In the prior art, due to insufficient chip production capacity, clock debouncing devices are customized chips, and suppliers need to generate configuration firmware according to customer requirements. Chips with different customer requirements cannot be used directly.
[0047] The online configuration method for clock debouncing in a switch provided by this invention involves the following steps: First, upon initial power-on of the switch, the BMC sends a power-on signal to the CPU and reads the clock debouncing model number. At this point, the system determines whether reconfiguration of the debouncing is required based on the model number. If so, the clock debouncing is reconfigured via the BMC, and the PHY chip is reset via the CPU. If not, the PHY chip is directly reset via the CPU. During switch operation, the BMC detects the CPU's preset signal status and determines whether a hot or cold restart operation has occurred. If a cold restart operation occurs, the clock debouncing is reconfigured. Therefore, this invention can select other custom chips from the same series when the custom chip supply to the clock debouncing in the switch is insufficient. The BMC chip reconfigures the firmware of the clock debouncing chip during the initial power-on and restart processes of the switch, without increasing material costs, thus ensuring the production of switch products.
[0048] To enable those skilled in the art to better understand the present invention, the specific application scenarios involved in the present invention are described below:
[0049] Existing switch boards contain one or more clock debouncing units. The clock generator produces a 156.25MHz clock signal. After passing through long paths and connectors, jitter is introduced into the clock signal. The clock debouncing unit eliminates this jitter and then generates multiple clock outputs to the PHY chip, ensuring that the MAC chip and PHY chip have the same reference clock. The configuration firmware of the clock debouncing unit can be programmed via OTP before leaving the factory or loaded via an external EEPROM. However, this method increases the cost of the EEPROM chip. During PCBA production, the EEPROM also needs to be programmed offline, increasing manufacturing costs. Therefore, the industry typically uses OTP clock debouncing units. Clock debouncing units are customized chips. Suppliers also generate configuration firmware according to customer requirements. Chips with different customer needs cannot be used directly. In recent years, chip supply has been tight. Suppliers usually prioritize customers with large shipment volumes, while smaller-volume customers face chip shortages, affecting product delivery. Suppliers print different silkscreens for different customers' chips. These chips are completely identical in hardware, differing only in configuration firmware.
[0050] These clock debouncing chips typically have I2C or SPI interfaces for loading firmware or modifying chip configurations. Modifications take effect immediately, allowing for online modification of clock debouncing chips within the same series (custom chips with high production volumes) via the I2C interface to ensure supply. However, switch systems are complex, primarily comprising CPU systems, switching chip systems, and PHY chip switching systems. These three systems are highly coupled, and the PHY chip timing requires a stable clock. If the PHY chip's reference clock is unstable, it can ultimately lead to the failure of the entire switch. Furthermore, switch operating modes are complex, including initial power-on, cold reboot, and warm reboot. All three scenarios require configuring the clock debouncing chip to meet hardware timing requirements.
[0051] In addition, a switch system typically includes a BMC (Block Controller) system, a completely independent CPU system that monitors the switch's hardware status. After the clock stabilizes, the CPU resets the PHY chip before configuring its operating mode. If a clock problem occurs, the PHY chip will fail to initialize, causing the entire switching plane to malfunction. In terms of the power-on sequence, the CPU system is always powered on only after the BMC system has been powered on. In the switch's power-on timing design, the time from PHY chip clock stabilization to PHY chip reset is very short. Therefore, with proper design of the BMC's clock debouncing configuration software logic, it is possible to implement online firmware updates for the clock debouncing device through the BMC.
[0052] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0053] Example 1:
[0054] like Figure 1 As shown in the figure, this embodiment provides an online configuration method for a clock debouncing device in a switch, including the following steps:
[0055] S1: When the switch is powered on for the first time, the BMC sends a power-on signal to the CPU.
[0056] S2: Read the model of the clock debouncing device via BMC.
[0057] First, the BMC reads the clock debouncing device's configuration firmware via the I2C interface; then it identifies the clock debouncing device's model from the configuration firmware.
[0058] S3: Determine whether the clock debouncing needs to be reconfigured based on the clock debouncing model. If yes, proceed to step S4; otherwise, proceed to step S5.
[0059] Specifically, if the clock debouncing device is determined to be a custom clock debouncing device for the switch based on its model number, then the debouncing device does not need to be reconfigured; if the clock debouncing device is determined to be a clock debouncing device of the same series adapted for the switch based on its model number, then the debouncing device needs to be reconfigured.
[0060] S4: Reconfigure the clock debouncing device via BMC.
[0061] Specifically, the BMC controls the writing of the required configuration firmware into the clock debouncing unit via the I2C interface.
[0062] It is important to note that the BMC reconfiguration time for the clock debouncing device must not be too long and must be kept within 5 seconds. If the configuration time exceeds 5 seconds, the switching plane will be powered on and the PHY chip will be reset. If the clock debouncing device has not yet stably output a 156.26MHz clock at this time, the PHY chip will not work properly and the CPU software will not be able to initialize the PHY chip.
[0063] S5: Reset the PHY chip via CPU.
[0064] S6: When the switch is running, the BMC detects the preset signal status of the CPU and determines whether a hot restart or cold restart operation has occurred.
[0065] The CPU's preset signals include the PLT_RST and S4 signals. When the PLT_RST signal falls, the system will shut down. If the S4 signal does not change, it is a warm restart. During a warm restart, the switching plane will not be powered off, and the BMC does not need to reconfigure the clock debouncing device. After the PLT_RST signal falls, a cold restart involves a power-off and power-on process on the switching plane, so the clock debouncing device needs to be reconfigured during a cold restart.
[0066] S7. When a cold restart occurs, reconfigure the clock debouncing device.
[0067] As an example, steps S6 and S7 above implement firmware reconfiguration for the clock debouncing device during switch reboot. Figure 2 As shown, the specific process is as follows:
[0068] 1. Determine if the PLT_RST signal has a falling edge. If so, proceed to the next step; otherwise, terminate directly.
[0069] 2. Determine if the S4 signal has a rising edge. If so, proceed to the next step; otherwise, terminate directly.
[0070] 3. Read the clock debouncer signal.
[0071] 4. Determine if the clock debouncing device is a clock debouncing device of the same series as the switch. If yes, reconfigure the clock debouncing device through the BMC; otherwise, end the process directly.
[0072] This embodiment provides an online configuration method for clock debouncing devices in a switch. When the custom chip supply voltage to the clock debouncing device in the switch is insufficient, other custom chips from the same series can be selected. The firmware of the clock debouncing chip is reconfigured via the BMC chip during the switch's initial power-on and restart processes, without increasing any material costs, thus ensuring the smooth production of the switch product. This method utilizes the switch's internal BMC system, which controls the power-on sequence of the switching system, shortening the online programming time for configuring the clock debouncing device and ensuring the switch can operate normally.
[0073] Example 2:
[0074] Based on Example 1, such as Figure 3 As shown, the present invention also discloses an online configuration system for a clock debouncing device in a switch, comprising: a power-on unit 1, a reading unit 2, a judgment unit 3, a configuration unit 4, and a signal identification unit 5.
[0075] Power-on unit 1 is used to send a power-on signal from the BMC to the CPU when the switch is powered on for the first time.
[0076] Reading unit 2 is used to read the model of the clock debouncing device via the BMC.
[0077] The reading unit 2 is specifically used to: read the configuration firmware of the clock debouncing device via the I2C interface using the BMC; and identify the model of the clock debouncing device from the configuration firmware.
[0078] Judgment Unit 3 determines whether the clock debouncing needs to be reconfigured based on the clock debouncing model. Specifically, Judgment Unit 3 is used as follows: if the clock debouncing model determines that the clock debouncing is a customized clock debouncing for the switch, then the clock debouncing does not need to be reconfigured; if the clock debouncing model determines that the clock debouncing is a clock debouncing of the same series adapted for the switch, then the clock debouncing needs to be reconfigured.
[0079] Configuration unit 4 is used to reconfigure the clock debouncing device via BMC and to de-reset the PHY chip via CPU.
[0080] The signal identification unit 5 is used to detect the preset signal status of the CPU through the BMC when the switch is running, and to determine whether a hot restart or cold restart operation has occurred.
[0081] The signal identification unit 5 is specifically used to: detect the status of the CPU's PLT_RST signal and S4 signal through the BMC; when the PLT_RST signal has a falling edge and the S4 signal has a rising edge, the switch performs a cold restart operation; when the PLT_RST signal has a falling edge and the S4 signal does not change, the switch performs a hot restart operation.
[0082] This embodiment provides an online configuration system for clock debouncing devices in switches. When the custom chip supply voltage of the clock debouncing device in the switch is insufficient, other custom chips in the same series can be selected. The firmware of the clock debouncing device chip can be reconfigured through the BMC chip during the initial power-on and restart process of the switch without increasing any material costs, thereby ensuring the production of switch products.
[0083] Example 3:
[0084] This embodiment discloses an online configuration device for a clock debouncing device in a switch, including a processor and a memory; wherein, when the processor executes the online configuration program for the clock debouncing device in the switch stored in the memory, it performs the following steps:
[0085] 1. When the switch is powered on for the first time, the BMC sends a power-on signal to the CPU.
[0086] 2. Read the model number of the clock debouncing device using the BMC.
[0087] 3. Determine whether the clock debouncing needs to be reconfigured based on the clock debouncing model. If yes, proceed to step 4; otherwise, proceed to step 5.
[0088] 4. Reconfigure the clock debouncing device via BMC.
[0089] 5. Reset the PHY chip via the CPU.
[0090] 6. When the switch is running, the BMC detects the preset signal status of the CPU and determines whether a hot restart or cold restart operation has occurred.
[0091] 7. When a cold restart occurs, reconfigure the clock debouncing device.
[0092] Furthermore, the online configuration device for the clock debouncing device in the switch in this embodiment may also include:
[0093] The input interface is used to acquire the online configuration program for the clock debouncing device in the switch imported from an external source, and save the acquired online configuration program to the memory. It can also be used to acquire various instructions and parameters transmitted from external terminal devices and transmit them to the processor, so that the processor can perform corresponding processing using these instructions and parameters. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk read interface, etc.
[0094] An output interface is used to output various data generated by the processor to connected terminal devices, so that other terminal devices connected to the output interface can obtain the various data generated by the processor. In this embodiment, the output interface may include, but is not limited to, a USB interface, a serial interface, etc.
[0095] A communication unit is used to establish a remote communication connection between the online configuration device for the clock debouncing device in the switch and an external server, so that the online configuration device for the clock debouncing device in the switch can mount the image file to the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on wireless communication technology or wired communication technology.
[0096] The keyboard is used to acquire various parameter data or commands input by the user through real-time keystrokes.
[0097] The monitor is used to display relevant information in real time regarding the process of locating a short circuit in the server's power supply line.
[0098] A mouse can be used to assist users in inputting data and simplifying user operations.
[0099] Example 4:
[0100] This embodiment also discloses a readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores an online configuration program for a clock debouncing device in a switch. When executed by a processor, the online configuration program for the clock debouncing device in the switch performs the following steps:
[0101] 1. When the switch is powered on for the first time, the BMC sends a power-on signal to the CPU.
[0102] 2. Read the model number of the clock debouncing device using the BMC.
[0103] 3. Determine whether the clock debouncing needs to be reconfigured based on the clock debouncing model. If yes, proceed to step 4; otherwise, proceed to step 5.
[0104] 4. Reconfigure the clock debouncing device via BMC.
[0105] 5. Reset the PHY chip via the CPU.
[0106] 6. When the switch is running, the BMC detects the preset signal status of the CPU and determines whether a hot restart or cold restart operation has occurred.
[0107] 7. When a cold restart occurs, reconfigure the clock debouncing device.
[0108] In summary, this invention enables the BMC chip to reconfigure the firmware of the clock debouncing chip as needed during the initial power-on and restart processes of the switch.
[0109] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the method section.
[0110] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0111] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.
[0112] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0113] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit.
[0114] Similarly, in the various embodiments of the present invention, each processing unit can be integrated into a functional module, or each processing unit can exist physically, or two or more processing units can be integrated into a functional module.
[0115] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0116] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0117] The above provides a detailed description of the online configuration method, system, device, and readable storage medium for the clock debouncing device in a switch provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.
Claims
1. A method for online configuration of a clock de-bouncer in a switch, characterized in that, include: When the switch is powered on for the first time, the BMC sends a power-on signal to the CPU. Read the model number of the clock debouncing device using the BMC; Determine whether the debouncer needs to be reconfigured based on the clock debouncer model; If so, the clock debouncing device is reconfigured via the BMC, and the PHY chip is de-reset via the CPU. If not, the PHY chip is directly reset via the CPU; When the switch is running, the BMC detects the preset signal status of the CPU and determines whether a hot restart or cold restart operation has occurred. When a cold restart occurs, the clock debouncing device should be reconfigured. The step of detecting the preset signal state of the CPU through the BMC and determining whether a hot reboot or cold reboot operation has occurred includes: The BMC will detect the status of the CPU's PLT_RST and S4 signals; When the PLT_RST signal has a falling edge and the S4 signal has a rising edge, the switch performs a cold restart operation. When the PLT_RST signal has a falling edge and the S4 signal remains unchanged, the switch will perform a hot restart operation.
2. The method of claim 1, wherein the method is performed in a switch clock de-bouncer. The method of reading the model of the clock debouncing device via BMC includes: BMC reads the clock debouncing configuration firmware via the I2C interface; Identify the clock debouncing model from the configuration firmware.
3. The method of online configuration of clock de-jitterer in a switch as claimed in claim 1 wherein, The step of determining whether the debouncing device needs to be reconfigured based on the clock debouncing device model includes: If the clock debouncing device is a custom clock debouncing device for the switch, then there is no need to reconfigure the debouncing device; If the clock debouncing device is a clock debouncing device from the same series as the switch, then the debouncing device needs to be reconfigured.
4. The method of claim 1, wherein the method is performed in a switch clock de-bouncer. The reconfiguration of the clock debouncing device via BMC includes: The BMC controls the writing of the required configuration firmware into the clock debouncing unit via the I2C interface.
5. The method of claim 4, wherein the method further comprises: The configuration time for the BMC to reconfigure the clock debouncer is less than or equal to 5 seconds.
6. The method of online configuration of a clock de-jitterer in a switch of claim 1, wherein, The reconfiguration of the clock debouncing mechanism when a cold restart occurs includes: Read the model number of the clock debouncing device using the BMC; Determine whether the clock debouncing device is a clock debouncing device of the same series as the switch; If so, reconfigure the clock debouncing via BMC; If not, then the process ends directly.
7. An online configuration system for a clock de-bouncer in a switch, characterized by, The system employs the online configuration method for clock debouncing in a switch as described in any one of claims 1 to 6; The system includes: The power-on unit is used to send a power-on signal to the CPU when the switch is powered on for the first time. The reading unit is used to read the model number of the clock debouncing device via the BMC. The judgment unit is used to determine whether the clock debouncer needs to be reconfigured based on the clock debouncer model. The configuration unit is used to reconfigure the clock debouncing unit via the BMC and to de-reset the PHY chip via the CPU. The signal recognition unit is used to detect the preset signal status of the CPU through the BMC when the switch is running, and to determine whether a hot restart or cold restart operation has occurred.
8. An online configuration device for a clock debouncing device in a switch, characterized in that, include: The memory is used to store the online configuration program for the clock debouncing device in the switch; A processor is configured to implement the steps of the online configuration method for a clock debouncing device in a switch as described in any one of claims 1 to 6 when executing the online configuration program for the clock debouncing device in the switch.
9. A readable storage medium, characterized in that: The readable storage medium stores an online configuration program for a clock debouncing device in a switch, which, when executed by a processor, implements the steps of the online configuration method for a clock debouncing device in a switch as described in any one of claims 1 to 6.