Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of fabricating the same, including: providing a bottom substrate; bonding a first stacked chip and a second stacked chip to the bottom substrate; conformally forming a first isolation layer to cover the first stacked chip and the second stacked chip and at least partially fill a gap between the first stacked chip and the second stacked chip; performing a thinning process to expose a back surface of the first stacked chip and the second stacked chip; performing a removal process to expose a through-substrate hole of the first stacked chip and the second stacked chip; forming a first cap layer to cover the through-substrate hole of the first stacked chip and the second stacked chip; and performing a planarization process to expose the through-substrate hole of the first stacked chip and the second stacked chip and provide a substantially flat surface.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 17 / 465,279, filed September 2, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for fabricating the semiconductor element, and more particularly to a semiconductor element having stacked chips and a method for fabricating the semiconductor element. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems have arisen during this shrinking process, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a bottom substrate; bonding a first stacked chip and a second stacked chip on the bottom substrate; conformally forming a first isolation layer to cover the first stacked chip and the second stacked chip, and at least partially filling a gap between the first stacked chip and the second stacked chip; performing a thinning process to expose a back surface of the first stacked chip and the second stacked chip; performing a removal process to expose a via of the first stacked chip and a via of the second stacked chip; forming a first capping layer to cover the via of the first stacked chip and the via of the second stacked chip; and performing a planarization process to expose the via of the first stacked chip and the via of the second stacked chip, and providing a substantially flat surface.

[0006] In some embodiments, the removal process is a dry etching process.

[0007] In some embodiments, the first isolation layer has an etch rate ratio of approximately 15:1 to approximately 2:1 for the dry etching process on the first stacked chip substrate.

[0008] In some embodiments, the method of fabricating the semiconductor device includes bonding a third stacked chip to the first stacked chip and bonding a fourth stacked chip to the second stacked chip.

[0009] In some embodiments, the first stacked chip and the second stacked chip are bonded to the bottom substrate by a hybrid bonding process.

[0010] In some embodiments, the process pressure of the hybrid bonding process is in the range of about 100 MPa to about 150 MPa.

[0011] In some embodiments, the process temperature of the hybrid bonding process is in the range of about 25°C to about 400°C.

[0012] In some embodiments, the method of fabricating the semiconductor element further includes a thermal annealing process after the first stacked chip and the second stacked chip are bonded to the bottom substrate.

[0013] In some embodiments, the first isolation layer includes an oxide layer, a nitride layer, or an oxynitride layer.

[0014] In some embodiments, the first capping layer includes an oxide layer, a nitride layer, or an oxynitride layer.

[0015] In some embodiments, the first stacked chip and the second stacked chip include a storage circuit.

[0016] In some embodiments, the first stacked chip includes a logic circuit, and the third stacked chip includes a memory circuit.

[0017] Another embodiment of this disclosure provides a semiconductor device, including: a bottom substrate; a first stacked chip and a second stacked chip disposed on the bottom substrate; a first isolation layer disposed on the bottom substrate and surrounding the first stacked chip and the second stacked chip; and a first capping layer disposed on a rear surface of the first stacked chip and surrounding a through-hole of the first stacked chip. A vertical height of a top surface of the first isolation layer is higher than a vertical height of the rear surface of the first stacked chip. A top surface of the through-hole of the first stacked chip, a top surface of the first isolation layer, and a top surface of the first capping layer are substantially coplanar.

[0018] In some embodiments, the thickness of the first stacked chip is equal to or less than about 10 nm (nanometer).

[0019] In some embodiments, the semiconductor element includes a third stacked chip disposed on the first stacked chip and a fourth stacked chip disposed on the second stacked chip.

[0020] In some embodiments, the first stacked chip and the third stacked chip include a storage circuit.

[0021] In some embodiments, the first stacked chip includes a logic circuit, and the third stacked chip includes a storage circuit.

[0022] In some embodiments, the semiconductor element includes a plurality of connectors disposed on the rear surface of the third stacked chip and the fourth stacked chip.

[0023] In some embodiments, the semiconductor device includes a redistribution layer disposed in the bottom substrate. The first stacked chip and the second stacked chip are electrically coupled to the redistribution layer, respectively.

[0024] In some embodiments, a conductive pad of the first stacked chip is in direct contact with the redistribution layer.

[0025] Due to the design of the semiconductor device disclosed herein, the thickness uniformity and edge profile of the chip can be improved. Therefore, the yield, quality, and performance of the semiconductor device can be improved.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Attached Figure Description

[0027] A more comprehensive understanding of the disclosure of this invention can be obtained by referring to the drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 14 This is a cross-sectional schematic diagram illustrating the fabrication process of the semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 15 This is a close-up cross-sectional schematic diagram illustrating a portion of the semiconductor element according to an embodiment of the present disclosure.

[0031] Figures 16 to 22 This is a schematic cross-sectional view illustrating some embodiments of the semiconductor device disclosed herein.

[0032] Figures 23 to 29 This is a cross-sectional schematic diagram illustrating the fabrication process of another semiconductor device according to an embodiment of the present disclosure.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 1A: Semiconductor components

[0035] 1B: Semiconductor components

[0036] 1C: Semiconductor components

[0037] 1D: Semiconductor components

[0038] 1E: Semiconductor components

[0039] 1F: Semiconductor components

[0040] 1G: Semiconductor components

[0041] 1H: Semiconductor components

[0042] 1I: Semiconductor components

[0043] 10: Preparation method

[0044] 100: Bottom base

[0045] 101: Passivation layer

[0046] 200: First bottom chip

[0047] 201: Base

[0048] 203: Interlayer dielectric layer

[0049] 205: Through-base hole

[0050] 207: Interconnection Layer

[0051] 209: Conductive pad

[0052] 211: Conductive via

[0053] 300: Second bottom chip

[0054] 301: Base

[0055] 303: Interlayer dielectric layer

[0056] 305: Through-hole

[0057] 400A: First stacked chip

[0058] 400B: Second stacked chip

[0059] 401A: Substrate

[0060] 401B: Substrate

[0061] 403A: Interlayer dielectric layer

[0062] 403B: Interlayer dielectric layer

[0063] 405A: Through-hole

[0064] 405B: Through-hole

[0065] 407A: Conductive pad

[0066] 407B: Conductive pad

[0067] 409A: Interconnection Layer

[0068] 409B: Interconnection Layer

[0069] 411A: Conductive via

[0070] 411B: Conductive via

[0071] 500A: Third-stacked chip

[0072] 500B: Fourth Stacked Chip

[0073] 601: Bottom isolation layer

[0074] 603: First Isolation Layer

[0075] 605: First capping layer

[0076] 607: Second Isolation Layer

[0077] 609: Second capping layer

[0078] 701: Connector

[0079] 703: First dummy conductive pad

[0080] 705: Second dummy conductive pad

[0081] 707: Redistribution layer

[0082] 709: First Virtual Semiconductor Via

[0083] 711: Second Dummy Semiconductor Via

[0084] 713: Bottom Connector

[0085] 715: Bottom Filler Layer

[0086] 717: Conductive pad

[0087] AL: Adhesion layer

[0088] FL: Fill layer

[0089] G1: First gap

[0090] G2: Second gap

[0091] IL: Insulating layer

[0092] S11: Steps

[0093] S13: Steps

[0094] S15: Steps

[0095] S17: Steps

[0096] S19: Steps

[0097] S21: Steps

[0098] S23: Steps

[0099] S25: Steps

[0100] S27: Steps

[0101] SL: Seed layer

[0102] T1: Thickness

[0103] T2: Thickness

[0104] T3: Thickness

[0105] T4: Thickness

[0106] T5: Thickness

[0107] T6: Thickness Detailed Implementation

[0108] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0109] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0110] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0111] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to impose limitations. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description below of forming a first feature "on" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed within the range of the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0112] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figure but also different orientations of the element in use or operation. The element may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be translated accordingly.

[0113] In this disclosure, semiconductor components generally refer to components that can function by utilizing the properties of semiconductors. Electro-optical components, light-emitting display electro-optical components, semiconductor circuits, and electronic electro-optical components are all included in the scope of semiconductor electro-optical components.

[0114] In this disclosure, "above" (or "up") corresponds to the direction of the arrow in direction Z, and "below" (or "down") corresponds to the opposite direction of the arrow in direction Z.

[0115] Figure 1 This is a schematic flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 14This is a schematic cross-sectional view illustrating the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 15 This is a schematic close-up cross-sectional view illustrating a portion of a semiconductor element 1A according to an embodiment of the present disclosure.

[0116] Reference Figure 1 and Figure 2 In step S11, a bottom substrate 100 can be provided, and a first bottom chip 200 and a second bottom chip 300 can be bonded to the bottom substrate 100.

[0117] Reference Figure 2 The bottom substrate 100 may be a wafer, chip, package substrate, or interposer. In some embodiments, the bottom substrate 100 may include logic circuitry. In some embodiments, the bottom substrate 100 may include memory circuitry, such as control circuitry or high-speed circuitry. In some embodiments, the bottom substrate 100 may not include any functional unit.

[0118] In the description of this disclosure, a functional unit generally refers to circuitry associated with a function, which has been divided into independent units. In some embodiments, a functional unit may typically be a highly complex circuit, such as a processor core, memory controller, control circuitry, high-speed circuitry, or accelerator unit. In other embodiments, the complexity and functionality of the functional unit may be more or slightly more complex.

[0119] Reference Figure 2 The first bottom chip 200 may include a substrate 201, an interlayer dielectric layer 203, a plurality of vias 205, a plurality of device elements (not shown for clarity), and a plurality of conductive features.

[0120] Reference Figure 2The interlayer dielectric layer 203 can be bonded to the front surface of the bottom substrate 100. In some embodiments, the interlayer dielectric layer 203 can be fabricated using techniques such as silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k materials, or combinations thereof. The dielectric constant of the low-k material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k material can be less than 2.0. Multiple element units and multiple conductive features can be formed in the interlayer dielectric layer 203 and electrically coupled to each other.

[0121] It should be understood that, in the description of this disclosure, the term "front" surface is a technical term referring to the main surface of a structure on which element units and conductive features are formed. Similarly, the "rear" surface of a structure refers to the main surface opposite the front surface.

[0122] In some embodiments, the element units of the first bottom chip 200 may be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, or combinations thereof. Conductive features may include interconnect layers 207, conductive pads 209, and conductive vias 211. The interconnect layers 207 may be separated from each other and may be horizontally disposed in the interlayer dielectric layer 203 along the Z-direction. In this embodiment, the bottommost interconnect layer 207 may be designated as a conductive pad 209. The conductive vias 211 may connect adjacent interconnect layers 207, adjacent element units and interconnect layers 209, and adjacent conductive pads 209 and interconnect layers 207 along the Z-direction. In some embodiments, the conductive vias 211 may improve heat dissipation in the interlayer dielectric layer 203 and may provide structural support in the interlayer dielectric layer 203. The fabrication techniques for multiple conductive features can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0123] Multiple component units and multiple conductive features can collectively configure the functional units of the first bottom chip 200. In some embodiments, the functional units of the first bottom chip 200 can cooperate to provide logic functions. In some embodiments, the functional units of the first bottom chip 200 can cooperate to provide memory functions. In some embodiments, the functional units of the first bottom chip 200 may only include core memory circuitry, such as input / output (I / O) and clock circuitry. The functional units of the first bottom chip 200 may not include any control circuitry or high-speed circuitry. The configuration of the functional units of the first bottom chip 200 can be referred to as the layout of the first bottom chip 200.

[0124] Reference Figure 2 The substrate 201 can be formed on the interlayer dielectric layer 203. The substrate 201 can be a bulk semiconductor substrate. The fabrication technology of the bulk semiconductor substrate can be, for example, elementary semiconductors such as silicon or germanium, or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V or II-VI compound semiconductors.

[0125] Reference Figure 2 Multiple vias 205 can be formed in the substrate 201. The bottom surfaces of the multiple vias 205 can be substantially coplanar with the interface between the substrate 201 and the interlayer dielectric layer 203. The multiple vias 205 can be electrically coupled to multiple element units via multiple conductive features. In some embodiments, the configuration of the multiple vias 205 may also be referred to as part of the layout of the first bottom chip 200.

[0126] Reference Figure 2 The second bottom chip 300 can be bonded to the front surface of the bottom substrate 100. The second bottom chip 300 can be spaced from the first bottom chip 200 by a first gap G1.

[0127] Reference Figure 2 The second bottom chip 300 may include a structure similar to that of the first bottom chip 200. For example, the second bottom chip 300 may include a substrate 301, an interlayer dielectric layer 303, a plurality of vias 305, a plurality of element units, and a plurality of conductive features. The second bottom chip 300, which has the same or similar name (or symbol) as the first bottom chip 200, may have the same or similar structure and may be made of the same or similar materials. Its contents will not be described again here.

[0128] In some embodiments, multiple component units and multiple conductive features may jointly configure the functional units of the second bottom chip 300. In some embodiments, the functional units of the second bottom chip 300 may cooperate to provide logic functions. In some embodiments, the functional units of the second bottom chip 300 may cooperate to provide memory functions. In some embodiments, the functional units of the second bottom chip 300 may include only core memory circuitry, such as input / output (I / O) and clock circuitry. The functional units of the second bottom chip 300 may not include any control circuitry or high-speed circuitry. The configuration of the functional units of the second bottom chip 300 may be referred to as the layout of the second bottom chip 300. In some embodiments, the layout of the first bottom chip 200 and the layout of the second bottom chip 300 are the same. In some embodiments, the layout of the first bottom chip 200 and the layout of the second bottom chip 300 are different. For example, the layout of the first bottom chip 200 and the layout of the second bottom chip 300 are symmetrical to each other. As another example, the layout of the first bottom chip 200 may be reflectively symmetrical with respect to the layout of the second bottom chip 300.

[0129] In some embodiments, the first bottom chip 200 and the second bottom chip 300 may be bonded to the front surface of the bottom substrate 100 via a hybrid bonding process, such as thermoforming, passivation-capping-layer-assisted bonding, or surface activation bonding. In some embodiments, the process pressure of the hybrid bonding process may be in the range of approximately 100 MPa to approximately 150 MPa. In some embodiments, the process temperature of the hybrid bonding process may be in the range of approximately room temperature (e.g., 25°C) to approximately 400°C. In some embodiments, surface treatments, such as wet chemical cleaning and gas / vapor phase heat treatment, may be used to reduce the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process. In some embodiments, the hybrid bonding process may include, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. In some embodiments, thermal annealing may be performed after the bonding process to enhance the bonding between dielectrics and induce thermal expansion between metals, thereby further improving the bonding quality.

[0130] Reference Figure 1 , Figure 3 and Figure 4 In step S13, a bottom isolation layer 601 can be formed on the bottom substrate 100, and a planarization process can be performed to expose a plurality of through-holes 205, 305 of the first bottom chip 200 and the second bottom chip 300.

[0131] Reference Figure 3A bottom isolation layer 601 may be conformally formed on a bottom substrate 100 to cover the first bottom chip 200 and the second bottom chip 300, and at least partially fill the first gap G1 between the first bottom chip 200 and the second bottom chip 300. In some embodiments, the first gap G1 may be completely filled by the bottom isolation layer 601. In some embodiments, the bottom isolation layer 601 may be fabricated using materials that are etch-selective for both the substrate 201 and the substrate 301. In some embodiments, the bottom isolation layer 601 may be fabricated using silicon oxide. In some embodiments, the bottom isolation layer 601 may be fabricated using silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material may be less than 3.0 or even less than 2.5. In some embodiments, the low dielectric constant material may have a dielectric constant less than 2.0. The bottom isolation layer 601 may be fabricated using deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes.

[0132] Reference Figure 4 A planarization process, such as chemical mechanical polishing, can be performed until the top surfaces of the plurality of through-holes 205 and 305 are exposed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, after the planarization process, the first bottom chip 200 and the second bottom chip 300 may have the same thickness, but this disclosure is not limited thereto. In some embodiments, the thickness T1 of the first bottom chip 200 may be less than or equal to about 10 μm. In some embodiments, the thickness T2 of the second bottom chip 300 may be less than or equal to about 10 μm. In some embodiments, the first bottom chip 200 and the second bottom chip 300 may be configured together in a bottom layer stack. The thickness of the bottom layer stack may be less than or equal to about 10 μm.

[0133] Since the bottom isolation layer 601 completely or partially fills the first gap G1, the top surfaces of the multiple through-holes 205 and the multiple through-holes 305, the top surface of the base 201, the top surface of the base 301 and the top surface of the bottom isolation layer 601 can be substantially coplanar.

[0134] Conversely, if the first gap G1 between the first bottom chip 200 and the second bottom chip 300 is not filled, the thickness uniformity may be worse, and the edges of the chips may become rounded. Both of these phenomena can have a serious adverse impact on subsequent processes, thus affecting the yield and quality of the fabricated semiconductor devices.

[0135] Furthermore, the planarization process is performed after the first bottom chip 200 and the second bottom chip 300 are bonded to the bottom substrate 100, and a carrier substrate may not be required to provide support during bonding. The absence of a carrier substrate can reduce fabrication costs and increase yield.

[0136] Reference Figure 1 , Figure 5 and Figure 6 In step S15, the first stacked chip 400A can be bonded to the first bottom chip 200, and the second stacked chip 400B can be bonded to the second bottom chip 300.

[0137] Reference Figure 5 The first stacked chip 400A may include a substrate 401A, an interlayer dielectric layer 403A, a plurality of vias 405A, a plurality of element units (not shown for clarity), and a plurality of conductive features (not shown for clarity).

[0138] Reference Figure 5 and Figure 6 The interlayer dielectric layer 403A can be bonded to the first bottom chip 200. In some embodiments, the interlayer dielectric layer 403A can be fabricated using, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material can be less than 2.0. Multiple element units and multiple conductive features can be formed in the interlayer dielectric layer 403A and electrically coupled to each other.

[0139] The element units of the first stacked chip 400A can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, or combinations thereof. The conductive features of the first stacked chip 400A may include multiple conductive pads 407A, multiple interconnect layers 409A, and multiple conductive vias 411A. The interconnect layers 409A may be separated from each other and may be horizontally disposed along the Z-direction in the interlayer dielectric layer 203. In this embodiment, the bottommost interconnect layer 409A may be designated as a conductive pad 407A. The conductive vias 411A may connect adjacent interconnect layers 409A, adjacent element units and interconnect layers 409A, and adjacent conductive pads 407A and interconnect layers 409A along the Z-direction. In some embodiments, the conductive vias 411A may improve heat dissipation in the interlayer dielectric layer 403A and may provide structural support in the interlayer dielectric layer 403A. The fabrication techniques for multiple conductive features can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0140] Multiple component units and multiple conductive features can be collectively configured as functional units of the first stacked chip 400A. In some embodiments, the functional units of the first stacked chip 400A can cooperate to provide logic functions. In some embodiments, the functional units of the first stacked chip 400A can cooperate to provide memory functions. In some embodiments, the functional units of the first stacked chip 400A may only include core memory circuitry, such as input / output (I / O) and clock circuitry. The functional units of the first stacked chip 400A may not include any control circuitry or high-speed circuitry. The configuration of the functional units of the first stacked chip 400A can be referred to as the layout of the first stacked chip 400A. In some embodiments, the layout of the first stacked chip 400A is different from the layout of the first bottom chip 200. For example, the layout of the first stacked chip 400A and the layout of the first bottom chip 200 are mutually symmetrical. Another example is that the layout of the first stacked chip 400A may be reflectively symmetrical with respect to the layout of the first bottom chip 200. In some embodiments, the layout of the first stacked chip 400A and the layout of the first bottom chip 200 may be the same.

[0141] Reference Figure 5 and Figure 6 The substrate 401A can be formed on the interlayer dielectric layer 403A. The substrate 401A can be a bulk semiconductor substrate. The fabrication technology of the bulk semiconductor substrate can be, for example, basic semiconductors such as silicon or germanium, or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V or II-VI compound semiconductors.

[0142] Reference Figure 5 and Figure 6 Through-holes 405A can be formed in the substrate 401A. The bottom surfaces of the plurality of through-holes 405A can be substantially coplanar with the interface between the substrate 401A and the interlayer dielectric layer 403A. The plurality of through-holes 405A can be electrically coupled to a plurality of element units of the first stacked chip 400A via a plurality of conductive features of the first stacked chip 400A. In some embodiments, the configuration of the plurality of through-holes 405A may also be referred to as part of the layout of the first stacked chip 400A.

[0143] Reference Figure 5 and Figure 6 The second stacked chip 400B can be bonded to the second bottom chip 300. The second stacked chip 400B can be spaced from the first stacked chip 400A by a second gap G2.

[0144] Reference Figure 5 and Figure 6The second stacked chip 400B may include a structure similar to that of the first stacked chip 400A. For example, the second stacked chip 400B may include a substrate 401B, an interlayer dielectric layer 403B, multiple vias 405B, multiple element units, and multiple conductive features, including multiple conductive pads 407B, multiple interconnect layers 409B, and multiple conductive vias 411B. The second stacked chip 400B, which has the same or similar name (or symbol) as the first stacked chip 400A, may have the same or similar structure and may be made of the same or similar materials. Its details will not be repeated here.

[0145] In some embodiments, multiple component units and multiple conductive features can jointly configure the functional units of the second stacked chip 400B. In some embodiments, the functional units of the second stacked chip 400B can cooperate to provide logic functions. In some embodiments, the functional units of the second stacked chip 400B can cooperate to provide memory functions. In some embodiments, the functional units of the second stacked chip 400B may only include core memory circuitry, such as input / output (I / O) and clock circuitry. The functional units of the second stacked chip 400B may not include any control circuitry or high-speed circuitry. The configuration of the functional units of the second stacked chip 400B can be referred to as the layout of the second stacked chip 400B. In some embodiments, the layout of the second stacked chip 400B is the same as the layout of the second bottom chip 300. In some embodiments, the layout of the second stacked chip 400B is different from the layout of the second bottom chip 300. For example, the layout of the second stacked chip 400B and the layout of the second bottom chip 300 are mutually symmetrical. As another example, the layout of the second stacked chip 400B may be reflectively symmetrical with respect to the layout of the second bottom chip 300.

[0146] Reference Figure 5 and Figure 6In some embodiments, the first stacked chip 400A and the second stacked chip 400B may have the same thickness, but this disclosure is not limited thereto. In some embodiments, the first stacked chip 400A and the second stacked chip 400B may be bonded to the first bottom chip 200 and the second bottom chip 300 respectively by a hybrid bonding process, such as a thermoforming bonding process, a passivation-capping assisted bonding process, or a surface activation bonding process. In some embodiments, the first stacked chip 400A may be bonded to the first bottom chip 200 in a face-to-back configuration, but this disclosure is not limited thereto. In some embodiments, the second stacked chip 400B may be bonded to the second bottom chip 300 in a face-to-back configuration, but this disclosure is not limited thereto. In some embodiments, the process pressure of the hybrid bonding process may be in the range of approximately 100 MPa to approximately 150 MPa. In some embodiments, the process temperature of the hybrid bonding process may be in the range of approximately room temperature (e.g., 25°C) to approximately 400°C. In some embodiments, surface treatments, such as wet chemical cleaning and vapor / vapor phase heat treatment, can be used to reduce the process temperature or shorten the time consumption of the hybrid bonding process. In some embodiments, the hybrid bonding process may include dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. In some embodiments, thermal annealing may be performed after the bonding process to enhance the bonding between dielectrics and induce thermal expansion between metals, thereby further improving the bonding quality.

[0147] Reference Figure 1 and Figure 7 In step S17, a first isolation layer 603 can be formed on the first stacked chip 400A and the second stacked chip 400B.

[0148] Reference Figure 7A first isolation layer 603 is conformally formed on a bottom isolation layer 601 to cover the first stacked chip 400A and the second stacked chip 400B, and at least partially fills the second gap G2 between the first stacked chip 400A and the second stacked chip 400B. That is, the bottom isolation layer 601 may surround the first stacked chip 400A and the second stacked chip 400B. In some embodiments, the thickness T3 of the first isolation layer 603 may be in the range of approximately 2 μm to approximately 7 μm, or in the range of approximately 4 μm to approximately 5 μm. In some embodiments, the second gap G2 may be completely filled by the first isolation layer 603. In some embodiments, the fabrication technique of the first isolation layer 603 is, for example, a material with etch selectivity for the substrates 401A and 401B. In some embodiments, the fabrication technique of the first isolation layer 603 is, for example, silicon oxide. In some embodiments, the fabrication technique of the first isolation layer 603 is, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material can be less than 2.0. The first insulating layer 603 can be fabricated by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or a similar process.

[0149] Reference Figure 1 and Figure 8 In step S19, a thinning process can be performed to expose the back surfaces of the first stacked chip 400A and the second stacked chip 400B.

[0150] Reference Figure 8 The thinning process can be accomplished by, for example, using wafer polishing, mechanical polishing, polishing, or similar processes, or by using chemical removal processes, such as wet etching. An advantage, but not a limiting, feature of the illustrated embodiment is that by bonding the first stacked chip 400A and the second stacked chip 400B prior to thinning, a carrier substrate may not be required to provide support during bonding. The absence of a carrier substrate can reduce fabrication costs and increase yield. The thinning process can improve heat dissipation and provide a lower device profile. It should be understood that, at this stage, the top surface of the first isolation layer 603 and the rear surfaces of the first stacked chip 400A and the second stacked chip 400B can be substantially coplanar.

[0151] Reference Figure 1 and Figure 9 In step S21, a removal process can be performed to expose multiple vias 405A and 405B of the first stacked chip 400A and the second stacked chip 400B.

[0152] Reference Figure 9The removal process can be, for example, an etching process. Specifically, the etching process can be a dry etching process. The etching process can selectively remove the substrates 401A and 401B of the first stacked chip 400A and the second stacked chip 400B. During the etching process, the etching rate ratio of the first isolation layer 603 to the substrates 401A and 401B can be in the range of approximately 100:1 to approximately 1.05:1, approximately 15:1 to approximately 2:1, or approximately 10:1 to approximately 2:1. During the etching process, the etching rate ratio of the vias 405A and 405B to the substrates 401A and 401B can be in the range of approximately 100:1 to approximately 1.05:1, approximately 15:1 to approximately 2:1, or approximately 10:1 to approximately 2:1. Using an etching process instead of a chemical mechanical polishing process can result in better thickness uniformity of the substrates 401A and 401B. It should be understood that, at this stage, the top surface of the first isolation layer 603 may be higher than the top surface of the plurality of through holes 405A, 405B by a vertical height and the rear surface of the substrates 401A, 401B by a vertical height. The plurality of through holes 405A, 405B may protrude from the top surface of the substrates 401A, 401B respectively and accordingly.

[0153] Reference Figure 1 and Figure 10 In step S23, a first capping layer 605 can be formed to cover multiple through-holes 405A and 405B of the first stacked chip 400A and the second stacked chip 400B.

[0154] Reference Figure 10 The first capping layer 605 can be conformally formed on the first stacked chip 400A and the second stacked chip 400B to cover a plurality of through-holes 405A, 405B, substrates 401A, 401B, and the first isolation layer 603. In some embodiments, the thickness T4 of the first capping layer 605 can be in the range of about 2 μm to about 8 μm, or about 4 μm to about 5 μm. In some embodiments, the first capping layer 605 is fabricated using the same material as the first isolation layer 603. In some embodiments, the first capping layer 605 is fabricated using, for example, silicon oxide. In some embodiments, the first capping layer 605 is fabricated using, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material can be less than 2.0. The first capping layer 605 is manufactured using a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or a similar process.

[0155] Reference Figure 1 and Figure 11 In step S25, a planarization process can be performed to expose the top surfaces of multiple through-holes 405A and 405B of the first stacked chip 400A and the second stacked chip 400B.

[0156] Reference Figure 11 A planarization process, such as chemical mechanical polishing, can be performed to expose the top surfaces of multiple through-holes 405A, 405B to remove excess material and provide a substantially flat surface for subsequent process steps. After the planarization process, the top surfaces of the multiple through-holes 405A, 405B and the top surface of the first capping layer 605 may be substantially coplanar. In some embodiments, the top surface of the first isolation layer 603 may be substantially coplanar with the top surface of the first capping layer 605. In some embodiments, a portion of the first capping layer 605 may surround the multiple through-holes 405A, 405B. In some embodiments, a portion of the first capping layer 605 may be surrounded by the first isolation layer 603. A first stacked chip 400A and a second stacked chip 400B are configured together in a first stack. In some embodiments, after the planarization process, the thickness T5 of the first stacked chip 400A may be less than or equal to about 10 μm. In some embodiments, after the planarization process, the thickness T6 of the second stacked chip 400B may be less than or equal to about 10 μm. In some embodiments, after the planarization process, the thickness of the first layer may be less than or equal to approximately 10 μm.

[0157] Reference Figure 1 and Figures 12 to 14 In step S27, a third stacked chip 500A can be formed on the first stacked chip 400A, and a fourth stacked chip 500B can be formed on the second stacked chip 400B.

[0158] Reference Figure 12 The third stacked chip 500A may have a structure similar to that of the first stacked chip 400A, the description of which will not be repeated here. The third stacked chip 500A may include memory circuitry, logic circuitry, or a combination thereof. In some embodiments, the third stacked chip 500A may include only core memory circuitry, such as input / output (I / O) and clock circuitry. The third stacked chip 500A may not include any control circuitry or high-speed circuitry. In some embodiments, the layout of the third stacked chip 500A may be the same as that of the first stacked chip 400A, but this disclosure is not limited thereto.

[0159] Reference Figure 12The fourth stacked chip 500B may have a structure similar to that of the second stacked chip 400B, the description of which will not be repeated here. The fourth stacked chip 500B may include storage circuitry, logic circuitry, or a combination thereof. In some embodiments, the fourth stacked chip 500B may include only core storage circuitry, such as input / output (I / O) and clock circuitry. The fourth stacked chip 500B may not include any control circuitry or high-speed circuitry. In some embodiments, the layout of the fourth stacked chip 500B may be the same as that of the second stacked chip 400B, but this disclosure is not limited thereto.

[0160] Reference Figure 12 The third stacked chip 500A and the fourth stacked chip 500B can be achieved through a similar method. Figure 5 and Figure 6 The hybrid bonding process shown is used to bond the first stacked chip 400A and the second stacked chip 400B respectively and accordingly, and its description will not be repeated here. A second isolation layer 607 may be formed to cover the third stacked chip 500A and the fourth stacked chip 500B, and at least partially fill the gap between the third stacked chip 500A and the fourth stacked chip 500B, similar to Figure 7 The procedure shown is described herein and will not be repeated. In some embodiments, the second isolation layer 607 may have the same material as the first isolation layer 603. In some embodiments, the fabrication technique of the second isolation layer 607 is, for example, silicon oxide. In some embodiments, the fabrication technique of the second isolation layer 607 is, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant material, or combinations thereof. The dielectric constant of the low dielectric constant material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material may be less than 2.0.

[0161] Reference Figure 13 It can be used in a similar way Figures 8 to 10 The illustrated process forms a thinning process, a removal process, and a second capping layer 609, the description of which will not be repeated here. In some embodiments, the second capping layer 609 may be fabricated using the same material as the first capping layer 605. In some embodiments, the second capping layer 609 may be fabricated using, for example, silicon oxide. In some embodiments, the second capping layer 609 may be fabricated using, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-dielectric-constant materials, or combinations thereof. The dielectric constant of the low-dielectric-constant material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-dielectric-constant material may be less than 2.0.

[0162] Reference Figure 14 It can be used in a similar way Figure 11The procedure shown performs a planarization process, the description of which will not be repeated here. The third stacked chip 500A and the fourth stacked chip 500B are configured together in a second stack. In some embodiments, after the planarization process, the thickness of the third stacked chip 500A may be less than or equal to approximately 10 μm. In some embodiments, after the planarization process, the thickness of the fourth stacked chip 500B may be less than or equal to approximately 10 μm. In some embodiments, after the planarization process, the thickness of the second stack may be less than or equal to approximately 10 μm.

[0163] For the sake of brevity, clarity, and ease of description, only one through-hole 205 will be described.

[0164] Reference Figure 15 The through-hole 205 may include a filling layer FL, two seed layers SL, two adhesive layers AL, two barrier layers BL, and two insulating layers IL.

[0165] Reference Figure 15 The filler layer FL can be disposed along the substrate 201. The filler layer FL can be, for example, copper. Two insulating layers IL can be disposed on both sides of the filler layer FL. In some embodiments, the two insulating layers IL can be fabricated using, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The two insulating layers IL can each have a thickness ranging from approximately 50 nm to approximately 200 nm. Alternatively, in some embodiments, the two insulating layers IL can be fabricated using, for example, parylene, epoxy, or poly(p-xylene). The two insulating layers IL can each have a thickness ranging from approximately 1 μm to approximately 5 μm. The two insulating layers IL ensure that the filler layer FL is electrically isolated within the substrate 201.

[0166] Reference Figure 15 Two barrier layers BL can be disposed between the filler layer FL and the two insulating layers IL. The two barrier layers BL can be fabricated using techniques such as tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer. The two barrier layers BL can inhibit the diffusion of conductive material from the filler layer FL to the two insulating layers IL and the substrate 201. The two barrier layers BL can be fabricated using deposition processes such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0167] Reference Figure 15Two adhesive layers AL can be disposed between the filler layer FL and the two barrier layers BL. The two adhesive layers AL can be fabricated using materials such as titanium, tantalum, titanium-tungsten, or manganese nitride. The two adhesive layers AL can improve the adhesion between the two seed layers SL and the two barrier layers BL. The two adhesive layers AL can each have a thickness ranging from approximately 5 nm to approximately 50 nm. The two adhesive layers AL can be fabricated using deposition processes such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0168] Reference Figure 15 Two seed layers (SLs) can be disposed between the fill layer (FL) and two adhesive layers (ALs). Each seed layer (SL) can have a thickness ranging from approximately 10 nm to approximately 40 nm. The two seed layers (SLs) can be fabricated using, for example, copper or ruthenium. The two seed layers (SLs) can be fabricated using deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering. During the process of forming the fill layer (FL) via electroplating, the two seed layers (SLs) can reduce resistivity.

[0169] In some embodiments, the through-holes 405A, 405B and 305 of the third stacked chip 500A and the fourth stacked chip 500B may have the same characteristics as those of the third stacked chip 500A and the fourth stacked chip 500B. Figure 15 The through-hole 205 shown has the same structure.

[0170] Figures 16 to 22 The schematic cross-sectional views illustrate semiconductor elements 1B, 1C, 1D, 1E, 1F, 1G and 1H of some embodiments of the present disclosure.

[0171] Reference Figure 16 Semiconductor element 1B can have the same characteristics as... Figure 14 Similar structures to those shown in the image. Figure 16 Zhongyu Figure 14 Identical or similar elements have been labeled with similar reference numerals, and repeated descriptions have been omitted. For brevity, clarity, and ease of description, only one through-hole 205 is described. Through-hole 205 may be disposed along the substrate 201 and extend to the interlayer dielectric layer 203. In some embodiments, through-hole 205 may be disposed along the substrate 201 and the interlayer dielectric layer 203. In some embodiments, through-hole 205 may directly contact the front surface of the bottom substrate 100. In some embodiments, through-hole 305, through-holes 405A and 405B of the third stacked chip 500A and the fourth stacked chip 500B may have similar characteristics to those of the through-hole 305. Figure 15 The structure of the through-hole 205 shown is illustrated.

[0172] Reference Figure 17 Semiconductor element 1C can have the same characteristics as... Figure 14 A structure similar to the one shown. Figure 17 Zhongyu Figure 14 Identical or similar elements are marked with similar reference numerals, and repeated descriptions have been omitted. Semiconductor element 1C may include a plurality of connectors 701. The plurality of connectors 701 may be respectively disposed on a plurality of through-holes of a third stacked chip 500A and a fourth stacked chip 500B. In some embodiments, the plurality of connectors 701 may include a conductive material with low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or alloys thereof, and may be fabricated using appropriate processes, such as evaporation, electroplating, ball drop, or screen printing. In some embodiments, the plurality of connectors 701 may be fabricated using controlled collapse chip connection (C4) bumps via a C4 process.

[0173] In some embodiments, the plurality of connectors 701 may be solder joints. Solder joints may include materials such as tin, or other suitable materials such as silver or copper. In one embodiment, the solder joint is a tin solder joint, and the solder joint may initially form a tin layer with a thickness in the range of approximately 10 μm to 100 μm by means of an evaporation process, an electroplating process, a printing process, a solder transfer process, or a ball placement process. Once the tin layer is formed on the third stacked chip 500A and the fourth stacked chip 500B, a reflow process may be performed to shape the solder joint into the desired shape.

[0174] In some embodiments, the fabrication technique for the plurality of connectors 701 can be, for example, copper columnar bumps. These columnar bumps can be formed directly on the third stacked chip 500A and the fourth stacked chip 500B without the need for contact pads, under-bump metallization, or similar materials, thus further reducing the cost and process complexity of the semiconductor device 1C, and thus allowing for increased columnar bump density. For example, in some embodiments, the critical dimensions (e.g., spacing) of the columnar bumps can be less than approximately 5 μm, and the height of the columnar bumps can be less than approximately 10 μm. The fabrication technique for the columnar bumps can be any suitable fabrication technique, such as depositing a seed layer, optionally forming under-bump metallization, using a mask to define the shape of the columnar bumps, electrochemically plating the columnar bumps in the mask, and subsequently removing unwanted portions of the mask and seed layer. The columnar bumps can be used to electrically connect the semiconductor device 1C to other package components, such as fan-out redistribution layers, package substrates, interposers, printed circuit boards, etc.

[0175] Reference Figure 18 Semiconductor element 1D can have the same characteristics as... Figure 14 A structure similar to the one shown. Figure 18 Zhongyu Figure 14 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0176] Reference Figure 18 Multiple first dummy conductive pads 703 can be disposed in the substrate 201 and can be substantially coplanar with the rear surface of the first bottom chip 200. Multiple second dummy conductive pads 705 can be disposed in the interlayer dielectric layer 403A, can be substantially coplanar with the rear surface of the first bottom chip 200, and directly contact the multiple first dummy conductive pads 703. The multiple first dummy conductive pads 703 and multiple second dummy conductive pads 705 can be fabricated using conductive materials such as copper, aluminum, or their alloys. The multiple first dummy conductive pads 703 and multiple second dummy conductive pads 705 can provide additional metal-to-metal bonding to improve the bonding quality between the first bottom chip 200 and the first stacked chip 400A.

[0177] It should be understood that referring to a component as a "dummy" component means that when the semiconductor component is in operation, no external voltage or current is applied to the component.

[0178] Reference Figure 19 Semiconductor element 1E can have the same characteristics as... Figure 14 A structure similar to the one shown. Figure 19 Zhongyu Figure 14 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0179] Reference Figure 19 A passivation layer 101 is disposed between the bottom substrate 100 and the underlying stack. In some embodiments, the passivation layer 101 may be fabricated using polymeric materials such as polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film, or similar materials. Polymeric materials (e.g., polyimide) may possess many attractive properties, such as the ability to fill openings with high aspect ratios, a relatively low dielectric constant (approximately 3.2), a simple deposition process, reduced sharp features or steps in the underlying substrate, and high-temperature resistance after curing.

[0180] In some other embodiments, the passivation layer 101 may be a dielectric layer. The dielectric layer may include nitrides (such as silicon nitride), oxides (such as silicon oxide), oxynitrides (such as silicon nitride oxide), phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or similar materials, or combinations thereof. In some embodiments, the passivation layer 101 may be fabricated using techniques such as spin coating, lamination, deposition, or similar processes. The deposition process may include chemical vapor deposition, such as plasma-enhanced chemical vapor deposition. The process temperature of the plasma-enhanced chemical vapor deposition process may be in the range of approximately 350°C to approximately 450°C. The process pressure of the plasma-enhanced chemical vapor deposition process may be in the range of approximately 2.0 Torr to approximately 2.8 Torr. The process duration of the plasma-enhanced chemical vapor deposition process may be in the range of approximately 8 seconds to approximately 12 seconds.

[0181] Reference Figure 19 Multiple redistribution layers 707 can be disposed in the passivation layer 101 and electrically coupled to the element units of the first bottom chip 200 and the second bottom chip 300 respectively.

[0182] Generally, the fabrication techniques for multiple redistribution layers 707 may include using any suitable fabrication techniques (e.g., spin coating, sputtering processes, etc.) to form one or more dielectric layers and to form conductive features within the dielectric layers. The fabrication techniques for the conductive features may include patterning the dielectric layer (e.g., using lithography and / or etching processes) and forming the conductive features within the patterned dielectric layer (e.g., by depositing a seed layer, using a masking layer to define the shape of the conductive features, and using an electroless / electrochemical electroplating process).

[0183] The fabrication techniques for multiple redistribution layers 707 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof.

[0184] Reference Figure 20 Semiconductor element 1F can have the same characteristics as... Figure 14 A structure similar to the one shown. Figure 20 Zhongyu Figure 14 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0185] Reference Figure 20Multiple first dummy semiconductor vias 709 can be disposed in the third stacked chip 500A and the fourth stacked chip 500B. The top surfaces of the multiple first dummy semiconductor vias 709 can be substantially coplanar with the rear surfaces of the third stacked chip 500A and the fourth stacked chip 500B. Multiple second dummy semiconductor vias 711 can be disposed in the second isolation layer 607. The top surfaces of the multiple second dummy semiconductor vias 711 can be substantially coplanar with the rear surfaces of the third stacked chip 500A and the fourth stacked chip 500B. The fabrication techniques of the multiple first dummy semiconductor vias 709 and the multiple second dummy semiconductor vias 711 can be similar to those used in other applications. Figure 15 The fabrication technique of the via 205 structure shown is illustrated herein, and its description will not be repeated here. The plurality of first dummy semiconductor vias 709 and the plurality of second dummy semiconductor vias 711 are not electrically connected to any other conductive feature of the semiconductor element 1F. The plurality of first dummy semiconductor vias 709 and the plurality of second dummy semiconductor vias 711 can improve the heat dissipation capability of the semiconductor element 1F.

[0186] Reference Figure 21 Semiconductor element 1G can have the same characteristics as... Figure 14 Similar structures to those shown in the image. Figure 21 Zhongyu Figure 14 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted. In semiconductor element 1G, further layers can be formed sequentially on the second layer in a process similar to that of the first and second layers.

[0187] Reference Figure 22 Semiconductor element 1H can have the same characteristics as... Figure 14 Similar structures to those shown in the image. Figure 22 Zhongyu Figure 14 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0188] Reference Figure 22The bottom filler layer 715 can be respectively disposed between the first bottom chip 200 and the bottom substrate 100 and between the second bottom chip 300 and the bottom substrate 100 to fill the space between the bottom substrate 100 and the first bottom chip 200 and the space between the bottom substrate 100 and the second bottom chip 300. The bottom filler layer 715 can surround a plurality of bottom connectors 713, which electrically connect the bottom substrate 100 and the first bottom chip 200 and the second bottom chip 300. In some embodiments, the bottom filler layer 715 can be manufactured by curing a bottom filler material made of cross-linked organic resin and inorganic particles with a low coefficient of thermal expansion (CTE) (up to 75% by weight). In some embodiments, the bottom filler material before curing can be formulated with liquid resin (such as epoxy resin), hardener (such as acid anhydride or amine), elastomer for toughening, catalyst for promoting cross-linking, and other additives for flow modification and adhesion.

[0189] The underfill layer 715 can be firmly adhered to the bottom substrate 100, the first bottom chip 200, and the second bottom chip 300, so that the underfill layer 715 can redistribute stress and strain from CTE mismatch and mechanical shock throughout the entire chip area of ​​the first bottom chip 200 and the second bottom chip 300. Therefore, the initiation and propagation of cracks in the plurality of bottom connectors 713 can be prevented or significantly reduced. Furthermore, the underfill layer 715 can provide protection to the plurality of bottom connectors 713 to improve the mechanical integrity of the configuration of the bottom substrate 100 and the first bottom chip 200 and the second bottom chip 300; thus, the overall reliability of the configuration of the bottom substrate 100 and the first bottom chip 200 and the second bottom chip 300 can also be significantly improved. In addition, the underfill layer 715 can provide partial protection against moisture ingress and other forms of contamination.

[0190] In some embodiments, the plurality of bottom connectors 713 may comprise conductive materials with low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or alloys thereof, and may be fabricated using appropriate processes such as evaporation, electroplating, ball-drop, or screen printing. In some embodiments, the plurality of bottom connectors 713 may be controlled-collapse chip connections (i.e., C4) bumps fabricated using a C4 process.

[0191] Figures 23 to 29 This is a schematic cross-sectional view illustrating the fabrication process of a semiconductor element 1I according to another embodiment of the present disclosure.

[0192] Reference Figure 23 The bottom substrate 100 and the passivation layer 101 can respectively have similar characteristics to those of the bottom substrate 100 and the passivation layer 101. Figure 19The structure shown is described herein and will not be repeated here. Multiple conductive pads 717 may be formed in the passivation layer 101. The top surfaces of the multiple conductive pads 717 may be substantially coplanar with the top surface of the passivation layer 101. The fabrication techniques for the multiple conductive pads 717 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0193] Reference Figure 23 The first stacked chip 400A and the second stacked chip 400B can be achieved through a method similar to Figure 5 and Figure 6 The hybrid bonding process shown is directly bonded to the passivation layer 101, and its description will not be repeated here.

[0194] Reference Figure 24 The plurality of conductive pads 407A of the first stacked chip 400A and the plurality of conductive pads 407B of the second stacked chip 400B can respectively and correspondingly directly contact the plurality of conductive pads 717. A first isolation layer 603 can be conformally formed to cover the first stacked chip 400A and the second stacked chip 400B, similar to... Figure 7 The procedure shown is described herein and will not be repeated. The second gap G2 between the first stacked chip 400A and the second stacked chip 400B may be at least partially filled by the first isolation layer 603. In some embodiments, the second gap G2 may be completely filled by the first isolation layer 603.

[0195] Reference Figure 25 The rear surfaces of the first stacked chip 400A and the second stacked chip 400B can be connected by means of a similar method. Figure 8 The procedure shown is exposed, and its description will not be repeated here. Since the first isolation layer 603 completely or partially fills the second gap G2, the rear surfaces of the first stacked chip 400A and the second stacked chip 400B and the top surface of the bottom isolation layer 601 can be substantially coplanar.

[0196] Conversely, if the second gap G2 between the first stacked chip 400A and the second stacked chip 400B is not filled, the thickness uniformity may be worse, and the chip edges may become rounded. Both of these phenomena can have a serious adverse impact on subsequent processes, thus affecting the yield and quality of the fabricated semiconductor devices.

[0197] Reference Figure 26 A removal process can be performed to reduce the thickness of substrates 401A and 401B and expose multiple vias 405A and 405B of the first stacked chip 400A and the second stacked chip 400B. This removal process can be similar to... Figure 9 The procedure shown is described here and will not be repeated.

[0198] Reference Figure 27 The first capping layer 605 can be conformally formed to cover the first insulating layer 603, the substrates 401A and 401B, and the plurality of through-holes 405A and 405B, similar to Figure 10 The procedure shown is described herein and will not be repeated here.

[0199] Reference Figure 28 Planarization processes, such as chemical mechanical polishing, can be performed until the top surfaces of the multiple through-holes 405A and 405B are exposed to remove excess material and provide a basically flat surface for subsequent process steps.

[0200] Reference Figure 29 The fabrication technology for the third-layer stacked chip 500A, the fourth-layer stacked chip 500B, and more layers can be similar to... Figures 12 to 14 The procedure shown is described here and will not be repeated.

[0201] One embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a bottom substrate; bonding a first stacked chip and a second stacked chip to the bottom substrate; conformally forming a first isolation layer to cover the first stacked chip and the second stacked chip, and at least partially filling a gap between the first stacked chip and the second stacked chip; performing a thinning process to expose a back surface of the first stacked chip and the second stacked chip; performing a removal process to expose a via of the first stacked chip and a via of the second stacked chip; forming a first capping layer to cover the via of the first stacked chip and the via of the second stacked chip; and performing a planarization process to expose the via of the first stacked chip and the via of the second stacked chip, and providing a substantially flat surface.

[0202] Another embodiment of this disclosure provides a semiconductor device, including: a bottom substrate; a first stacked chip and a second stacked chip disposed on the bottom substrate; a first isolation layer disposed on the bottom substrate and surrounding the first stacked chip and the second stacked chip; and a first capping layer disposed on a rear surface of the first stacked chip and surrounding a through-hole of the first stacked chip. A vertical height of a top surface of the first isolation layer is higher than a vertical height of a rear surface of the first stacked chip. A top surface of the through-hole of the first stacked chip, a top surface of the first isolation layer, and a top surface of the first capping layer are substantially coplanar.

[0203] Due to the design of the semiconductor device disclosed herein, the thickness uniformity and edge profile of the chip can be improved. Therefore, the yield, quality, and performance of the semiconductor device can be improved.

[0204] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0205] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, preparations, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, preparations, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, preparations, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a bottom base; A first stacked chip and a second stacked chip are bonded to the bottom substrate; A first isolation layer is conformally formed to cover the first stacked chip and the second stacked chip, and to at least partially fill a gap between the first stacked chip and the second stacked chip; A thinning process is performed to expose a back surface of the first stacked chip and the second stacked chip; Perform a removal process to expose a via of the first stacked chip and a via of the second stacked chip; A first capping layer is formed to cover the via of the first stacked chip and the via of the second stacked chip; Perform a planarization process to expose the vias of the first stacked chip and the second stacked chip, and provide a substantially flat surface; as well as A third stacked chip is bonded to the first stacked chip, and a fourth stacked chip is bonded to the second stacked chip. The first stacked chip and the second stacked chip include a storage circuit.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein the removal process is a dry etching process.

3. The method for fabricating a semiconductor element as claimed in claim 2, wherein the etching rate ratio of the first isolation layer to the dry etching process of the first stacked chip substrate is in the range of 15:1 to 2:

1.

4. The method for fabricating a semiconductor device as claimed in claim 3, wherein the first stacked chip and the second stacked chip are bonded to the bottom substrate by a hybrid bonding process.

5. The method for fabricating a semiconductor device as claimed in claim 4, wherein a process pressure of the hybrid bonding process is in the range of 100 MPa to 150 MPa.

6. The method for fabricating a semiconductor device as claimed in claim 5, wherein a process temperature of the hybrid bonding process is in the range of 25°C to 400°C.

7. The method for fabricating a semiconductor element as described in claim 6 further includes a thermal annealing process after the first stacked chip and the second stacked chip are bonded to the bottom substrate.

8. The method for fabricating a semiconductor device as described in claim 7, wherein the first isolation layer comprises an oxide layer, a nitride layer, or an oxynitride layer.

9. The method for fabricating a semiconductor device as described in claim 8, wherein the first capping layer comprises an oxide layer, a nitride layer, or an oxynitride layer.

10. The method for fabricating a semiconductor element as claimed in claim 9, wherein the first stacked chip includes a logic circuit, and the third stacked chip includes a memory circuit.

11. A semiconductor element, comprising: A bottom base; A first stacked chip and a second stacked chip are disposed on the bottom substrate; A first isolation layer is disposed on the bottom substrate and surrounds the first stacked chip and the second stacked chip, wherein a vertical height of a top surface of the first isolation layer is higher than a vertical height of a rear surface of the first stacked chip; A first capping layer is disposed on the rear surface of the first stacked chip and surrounds a through-hole of the first stacked chip, wherein a top surface of the through-hole of the first stacked chip, a top surface of the first isolation layer, and a top surface of the first capping layer are substantially coplanar. A third stacked chip and a fourth stacked chip are respectively disposed on the first stacked chip and on the second stacked chip; Multiple first dummy conductive pads are disposed in the first stacked chip; as well as Multiple second dummy conductive pads are disposed in the third stacked chip, wherein the second dummy conductive pads respectively contact the first dummy conductive pad.

12. The semiconductor element of claim 11, wherein the thickness of the first stacked chip is equal to or less than 10 nm (nanometer).

13. The semiconductor device of claim 12, wherein the first stacked chip and the third stacked chip include a memory circuit.

14. The semiconductor device of claim 12, wherein the first stacked chip includes a logic circuit and the third stacked chip includes a memory circuit.

15. The semiconductor element of claim 12, further comprising a plurality of connectors disposed on a rear surface of the third stacked chip and the fourth stacked chip.

16. The semiconductor device of claim 12, further comprising a redistribution layer disposed in the bottom substrate, wherein the first stacked chip and the second stacked chip are electrically coupled to the redistribution layer, respectively.

17. The semiconductor device of claim 16, wherein a conductive pad of the first stacked chip is in direct contact with the redistribution layer.

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